410 lines
16 KiB
C++
410 lines
16 KiB
C++
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#include "log.h"
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#include "nextpnr.h"
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#define HIMBAECHEL_CONSTIDS "uarch/gowin/constids.inc"
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#include "himbaechel_constids.h"
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#include "himbaechel_helpers.h"
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#include "gowin.h"
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#include "pack.h"
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NEXTPNR_NAMESPACE_BEGIN
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namespace {
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struct GowinPacker
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{
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Context *ctx;
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HimbaechelHelpers h;
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GowinPacker(Context *ctx) : ctx(ctx) { h.init(ctx); }
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// ===================================
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// IO
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// ===================================
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void pack_iobs(void)
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{
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log_info("Pack IOBs...\n");
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// Trim nextpnr IOBs - assume IO buffer insertion has been done in synthesis
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const pool<CellTypePort> top_ports{
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CellTypePort(id_IBUF, id_I),
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CellTypePort(id_OBUF, id_O),
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};
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h.remove_nextpnr_iobs(top_ports);
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}
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// ===================================
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// Constant nets
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// ===================================
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void handle_constants(void)
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{
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log_info("Create constant nets...\n");
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const dict<IdString, Property> vcc_params;
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const dict<IdString, Property> gnd_params;
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h.replace_constants(CellTypePort(id_GOWIN_VCC, id_V), CellTypePort(id_GOWIN_GND, id_G), vcc_params, gnd_params);
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// disconnect the constant LUT inputs
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log_info("Modify LUTs...\n");
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for (IdString netname : {ctx->id("$PACKER_GND"), ctx->id("$PACKER_VCC")}) {
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auto net = ctx->nets.find(netname);
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if (net == ctx->nets.end()) {
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continue;
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}
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NetInfo *constnet = net->second.get();
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for (auto user : constnet->users) {
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CellInfo *uc = user.cell;
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if (ctx->debug)
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log_info("%s user %s/%s\n", ctx->nameOf(constnet), ctx->nameOf(uc), user.port.c_str(ctx));
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if (is_lut(uc) && (user.port.str(ctx).at(0) == 'I')) {
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auto it_param = uc->params.find(id_INIT);
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if (it_param == uc->params.end())
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log_error("No initialization for lut found.\n");
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int64_t uc_init = it_param->second.intval;
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int64_t mask = 0;
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uint8_t amt = 0;
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if (user.port == id_I0) {
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mask = 0x5555;
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amt = 1;
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} else if (user.port == id_I1) {
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mask = 0x3333;
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amt = 2;
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} else if (user.port == id_I2) {
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mask = 0x0F0F;
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amt = 4;
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} else if (user.port == id_I3) {
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mask = 0x00FF;
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amt = 8;
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} else {
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log_error("Port number invalid.\n");
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}
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if ((constnet->name == ctx->id("$PACKER_GND"))) {
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uc_init = (uc_init & mask) | ((uc_init & mask) << amt);
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} else {
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uc_init = (uc_init & (mask << amt)) | ((uc_init & (mask << amt)) >> amt);
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}
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size_t uc_init_len = it_param->second.to_string().length();
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uc_init &= (1LL << uc_init_len) - 1;
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if (ctx->verbose && it_param->second.intval != uc_init)
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log_info("%s lut config modified from 0x%lX to 0x%lX\n", ctx->nameOf(uc),
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it_param->second.intval, uc_init);
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it_param->second = Property(uc_init, uc_init_len);
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uc->disconnectPort(user.port);
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}
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}
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}
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}
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// ===================================
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// Wideluts
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// ===================================
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void pack_wideluts(void)
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{
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log_info("Pack wide LUTs...\n");
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// children's offsets
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struct _children
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{
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IdString port;
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int dx, dz;
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} mux_inputs[4][2] = {{{id_I0, 1, -7}, {id_I1, 0, -7}},
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{{id_I0, 0, 4}, {id_I1, 0, -4}},
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{{id_I0, 0, 2}, {id_I1, 0, -2}},
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{{id_I0, 0, -BelZ::MUX20_Z}, {id_I1, 0, 2 - BelZ::MUX20_Z}}};
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typedef std::function<void(CellInfo &, CellInfo *, int, int)> recurse_func_t;
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recurse_func_t make_cluster = [&, this](CellInfo &ci_root, CellInfo *ci_cursor, int dx, int dz) {
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_children *inputs;
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if (is_lut(ci_cursor)) {
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return;
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}
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switch (ci_cursor->type.hash()) {
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case ID_MUX2_LUT8:
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inputs = mux_inputs[0];
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break;
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case ID_MUX2_LUT7:
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inputs = mux_inputs[1];
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break;
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case ID_MUX2_LUT6:
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inputs = mux_inputs[2];
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break;
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case ID_MUX2_LUT5:
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inputs = mux_inputs[3];
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break;
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default:
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log_error("Bad MUX2 node:%s\n", ctx->nameOf(ci_cursor));
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}
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for (int i = 0; i < 2; ++i) {
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// input src
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NetInfo *in = ci_cursor->getPort(inputs[i].port);
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NPNR_ASSERT(in && in->driver.cell);
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int child_dx = dx + inputs[i].dx;
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int child_dz = dz + inputs[i].dz;
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ci_root.constr_children.push_back(in->driver.cell);
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in->driver.cell->cluster = ci_root.name;
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in->driver.cell->constr_abs_z = false;
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in->driver.cell->constr_x = child_dx;
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in->driver.cell->constr_y = 0;
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in->driver.cell->constr_z = child_dz;
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make_cluster(ci_root, in->driver.cell, child_dx, child_dz);
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}
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};
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// look for MUX2
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// MUX2_LUT8 create right away, collect others
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std::vector<IdString> muxes[3];
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int packed[4] = {0, 0, 0, 0};
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for (auto &cell : ctx->cells) {
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auto &ci = *cell.second;
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if (ci.cluster != ClusterId()) {
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continue;
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}
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if (ci.type == id_MUX2_LUT8) {
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ci.cluster = ci.name;
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ci.constr_abs_z = false;
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make_cluster(ci, &ci, 0, 0);
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++packed[0];
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continue;
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}
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if (ci.type.in(id_MUX2_LUT7, id_MUX2_LUT6, id_MUX2_LUT5)) {
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switch (ci.type.hash()) {
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case ID_MUX2_LUT7:
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muxes[0].push_back(cell.first);
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break;
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case ID_MUX2_LUT6:
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muxes[1].push_back(cell.first);
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break;
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default: // ID_MUX2_LUT5
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muxes[2].push_back(cell.first);
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break;
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}
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}
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}
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// create others
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for (int i = 0; i < 3; ++i) {
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for (IdString cell_name : muxes[i]) {
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auto &ci = *ctx->cells.at(cell_name);
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if (ci.cluster != ClusterId()) {
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continue;
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}
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ci.cluster = ci.name;
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ci.constr_abs_z = false;
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make_cluster(ci, &ci, 0, 0);
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++packed[i + 1];
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}
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}
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log_info("Packed MUX2_LUT8:%d, MUX2_LU7:%d, MUX2_LUT6:%d, MUX2_LUT5:%d\n", packed[0], packed[1], packed[2],
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packed[3]);
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}
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// ===================================
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// ALU
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// ===================================
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// create ALU CIN block
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std::unique_ptr<CellInfo> alu_add_cin_block(Context *ctx, CellInfo *head, NetInfo *cin_net)
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{
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std::string name = head->name.str(ctx) + "_HEAD_ALULC";
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IdString name_id = ctx->id(name);
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NetInfo *cout_net = ctx->createNet(name_id);
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head->disconnectPort(id_CIN);
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head->connectPort(id_CIN, cout_net);
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auto cin_ci = std::make_unique<CellInfo>(ctx, name_id, id_ALU);
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cin_ci->addOutput(id_COUT);
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cin_ci->connectPort(id_COUT, cout_net);
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if (cin_net->name == ctx->id("$PACKER_GND")) {
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cin_ci->params[id_ALU_MODE] = std::string("C2L");
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return cin_ci;
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}
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if (cin_net->name == ctx->id("$PACKER_VCC")) {
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cin_ci->params[id_ALU_MODE] = std::string("ONE2C");
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return cin_ci;
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}
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// CIN from logic
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cin_ci->addInput(id_I1);
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cin_ci->addInput(id_I3);
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cin_ci->addInput(id_I2);
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cin_ci->connectPort(id_I1, cin_net);
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cin_ci->connectPort(id_I3, cin_net);
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cin_ci->connectPort(id_I2, ctx->nets[ctx->id("$PACKER_VCC")].get());
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cin_ci->params[id_ALU_MODE] = std::string("0"); // ADD
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return cin_ci;
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}
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// create ALU COUT block
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std::unique_ptr<CellInfo> alu_add_cout_block(Context *ctx, CellInfo *tail, NetInfo *cout_net)
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{
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std::string name = tail->name.str(ctx) + "_TAIL_ALULC";
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IdString name_id = ctx->id(name);
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NetInfo *cin_net = ctx->createNet(name_id);
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tail->disconnectPort(id_COUT);
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tail->connectPort(id_COUT, cin_net);
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auto cout_ci = std::make_unique<CellInfo>(ctx, name_id, id_ALU);
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cout_ci->addOutput(id_COUT); // may be needed for the ALU filler
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cout_ci->addInput(id_CIN);
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cout_ci->connectPort(id_CIN, cin_net);
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cout_ci->addOutput(id_SUM);
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cout_ci->connectPort(id_SUM, cout_net);
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cout_ci->params[id_ALU_MODE] = std::string("C2L");
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return cout_ci;
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}
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// create ALU filler block
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std::unique_ptr<CellInfo> alu_add_dummy_block(Context *ctx, CellInfo *tail)
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{
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std::string name = tail->name.str(ctx) + "_DUMMY_ALULC";
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IdString name_id = ctx->id(name);
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auto dummy_ci = std::make_unique<CellInfo>(ctx, name_id, id_ALU);
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dummy_ci->params[id_ALU_MODE] = std::string("C2L");
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return dummy_ci;
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}
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// create ALU chain
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void pack_alus(void)
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{
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static CellTypePort cell_alu_cout = CellTypePort(id_ALU, id_COUT);
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static CellTypePort cell_alu_cin = CellTypePort(id_ALU, id_CIN);
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std::vector<std::unique_ptr<CellInfo>> new_cells;
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log_info("Pack ALUs...\n");
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for (auto &cell : ctx->cells) {
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auto ci = cell.second.get();
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if (ci->cluster != ClusterId()) {
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continue;
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}
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if (is_alu(ci)) {
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// The ALU head is when the input carry is not a dedicated wire from the previous ALU
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NetInfo *cin_net = ci->getPort(id_CIN);
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if (!cin_net || !cin_net->driver.cell) {
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log_error("CIN disconnected at ALU:%s\n", ctx->nameOf(ci));
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}
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if (CellTypePort(cin_net->driver) != cell_alu_cout || cin_net->users.entries() > 1) {
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if (ctx->debug) {
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log_info("ALU head found %s. CIN net is %s\n", ctx->nameOf(ci), ctx->nameOf(cin_net));
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}
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// always prepend first ALU with carry generator block
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// three cases: CIN == 0, CIN == 1 and CIN == ?
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new_cells.push_back(std::move(alu_add_cin_block(ctx, ci, cin_net)));
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CellInfo *cin_block_ci = new_cells.back().get();
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// CIN block is the cluster root and is always placed in ALU0
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// This is a possible place for further optimization
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cin_block_ci->cluster = cin_block_ci->name;
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cin_block_ci->constr_z = BelZ::ALU0_Z;
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cin_block_ci->constr_abs_z = true;
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int alu_chain_len = 1;
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while (true) {
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// add to cluster
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if (ctx->debug) {
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log_info("Add ALU to the chain (len:%d): %s\n", alu_chain_len, ctx->nameOf(ci));
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}
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cin_block_ci->constr_children.push_back(ci);
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ci->cluster = cin_block_ci->name;
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ci->constr_abs_z = false;
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ci->constr_x = alu_chain_len / 6;
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ci->constr_y = 0;
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ci->constr_z = alu_chain_len % 6;
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// XXX I2 is pin C which must be set to 1 for all ALU modes except MUL
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// we use only mode 2 ADDSUB so create and connect this pin
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ci->addInput(id_I2);
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ci->connectPort(id_I2, ctx->nets[ctx->id("$PACKER_VCC")].get());
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++alu_chain_len;
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// check for the chain end
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NetInfo *cout_net = ci->getPort(id_COUT);
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if (!cout_net || cout_net->users.empty()) {
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break;
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}
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if (CellTypePort(*cout_net->users.begin()) != cell_alu_cin || cout_net->users.entries() > 1) {
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new_cells.push_back(std::move(alu_add_cout_block(ctx, ci, cout_net)));
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CellInfo *cout_block_ci = new_cells.back().get();
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cin_block_ci->constr_children.push_back(cout_block_ci);
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cout_block_ci->cluster = cin_block_ci->name;
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cout_block_ci->constr_abs_z = false;
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cout_block_ci->constr_x = alu_chain_len / 6;
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cout_block_ci->constr_y = 0;
|
||
|
|
cout_block_ci->constr_z = alu_chain_len % 6;
|
||
|
|
if (ctx->debug) {
|
||
|
|
log_info("Add ALU carry out to the chain (len:%d): %s\n", alu_chain_len,
|
||
|
|
ctx->nameOf(cout_block_ci));
|
||
|
|
}
|
||
|
|
|
||
|
|
++alu_chain_len;
|
||
|
|
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
ci = (*cout_net->users.begin()).cell;
|
||
|
|
}
|
||
|
|
// ALUs are always paired
|
||
|
|
if (alu_chain_len & 1) {
|
||
|
|
// create dummy cell
|
||
|
|
new_cells.push_back(std::move(alu_add_dummy_block(ctx, ci)));
|
||
|
|
CellInfo *dummy_block_ci = new_cells.back().get();
|
||
|
|
cin_block_ci->constr_children.push_back(dummy_block_ci);
|
||
|
|
dummy_block_ci->cluster = cin_block_ci->name;
|
||
|
|
dummy_block_ci->constr_abs_z = false;
|
||
|
|
dummy_block_ci->constr_x = alu_chain_len / 6;
|
||
|
|
dummy_block_ci->constr_y = 0;
|
||
|
|
dummy_block_ci->constr_z = alu_chain_len % 6;
|
||
|
|
if (ctx->debug) {
|
||
|
|
log_info("Add ALU dummy cell to the chain (len:%d): %s\n", alu_chain_len,
|
||
|
|
ctx->nameOf(dummy_block_ci));
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
for (auto &ncell : new_cells) {
|
||
|
|
ctx->cells[ncell->name] = std::move(ncell);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
// ===================================
|
||
|
|
// glue LUT and FF
|
||
|
|
// ===================================
|
||
|
|
void constrain_lutffs(void)
|
||
|
|
{
|
||
|
|
// Constrain directly connected LUTs and FFs together to use dedicated resources
|
||
|
|
auto lut_outs = pool<CellTypePort>{{id_LUT1, id_F}, {id_LUT2, id_F}, {id_LUT3, id_F}, {id_LUT4, id_F}};
|
||
|
|
auto dff_ins = pool<CellTypePort>{{id_DFF, id_D}, {id_DFFE, id_D}, {id_DFFN, id_D}, {id_DFFNE, id_D},
|
||
|
|
{id_DFFS, id_D}, {id_DFFSE, id_D}, {id_DFFNS, id_D}, {id_DFFNSE, id_D},
|
||
|
|
{id_DFFR, id_D}, {id_DFFRE, id_D}, {id_DFFNR, id_D}, {id_DFFNRE, id_D},
|
||
|
|
{id_DFFP, id_D}, {id_DFFPE, id_D}, {id_DFFNP, id_D}, {id_DFFNPE, id_D},
|
||
|
|
{id_DFFC, id_D}, {id_DFFCE, id_D}, {id_DFFNC, id_D}, {id_DFFNCE, id_D}};
|
||
|
|
|
||
|
|
int lutffs = h.constrain_cell_pairs(lut_outs, dff_ins, 1);
|
||
|
|
log_info("Constrained %d LUTFF pairs.\n", lutffs);
|
||
|
|
|
||
|
|
log_info("Pack ALUs...\n");
|
||
|
|
pack_alus();
|
||
|
|
}
|
||
|
|
|
||
|
|
void run(void)
|
||
|
|
{
|
||
|
|
pack_iobs();
|
||
|
|
handle_constants();
|
||
|
|
pack_wideluts();
|
||
|
|
pack_alus();
|
||
|
|
constrain_lutffs();
|
||
|
|
}
|
||
|
|
};
|
||
|
|
} // namespace
|
||
|
|
|
||
|
|
void gowin_pack(Context *ctx)
|
||
|
|
{
|
||
|
|
GowinPacker packer(ctx);
|
||
|
|
packer.run();
|
||
|
|
}
|
||
|
|
|
||
|
|
NEXTPNR_NAMESPACE_END
|