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[interchange] Update to v6 of FPGA interchange chipdb.

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Changes:
 - Adds LUT output pin to LutBelPOD.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
This commit is contained in:
Keith Rothman 2021-04-01 15:16:23 -07:00
parent ec98fee1ee
commit 009d3b64b6
3 changed files with 12 additions and 2 deletions
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7
fpga_interchange/arch.cc
View File

@ -247,10 +247,13 @@ Arch::Arch(ArchArgs args) : args(args)
LutElement &element = elements.back();
element.width = lut_element.width;
for (auto &lut_bel : lut_element.lut_bels) {
auto result = element.lut_bels.emplace(IdString(lut_bel.name), LutBel());
IdString name(lut_bel.name);
auto result = element.lut_bels.emplace(name, LutBel());
NPNR_ASSERT(result.second);
LutBel &lut = result.first->second;
lut.name = name;
lut.low_bit = lut_bel.low_bit;
lut.high_bit = lut_bel.high_bit;
@ -260,6 +263,8 @@ Arch::Arch(ArchArgs args) : args(args)
lut.pins.push_back(pin);
lut.pin_to_index[pin] = i;
}
lut.output_pin = IdString(lut_bel.out_pin);
}
element.compute_pin_order();

3
fpga_interchange/chipdb.h
View File

@ -34,7 +34,7 @@ NEXTPNR_NAMESPACE_BEGIN
* kExpectedChipInfoVersion
*/
static constexpr int32_t kExpectedChipInfoVersion = 5;
static constexpr int32_t kExpectedChipInfoVersion = 6;
// Flattened site indexing.
//
@ -133,6 +133,7 @@ NPNR_PACKED_STRUCT(struct LutBelPOD {
RelSlice<int32_t> pins; // constid
uint32_t low_bit;
uint32_t high_bit;
int32_t out_pin; // constid
});
NPNR_PACKED_STRUCT(struct LutElementPOD {

4
fpga_interchange/luts.h
View File

@ -51,10 +51,14 @@ struct LutCell
struct LutBel
{
IdString name;
// LUT BEL pins to LUT array index.
std::vector<IdString> pins;
std::unordered_map<IdString, size_t> pin_to_index;
IdString output_pin;
// What part of the LUT equation does this LUT output use?
// This assumes contiguous LUT bits.
uint32_t low_bit;