Merge pull request #242 from YosysHQ/ecp5next
ecp5: Fixes and QoR improvements
This commit is contained in:
David Shah
GitHub
commit
031725c80e
@ -611,8 +611,9 @@ struct Timing
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continue;
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delay_t dmax = crit_path->at(ClockPair{startdomain.first, startdomain.first}).path_delay;
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for (size_t i = 0; i < net->users.size(); i++) {
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float criticality = 1.0f - (float(nc.slack.at(i) - worst_slack.at(startdomain.first)) / dmax);
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nc.criticality.at(i) = criticality;
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float criticality =
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1.0f - ((float(nc.slack.at(i)) - float(worst_slack.at(startdomain.first))) / dmax);
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nc.criticality.at(i) = std::min<double>(1.0, std::max<double>(0.0, criticality));
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}
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nc.max_path_length = nd.max_path_length;
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nc.cd_worst_slack = worst_slack.at(startdomain.first);
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@ -837,6 +838,10 @@ void timing_analysis(Context *ctx, bool print_histogram, bool print_fmax, bool p
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auto cursor = sink_wire;
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delay_t delay;
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while (driver_wire != cursor) {
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#ifdef ARCH_ECP5
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if (net->is_global)
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break;
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#endif
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auto it = net->wires.find(cursor);
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assert(it != net->wires.end());
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auto pip = it->second.pip;
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91
ecp5/arch.cc
91
ecp5/arch.cc
@ -427,44 +427,90 @@ BelId Arch::getBelByLocation(Loc loc) const
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delay_t Arch::estimateDelay(WireId src, WireId dst) const
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{
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auto est_location = [&](WireId w) -> std::pair<int16_t, int16_t> {
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if (w.location.x == 0 && w.location.y == 0) {
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// Global wires
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const auto &wire = locInfo(w)->wire_data[w.index];
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// Use location of first downhill bel or pip, if available
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if (wire.num_bel_pins > 0) {
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return std::make_pair(wire.bel_pins[0].rel_bel_loc.x, wire.bel_pins[0].rel_bel_loc.y);
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} else if (wire.num_downhill > 0) {
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return std::make_pair(wire.pips_downhill[0].rel_loc.x, wire.pips_downhill[0].rel_loc.y);
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} else if (wire.num_uphill > 0) {
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return std::make_pair(wire.pips_uphill[0].rel_loc.x, wire.pips_uphill[0].rel_loc.y);
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} else {
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return std::make_pair<int16_t, int16_t>(0, 0);
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}
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WireId cursor = dst;
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int num_uh = locInfo(dst)->wire_data[dst.index].num_uphill;
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if (num_uh < 6) {
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for (auto uh : getPipsUphill(dst)) {
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if (getPipSrcWire(uh) == src)
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return getPipDelay(uh).maxDelay();
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}
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}
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auto est_location = [&](WireId w) -> std::pair<int, int> {
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const auto &wire = locInfo(w)->wire_data[w.index];
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if (wire.num_bel_pins > 0) {
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return std::make_pair(w.location.x + wire.bel_pins[0].rel_bel_loc.x,
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w.location.y + wire.bel_pins[0].rel_bel_loc.y);
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} else if (wire.num_downhill > 0) {
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return std::make_pair(w.location.x + wire.pips_downhill[0].rel_loc.x,
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w.location.y + wire.pips_downhill[0].rel_loc.y);
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} else if (wire.num_uphill > 0) {
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return std::make_pair(w.location.x + wire.pips_uphill[0].rel_loc.x,
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w.location.y + wire.pips_uphill[0].rel_loc.y);
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} else {
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return std::make_pair(w.location.x, w.location.y);
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return std::make_pair(int(w.location.x), int(w.location.y));
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}
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};
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auto src_loc = est_location(src), dst_loc = est_location(dst);
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return (240 - 20 * args.speed) * (abs(src_loc.first - dst_loc.first) + abs(src_loc.second - dst_loc.second));
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int dx = abs(src_loc.first - dst_loc.first), dy = abs(src_loc.second - dst_loc.second);
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return (130 - 25 * args.speed) *
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(6 + std::max(dx - 5, 0) + std::max(dy - 5, 0) + 2 * (std::min(dx, 5) + std::min(dy, 5)));
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}
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delay_t Arch::predictDelay(const NetInfo *net_info, const PortRef &sink) const
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{
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const auto &driver = net_info->driver;
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if ((driver.port == id_FCO && sink.port == id_FCI) || sink.port == id_FXA || sink.port == id_FXB)
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return 0;
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auto driver_loc = getBelLocation(driver.cell->bel);
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auto sink_loc = getBelLocation(sink.cell->bel);
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return (240 - 20 * args.speed) * (abs(driver_loc.x - sink_loc.x) + abs(driver_loc.y - sink_loc.y));
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// Encourage use of direct interconnect
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if (driver_loc.x == sink_loc.x && driver_loc.y == sink_loc.y) {
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if ((sink.port == id_A0 || sink.port == id_A1) && (driver.port == id_F1) &&
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(driver_loc.z == 2 || driver_loc.z == 3))
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return 0;
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if ((sink.port == id_B0 || sink.port == id_B1) && (driver.port == id_F1) &&
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(driver_loc.z == 0 || driver_loc.z == 1))
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return 0;
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if ((sink.port == id_C0 || sink.port == id_C1) && (driver.port == id_F0) &&
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(driver_loc.z == 2 || driver_loc.z == 3))
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return 0;
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if ((sink.port == id_D0 || sink.port == id_D1) && (driver.port == id_F0) &&
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(driver_loc.z == 0 || driver_loc.z == 1))
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return 0;
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}
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int dx = abs(driver_loc.x - sink_loc.x), dy = abs(driver_loc.y - sink_loc.y);
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return (130 - 25 * args.speed) *
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(6 + std::max(dx - 5, 0) + std::max(dy - 5, 0) + 2 * (std::min(dx, 5) + std::min(dy, 5)));
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}
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bool Arch::getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t &budget) const { return false; }
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bool Arch::getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t &budget) const
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{
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if (net_info->driver.port == id_FCO && sink.port == id_FCI) {
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budget = 0;
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return true;
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} else if (sink.port == id_FXA || sink.port == id_FXB) {
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budget = 0;
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return true;
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} else {
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return false;
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}
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}
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// -----------------------------------------------------------------------
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bool Arch::place() { return placer1(getCtx(), Placer1Cfg(getCtx())); }
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bool Arch::place()
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{
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bool result = placer1(getCtx(), Placer1Cfg(getCtx()));
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if (result)
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permute_luts();
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return result;
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}
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bool Arch::route()
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{
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@ -602,7 +648,7 @@ bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort
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// Data for -8 grade
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if (cell->type == id_TRELLIS_SLICE) {
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bool has_carry = str_or_default(cell->params, id("MODE"), "LOGIC") == "CCU2";
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bool has_carry = cell->sliceInfo.is_carry;
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if (fromPort == id_A0 || fromPort == id_B0 || fromPort == id_C0 || fromPort == id_D0 || fromPort == id_A1 ||
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fromPort == id_B1 || fromPort == id_C1 || fromPort == id_D1 || fromPort == id_M0 || fromPort == id_M1 ||
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fromPort == id_FXA || fromPort == id_FXB || fromPort == id_FCI) {
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@ -639,7 +685,7 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, in
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auto disconnected = [cell](IdString p) { return !cell->ports.count(p) || cell->ports.at(p).net == nullptr; };
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clockInfoCount = 0;
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if (cell->type == id_TRELLIS_SLICE) {
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int sd0 = int_or_default(cell->params, id("REG0_SD"), 0), sd1 = int_or_default(cell->params, id("REG1_SD"), 0);
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int sd0 = cell->sliceInfo.sd0, sd1 = cell->sliceInfo.sd1;
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if (port == id_CLK || port == id_WCK)
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return TMG_CLOCK_INPUT;
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if (port == id_A0 || port == id_A1 || port == id_B0 || port == id_B1 || port == id_C0 || port == id_C1 ||
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@ -782,8 +828,7 @@ TimingClockingInfo Arch::getPortClockingInfo(const CellInfo *cell, IdString port
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info.hold = getDelayFromNS(0);
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info.clockToQ = getDelayFromNS(0);
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if (cell->type == id_TRELLIS_SLICE) {
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int sd0 = int_or_default(cell->params, id("REG0_SD"), 0), sd1 = int_or_default(cell->params, id("REG1_SD"), 0);
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int sd0 = cell->sliceInfo.sd0, sd1 = cell->sliceInfo.sd1;
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if (port == id_WD0 || port == id_WD1 || port == id_WAD0 || port == id_WAD1 || port == id_WAD2 ||
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port == id_WAD3 || port == id_WRE) {
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info.edge = RISING_EDGE;
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@ -918,7 +918,7 @@ struct Arch : BaseCtx
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delay_t estimateDelay(WireId src, WireId dst) const;
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delay_t predictDelay(const NetInfo *net_info, const PortRef &sink) const;
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delay_t getDelayEpsilon() const { return 20; }
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delay_t getRipupDelayPenalty() const { return 200; }
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delay_t getRipupDelayPenalty() const { return 250; }
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float getDelayNS(delay_t v) const { return v * 0.001; }
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DelayInfo getDelayFromNS(float ns) const
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{
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@ -971,6 +971,8 @@ struct Arch : BaseCtx
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void assignArchInfo();
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void permute_luts();
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std::vector<std::pair<std::string, std::string>> getTilesAtLocation(int row, int col);
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std::string getTileByTypeAndLocation(int row, int col, std::string type) const
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{
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@ -18,8 +18,10 @@
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*/
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#include "cells.h"
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#include "design_utils.h"
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#include "log.h"
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#include "nextpnr.h"
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#include "timing.h"
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#include "util.h"
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NEXTPNR_NAMESPACE_BEGIN
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@ -115,4 +117,76 @@ bool Arch::isValidBelForCell(CellInfo *cell, BelId bel) const
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}
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}
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void Arch::permute_luts()
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{
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NetCriticalityMap nc;
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get_criticalities(getCtx(), &nc);
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std::unordered_map<PortInfo *, size_t> port_to_user;
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for (auto net : sorted(nets)) {
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NetInfo *ni = net.second;
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for (size_t i = 0; i < ni->users.size(); i++) {
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auto &usr = ni->users.at(i);
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port_to_user[&(usr.cell->ports.at(usr.port))] = i;
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}
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}
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auto proc_lut = [&](CellInfo *ci, int lut) {
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std::vector<IdString> port_names;
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for (int i = 0; i < 4; i++)
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port_names.push_back(id(std::string("ABCD").substr(i, 1) + std::to_string(lut)));
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std::vector<std::pair<float, int>> inputs;
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std::vector<NetInfo *> orig_nets;
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for (int i = 0; i < 4; i++) {
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auto &port = ci->ports.at(port_names.at(i));
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float crit = 0;
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if (port.net != nullptr && nc.count(port.net->name)) {
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auto &n = nc.at(port.net->name);
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size_t usr = port_to_user.at(&port);
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if (usr < n.criticality.size())
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crit = n.criticality.at(usr);
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}
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orig_nets.push_back(port.net);
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inputs.emplace_back(crit, i);
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}
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// Least critical first (A input is slowest)
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std::sort(inputs.begin(), inputs.end());
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for (int i = 0; i < 4; i++) {
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IdString p = port_names.at(i);
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// log_info("%s %s %f\n", p.c_str(ctx), port_names.at(inputs.at(i).second).c_str(ctx), inputs.at(i).first);
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disconnect_port(getCtx(), ci, p);
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ci->ports.at(p).net = nullptr;
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if (orig_nets.at(inputs.at(i).second) != nullptr) {
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connect_port(getCtx(), orig_nets.at(inputs.at(i).second), ci, p);
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ci->params[id(p.str(this) + "MUX")] = p.str(this);
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} else {
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ci->params[id(p.str(this) + "MUX")] = "1";
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}
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}
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// Rewrite function
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int old_init = int_or_default(ci->params, id("LUT" + std::to_string(lut) + "_INITVAL"), 0);
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int new_init = 0;
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for (int i = 0; i < 16; i++) {
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int old_index = 0;
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for (int k = 0; k < 4; k++) {
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if (i & (1 << k))
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old_index |= (1 << inputs.at(k).second);
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}
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if (old_init & (1 << old_index))
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new_init |= (1 << i);
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}
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ci->params[id("LUT" + std::to_string(lut) + "_INITVAL")] = std::to_string(new_init);
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};
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for (auto cell : sorted(cells)) {
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CellInfo *ci = cell.second;
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if (ci->type == id_TRELLIS_SLICE && str_or_default(ci->params, id("MODE"), "LOGIC") == "LOGIC") {
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proc_lut(ci, 0);
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proc_lut(ci, 1);
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}
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}
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}
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NEXTPNR_NAMESPACE_END
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@ -159,7 +159,9 @@ struct ArchCellInfo
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{
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bool using_dff;
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bool has_l6mux;
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bool is_carry;
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IdString clk_sig, lsr_sig, clkmux, lsrmux, srmode;
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int sd0, sd1;
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} sliceInfo;
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};
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@ -448,6 +448,8 @@ class Ecp5GlobalRouter
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if (i < 8)
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fab_globals.insert(i);
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}
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std::vector<std::pair<PortRef *, int>> toroute;
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std::unordered_map<int, NetInfo *> clocks;
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for (auto cell : sorted(ctx->cells)) {
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CellInfo *ci = cell.second;
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if (ci->type == id_DCCA) {
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@ -472,15 +474,18 @@ class Ecp5GlobalRouter
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NPNR_ASSERT(routed);
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// WCK must have routing priority
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auto sorted_users = clock->users;
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std::sort(sorted_users.begin(), sorted_users.end(), [this](const PortRef &a, const PortRef &b) {
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return global_route_priority(a) < global_route_priority(b);
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});
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for (const auto &user : sorted_users) {
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route_logic_tile_global(clock, glbid, user);
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}
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for (auto &user : clock->users)
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toroute.emplace_back(&user, glbid);
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clocks[glbid] = clock;
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}
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}
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std::sort(toroute.begin(), toroute.end(),
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[this](const std::pair<PortRef *, int> &a, const std::pair<PortRef *, int> &b) {
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return global_route_priority(*a.first) < global_route_priority(*b.first);
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});
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for (const auto &user : toroute) {
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route_logic_tile_global(clocks.at(user.second), user.second, *user.first);
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}
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}
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};
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void promote_ecp5_globals(Context *ctx) { Ecp5GlobalRouter(ctx).promote_globals(); }
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67
ecp5/pack.cc
67
ecp5/pack.cc
@ -27,6 +27,7 @@
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#include "design_utils.h"
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#include "globals.h"
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#include "log.h"
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#include "timing.h"
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#include "util.h"
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NEXTPNR_NAMESPACE_BEGIN
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@ -164,6 +165,7 @@ class Ecp5Packer
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CellInfo *ci = cell.second;
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if (is_lut(ctx, ci) && procdLuts.find(cell.first) == procdLuts.end()) {
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NetInfo *znet = ci->ports.at(ctx->id("Z")).net;
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std::vector<NetInfo *> inpnets;
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if (znet != nullptr) {
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for (auto user : znet->users) {
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if (is_lut(ctx, user.cell) && user.cell != ci &&
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@ -228,12 +230,67 @@ class Ecp5Packer
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}
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}
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}
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// Pack LUTs feeding the same CCU2, RAM or DFF into a SLICE
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if (znet != nullptr && znet->users.size() < 10) {
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for (auto user : znet->users) {
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if (is_lc(ctx, user.cell) || user.cell->type == ctx->id("DP16KD") || is_ff(ctx, user.cell)) {
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for (auto port : user.cell->ports) {
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if (port.second.type != PORT_IN || port.second.net == nullptr ||
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port.second.net == znet)
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continue;
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if (port.second.net->users.size() > 10)
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continue;
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CellInfo *drv = port.second.net->driver.cell;
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if (drv == nullptr)
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continue;
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if (is_lut(ctx, drv) && !procdLuts.count(drv->name) &&
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can_pack_lutff(ci->name, drv->name)) {
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procdLuts.insert(ci->name);
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procdLuts.insert(drv->name);
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lutPairs[ci->name] = drv->name;
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goto paired_inlut;
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}
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}
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}
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}
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}
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// Pack LUTs sharing an input with a simple fanout-based heuristic
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for (const char *inp : {"A", "B", "C", "D"}) {
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NetInfo *innet = ci->ports.at(ctx->id(inp)).net;
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if (innet != nullptr && innet->users.size() < 5 && innet->users.size() > 1)
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inpnets.push_back(innet);
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}
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std::sort(inpnets.begin(), inpnets.end(),
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[&](const NetInfo *a, const NetInfo *b) { return a->users.size() < b->users.size(); });
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for (auto inet : inpnets) {
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for (auto &user : inet->users) {
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if (user.cell == nullptr || user.cell == ci || !is_lut(ctx, user.cell))
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continue;
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||||
if (procdLuts.count(user.cell->name))
|
||||
continue;
|
||||
if (can_pack_lutff(ci->name, user.cell->name)) {
|
||||
procdLuts.insert(ci->name);
|
||||
procdLuts.insert(user.cell->name);
|
||||
lutPairs[ci->name] = user.cell->name;
|
||||
goto paired_inlut;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (false) {
|
||||
paired_inlut:
|
||||
continue;
|
||||
}
|
||||
}
|
||||
}
|
||||
if (ctx->debug) {
|
||||
log_info("Singleton LUTs (packer QoR debug): \n");
|
||||
for (auto cell : sorted(ctx->cells))
|
||||
if (is_lut(ctx, cell.second) && !procdLuts.count(cell.first))
|
||||
log_info(" %s\n", cell.first.c_str(ctx));
|
||||
}
|
||||
}
|
||||
|
||||
// Return true if an port is a top level port that provides its own IOBUF
|
||||
@ -940,11 +997,11 @@ class Ecp5Packer
|
||||
if (is_lut(ctx, ci)) {
|
||||
std::unique_ptr<CellInfo> slice =
|
||||
create_ecp5_cell(ctx, ctx->id("TRELLIS_SLICE"), ci->name.str(ctx) + "_SLICE");
|
||||
lut_to_slice(ctx, ci, slice.get(), 0);
|
||||
lut_to_slice(ctx, ci, slice.get(), 1);
|
||||
auto ff = lutffPairs.find(ci->name);
|
||||
|
||||
if (ff != lutffPairs.end()) {
|
||||
ff_to_slice(ctx, ctx->cells.at(ff->second).get(), slice.get(), 0, true);
|
||||
ff_to_slice(ctx, ctx->cells.at(ff->second).get(), slice.get(), 1, true);
|
||||
packed_cells.insert(ff->second);
|
||||
fflutPairs.erase(ff->second);
|
||||
lutffPairs.erase(ci->name);
|
||||
@ -1825,7 +1882,8 @@ class Ecp5Packer
|
||||
}
|
||||
iol->params[ctx->id("DELAY.DEL_VALUE")] =
|
||||
std::to_string(lookup_delay(str_or_default(ci->params, ctx->id("DEL_MODE"), "USER_DEFINED")));
|
||||
if (ci->params.count(ctx->id("DEL_VALUE")) && ci->params.at(ctx->id("DEL_VALUE")) != "DELAY0")
|
||||
if (ci->params.count(ctx->id("DEL_VALUE")) &&
|
||||
ci->params.at(ctx->id("DEL_VALUE")).substr(0, 5) != "DELAY")
|
||||
iol->params[ctx->id("DELAY.DEL_VALUE")] = ci->params.at(ctx->id("DEL_VALUE"));
|
||||
if (ci->ports.count(id_LOADN))
|
||||
replace_port(ci, id_LOADN, iol, id_LOADN);
|
||||
@ -2388,6 +2446,9 @@ void Arch::assignArchInfo()
|
||||
ci->sliceInfo.clkmux = id(str_or_default(ci->params, id_CLKMUX, "CLK"));
|
||||
ci->sliceInfo.lsrmux = id(str_or_default(ci->params, id_LSRMUX, "LSR"));
|
||||
ci->sliceInfo.srmode = id(str_or_default(ci->params, id_SRMODE, "LSR_OVER_CE"));
|
||||
ci->sliceInfo.is_carry = str_or_default(ci->params, id("MODE"), "LOGIC") == "CCU2";
|
||||
ci->sliceInfo.sd0 = int_or_default(ci->params, id("REG0_SD"), 0);
|
||||
ci->sliceInfo.sd1 = int_or_default(ci->params, id("REG1_SD"), 0);
|
||||
ci->sliceInfo.has_l6mux = false;
|
||||
if (ci->ports.count(id_FXA) && ci->ports[id_FXA].net != nullptr &&
|
||||
ci->ports[id_FXA].net->driver.port == id_OFX0)
|
||||
|
||||
@ -153,7 +153,7 @@ speed_grade_names = ["6", "7", "8", "8_5G"]
|
||||
speed_grade_cells = {}
|
||||
speed_grade_pips = {}
|
||||
|
||||
pip_class_to_idx = {"default": 0}
|
||||
pip_class_to_idx = {"default": 0, "zero": 1}
|
||||
|
||||
timing_port_xform = {
|
||||
"RAD0": "D0",
|
||||
@ -199,7 +199,7 @@ def process_timing_data():
|
||||
pip_class_delays = []
|
||||
for i in range(len(pip_class_to_idx)):
|
||||
pip_class_delays.append((50, 50, 0, 0))
|
||||
|
||||
pip_class_delays[pip_class_to_idx["zero"]] = (0, 0, 0, 0)
|
||||
with open(timing_dbs.interconnect_db_path("ECP5", grade)) as f:
|
||||
interconn_data = json.load(f)
|
||||
for pipclass, pipdata in sorted(interconn_data.items()):
|
||||
@ -219,6 +219,12 @@ def process_timing_data():
|
||||
|
||||
|
||||
def get_pip_class(wire_from, wire_to):
|
||||
|
||||
if "FCO" in wire_from or "FCI" in wire_to:
|
||||
return pip_class_to_idx["zero"]
|
||||
if "F5" in wire_from or "FX" in wire_from or "FXA" in wire_to or "FXB" in wire_to:
|
||||
return pip_class_to_idx["zero"]
|
||||
|
||||
class_name = pip_classes.get_pip_class(wire_from, wire_to)
|
||||
if class_name is None or class_name not in pip_class_to_idx:
|
||||
class_name = "default"
|
||||
|
||||
Loading…
Reference in New Issue
Block a user