Add blinky post-synthesis testbench

Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2018-06-10 14:31:38 +02:00
parent 4a79e70470
commit 032c94d094
3 changed files with 26 additions and 5 deletions

9
ice40/.gitignore vendored
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@ -1,5 +1,4 @@
/chipdb-1k.cc /blinky_chip.v
/chipdb-384.cc /blinky_tb
/chipdb-5k.cc /blinky_tb.vcd
/chipdb-8k.cc /chipdbs/
chipdbs/

7
ice40/blinky.sh Normal file
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#!/bin/bash
set -ex
yosys blinky.ys
../nextpnr-ice40 --json blinky.json --asc blinky.asc
icebox_vlog blinky.asc > blinky_chip.v
iverilog -o blinky_tb blinky_chip.v blinky_tb.v
./blinky_tb

15
ice40/blinky_tb.v Normal file
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module blinky_tb;
reg clk;
always #5 clk = (clk === 1'b0);
chip uut (
.io_0_8_1(clk)
);
initial begin
$dumpfile("blinky_tb.vcd");
$dumpvars(0, blinky_tb);
repeat (9000000) @(posedge clk);
$finish;
end
endmodule