ecp5: Major improvements to Trellis importer
Signed-off-by: David Shah <davey1576@gmail.com>
This commit is contained in:
David Shah
parent
889e1fc19f
commit
044db02012
@ -32,213 +32,6 @@ def get_tiletype_index(name):
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portpins = dict()
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loc_wire_indices = dict()
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loc_wires = dict()
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loc_bels = dict()
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wire_bel_pins_uphill = dict()
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wire_bel_pins_downhill = dict()
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# Import all wire names at all locations
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def import_location_wires(rg, x, y):
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loc_wire_indices[x, y] = dict()
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loc_wires[x, y] = list()
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wire_bel_pins_uphill[x, y] = list()
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wire_bel_pins_downhill[x, y] = list()
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rtile = rg.tiles[pytrellis.Location(x, y)]
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for wire in rtile.wires:
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name = rg.to_str(wire.key())
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idx = len(loc_wires[x, y])
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loc_wires[x, y].append(name)
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loc_wire_indices[x, y][name] = idx
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wire_bel_pins_uphill[x, y].append([])
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wire_bel_pins_downhill[x, y].append([])
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# Take a RoutingId from Trellis and make into a (relx, rely, name) tuple
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def resolve_wirename(rg, rid, cur_x, cur_y):
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if is_global(rid.loc):
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return (cur_x, cur_y, rg.to_str(rid.id))
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else:
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x = rid.loc.x
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y = rid.loc.y
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widx = loc_wire_indices[x, y][rg.to_str(rid.id)]
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return (x - cur_x, y - cur_y, widx)
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loc_arc_indices = dict() # Map RoutingId index to nextpnr index
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loc_arcs = dict()
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# Import all arc indices at a location
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def index_location_arcs(rg, x, y):
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loc_arc_indices[x, y] = dict()
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loc_arcs[x, y] = list()
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rtile = rg.tiles[pytrellis.Location(x, y)]
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for arc in rtile.arcs:
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idx = len(loc_arcs[x, y])
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trid = arc.key()
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loc_arcs[x, y].append(trid)
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loc_arc_indices[x, y][trid] = idx
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def add_bel_input(bel_x, bel_y, bel_idx, bel_pin, wire_x, wire_y, wire_name):
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bel_pin = portpins[bel_pin]
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loc_bels[bel_x, bel_y][bel_idx][2].append((bel_pin, (wire_x, wire_y, loc_wire_indices[wire_x, wire_y][wire_name])))
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wire_bel_pins_downhill[wire_x, wire_y][loc_wire_indices[wire_x, wire_y][wire_name]].append((
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(bel_x, bel_y, bel_idx), bel_pin))
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def add_bel_output(bel_x, bel_y, bel_idx, bel_pin, wire_x, wire_y, wire_name):
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bel_pin = portpins[bel_pin]
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loc_bels[bel_x, bel_y][bel_idx][2].append((bel_pin, (wire_x, wire_y, loc_wire_indices[wire_x, wire_y][wire_name])))
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wire_bel_pins_uphill[wire_x, wire_y][loc_wire_indices[wire_x, wire_y][wire_name]].append((
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(bel_x, bel_y, bel_idx), bel_pin))
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def add_slice(x, y, z):
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idx = len(loc_bels[x, y])
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l = ("A", "B", "C", "D")[z]
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name = "SLICE" + l
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loc_bels[x, y].append((name, "SLICE", []))
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lc0 = z * 2
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lc1 = z * 2 + 1
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add_bel_input(x, y, idx, "A0", x, y, "A{}_SLICE".format(lc0))
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add_bel_input(x, y, idx, "B0", x, y, "B{}_SLICE".format(lc0))
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add_bel_input(x, y, idx, "C0", x, y, "C{}_SLICE".format(lc0))
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add_bel_input(x, y, idx, "D0", x, y, "D{}_SLICE".format(lc0))
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add_bel_input(x, y, idx, "M0", x, y, "M{}_SLICE".format(lc0))
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add_bel_input(x, y, idx, "A1", x, y, "A{}_SLICE".format(lc1))
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add_bel_input(x, y, idx, "B1", x, y, "B{}_SLICE".format(lc1))
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add_bel_input(x, y, idx, "C1", x, y, "C{}_SLICE".format(lc1))
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add_bel_input(x, y, idx, "D1", x, y, "D{}_SLICE".format(lc1))
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add_bel_input(x, y, idx, "M1", x, y, "M{}_SLICE".format(lc1))
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add_bel_input(x, y, idx, "FCI", x, y, "FCI{}_SLICE".format(l if z > 0 else ""))
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add_bel_input(x, y, idx, "FXA", x, y, "FXA{}_SLICE".format(l))
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add_bel_input(x, y, idx, "FXB", x, y, "FXB{}_SLICE".format(l))
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add_bel_input(x, y, idx, "CLK", x, y, "CLK{}_SLICE".format(z))
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add_bel_input(x, y, idx, "LSR", x, y, "LSR{}_SLICE".format(z))
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add_bel_input(x, y, idx, "CE", x, y, "CE{}_SLICE".format(z))
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add_bel_input(x, y, idx, "DI0", x, y, "DI{}_SLICE".format(lc0))
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add_bel_input(x, y, idx, "DI1", x, y, "DI{}_SLICE".format(lc1))
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if z == 0 or z == 1:
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add_bel_input(x, y, idx, "WD0", x, y, "WD0{}_SLICE".format(l))
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add_bel_input(x, y, idx, "WD1", x, y, "WD1{}_SLICE".format(l))
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add_bel_input(x, y, idx, "WAD0", x, y, "WAD0{}_SLICE".format(l))
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add_bel_input(x, y, idx, "WAD1", x, y, "WAD1{}_SLICE".format(l))
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add_bel_input(x, y, idx, "WAD2", x, y, "WAD2{}_SLICE".format(l))
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add_bel_input(x, y, idx, "WAD3", x, y, "WAD3{}_SLICE".format(l))
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add_bel_input(x, y, idx, "WRE", x, y, "WRE{}_SLICE".format(z))
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add_bel_input(x, y, idx, "WCK", x, y, "WCK{}_SLICE".format(z))
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add_bel_output(x, y, idx, "F0", x, y, "F{}_SLICE".format(lc0))
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add_bel_output(x, y, idx, "Q0", x, y, "Q{}_SLICE".format(lc0))
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add_bel_output(x, y, idx, "F1", x, y, "F{}_SLICE".format(lc1))
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add_bel_output(x, y, idx, "Q1", x, y, "Q{}_SLICE".format(lc1))
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add_bel_output(x, y, idx, "OFX0", x, y, "F5{}_SLICE".format(l))
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add_bel_output(x, y, idx, "OFX1", x, y, "FX{}_SLICE".format(l))
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add_bel_output(x, y, idx, "FCO", x, y, "FCO{}_SLICE".format(l if z < 3 else ""))
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if z == 2:
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add_bel_output(x, y, idx, "WDO0", x, y, "WDO0C_SLICE")
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add_bel_output(x, y, idx, "WDO1", x, y, "WDO1C_SLICE")
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add_bel_output(x, y, idx, "WDO2", x, y, "WDO2C_SLICE")
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add_bel_output(x, y, idx, "WDO3", x, y, "WDO3C_SLICE")
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add_bel_output(x, y, idx, "WADO0", x, y, "WADO0C_SLICE")
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add_bel_output(x, y, idx, "WADO1", x, y, "WADO1C_SLICE")
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add_bel_output(x, y, idx, "WADO2", x, y, "WADO2C_SLICE")
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add_bel_output(x, y, idx, "WADO3", x, y, "WADO3C_SLICE")
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def add_pio(x, y, z):
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idx = len(loc_bels[x, y])
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l = ("A", "B", "C", "D")[z]
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name = "PIO" + l
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loc_bels[x, y].append((name, "PIO", []))
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add_bel_input(x, y, idx, "I", x, y, "PADDO{}_PIO".format(l))
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add_bel_input(x, y, idx, "T", x, y, "PADDT{}_PIO".format(l))
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add_bel_output(x, y, idx, "O", x, y, "JPADDI{}_PIO".format(l))
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def add_bels(chip, x, y):
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loc_bels[x, y] = []
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tiles = chip.get_tiles_by_position(y, x)
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num_slices = 0
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num_pios = 0
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for tile in tiles:
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tt = tile.info.type
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if tt == "PLC2":
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num_slices = 4
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elif "PICL0" in tt or "PICR0" in tt:
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num_pios = 4
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elif "PIOT0" in tt or ("PICB0" in tt and "SPICB" not in tt):
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num_pios = 2
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for i in range(num_slices):
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add_slice(x, y, i)
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for i in range(num_pios):
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add_pio(x, y, i)
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# Import a location, deduplicating if appropriate
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def import_location(rg, x, y):
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rtile = rg.tiles[pytrellis.Location(x, y)]
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arcs = [] # (src, dst, configurable, tiletype)
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wires = [] # (name, uphill, downhill, belpin_uphill, belpins_downhill)
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bels = [] # (name, [(pin, wire)])
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for name in loc_wires[x, y]:
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w = rtile.wires[rg.ident(name)]
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arcs_uphill = []
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arcs_downhill = []
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belpins_uphill = []
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belpins_downhill = []
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for uh in w.uphill:
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arcidx = loc_arc_indices[uh.loc.x, uh.loc.y][uh.id]
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arcs_uphill.append((uh.loc.x - x, uh.loc.y - y, arcidx))
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for dh in w.downhill:
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arcidx = loc_arc_indices[dh.loc.x, dh.loc.y][dh.id]
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arcs_downhill.append((dh.loc.x - x, dh.loc.y - y, arcidx))
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for bp in wire_bel_pins_uphill[x, y][loc_wire_indices[x, y][name]]:
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bel, pin = bp
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bel_x, bel_y, bel_idx = bel
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belpins_uphill.append(((bel_x - x, bel_y - y, bel_idx), pin))
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for bp in wire_bel_pins_downhill[x, y][loc_wire_indices[x, y][name]]:
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bel, pin = bp
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bel_x, bel_y, bel_idx = bel
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belpins_downhill.append(((bel_x - x, bel_y - y, bel_idx), pin))
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assert len(belpins_uphill) <= 1
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wires.append((name, tuple(arcs_downhill), tuple(arcs_uphill), tuple(belpins_uphill), tuple(belpins_downhill)))
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for bel in loc_bels[x, y]:
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name, beltype, pins = bel
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xformed_pins = tuple((p[0], (p[1][0] - x, p[1][1] - y, p[1][2])) for p in pins)
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bels.append((name, beltype, xformed_pins))
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for arcidx in loc_arcs[x, y]:
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a = rtile.arcs[arcidx]
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source_wire = resolve_wirename(rg, a.source, x, y)
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dest_wire = resolve_wirename(rg, a.sink, x, y)
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arcs.append((source_wire, dest_wire, a.configurable, get_tiletype_index(rg.to_str(a.tiletype))))
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tile_data = (tuple(wires), tuple(arcs), tuple(bels))
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if tile_data in location_types:
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type_at_location[x, y] = location_types[tile_data]
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else:
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idx = len(location_types)
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location_types[tile_data] = idx
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type_at_location[x, y] = idx
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class BinaryBlobAssembler:
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def __init__(self, cname, endianness, nodebug=False):
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@ -526,100 +319,96 @@ bel_types = {
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"PIO": 2
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}
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def write_database(dev_name, endianness):
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def write_loc(x, y, sym_name):
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bba.s16(x, "%s.x" % sym_name)
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bba.s16(y, "%s.y" % sym_name)
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def write_database(dev_name, ddrg, endianness):
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def write_loc(loc, sym_name):
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bba.s16(loc.x, "%s.x" % sym_name)
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bba.s16(loc.y, "%s.y" % sym_name)
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bba = BinaryBlobAssembler("chipdb_blob_%s" % dev_name, endianness)
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bba.r("chip_info", "chip_info")
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for loctype, idx in sorted(location_types.items(), key=lambda x: x[1]):
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wires, arcs, bels = loctype
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if len(arcs) > 0:
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loctypes = list([_.key() for _ in ddrg.locationTypes])
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for idx in range(len(loctypes)):
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loctype = ddrg.locationTypes[loctypes[idx]]
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if len(loctype.arcs) > 0:
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bba.l("loc%d_pips" % idx, "PipInfoPOD")
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for arc in arcs:
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src_wire, dst_wire, configurable, tile_type = arc
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write_loc(src_wire[0], src_wire[1], "src")
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write_loc(dst_wire[0], dst_wire[1], "dst")
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bba.u32(src_wire[2], "src_idx")
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bba.u32(dst_wire[2], "dst_idx")
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bba.u32(1, "delay") # TODO:delay
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bba.u16(tile_type, "tile_type")
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bba.u8(1 if not configurable else 0, "pip_type")
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for arc in loctype.arcs:
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write_loc(arc.srcWire.rel, "src")
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write_loc(arc.sinkWire.rel, "dst")
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bba.u32(arc.srcWire.id, "src_idx")
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bba.u32(arc.sinkWire.id, "dst_idx")
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bba.u32(arc.delay, "delay") # TODO:delay
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bba.u16(get_tiletype_index(ddrg.to_str(arc.tiletype)), "tile_type")
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bba.u8(int(arc.cls), "pip_type")
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bba.u8(0, "padding")
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if len(wires) > 0:
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for wire_idx in range(len(wires)):
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wire = wires[wire_idx]
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name, downpips, uppips, downbels, upbels = wire
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if len(downpips) > 0:
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if len(loctype.wires) > 0:
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for wire_idx in range(len(loctype.wires)):
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wire = loctype.wires[wire_idx]
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if len(wire.arcsDownhill) > 0:
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bba.l("loc%d_wire%d_downpips" % (idx, wire_idx), "PipLocatorPOD")
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for dp in downpips:
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write_loc(dp[0], dp[1], "rel_loc")
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bba.u32(dp[2], "index")
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if len(uppips) > 0:
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for dp in wire.arcsDownhill:
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write_loc(dp.rel, "rel_loc")
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bba.u32(dp.id, "index")
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if len(wire.arcsUphill) > 0:
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bba.l("loc%d_wire%d_uppips" % (idx, wire_idx), "PipLocatorPOD")
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for up in uppips:
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write_loc(up[0], up[1], "rel_loc")
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bba.u32(up[2], "index")
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if len(downbels) > 0:
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for up in wire.arcsUphill:
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write_loc(up.rel, "rel_loc")
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bba.u32(up.id, "index")
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if len(wire.belsDownhill) > 0:
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bba.l("loc%d_wire%d_downbels" % (idx, wire_idx), "BelPortPOD")
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for db in downbels:
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bel, pin = db
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write_loc(bel[0], bel[1], "rel_bel_loc")
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bba.u32(bel[2], "bel_index")
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bba.u32(pin, "port")
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for db in wire.belsDownhill:
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write_loc(db.bel.rel, "rel_bel_loc")
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bba.u32(db.bel.id, "bel_index")
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bba.u32(portpins[ddrg.to_str(db.pin)], "port")
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bba.l("loc%d_wires" % idx, "WireInfoPOD")
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for wire_idx in range(len(wires)):
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wire = wires[wire_idx]
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name, downpips, uppips, downbels, upbels = wire
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bba.s(name, "name")
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bba.u32(len(uppips), "num_uphill")
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bba.u32(len(downpips), "num_downhill")
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bba.r("loc%d_wire%d_uppips" % (idx, wire_idx) if len(uppips) > 0 else None, "pips_uphill")
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bba.r("loc%d_wire%d_downpips" % (idx, wire_idx) if len(downpips) > 0 else None, "pips_downhill")
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bba.u32(len(downbels), "num_bels_downhill")
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if len(upbels) == 1:
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bel, pin = upbels[0]
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write_loc(bel[0], bel[1], "uphill_bel_loc")
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bba.u32(bel[2], "uphill_bel_idx")
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bba.u32(pin, "uphill_bel_pin")
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for wire_idx in range(len(loctype.wires)):
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wire = loctype.wires[wire_idx]
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bba.s(ddrg.to_str(wire.name), "name")
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bba.u32(len(wire.arcsUphill), "num_uphill")
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bba.u32(len(wire.arcsDownhill), "num_downhill")
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bba.r("loc%d_wire%d_uppips" % (idx, wire_idx) if len(wire.arcsUphill) > 0 else None, "pips_uphill")
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bba.r("loc%d_wire%d_downpips" % (idx, wire_idx) if len(wire.arcsDownhill) > 0 else None, "pips_downhill")
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bba.u32(len(wire.belsDownhill), "num_bels_downhill")
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write_loc(wire.belUphill.bel.rel, "uphill_bel_loc")
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if wire.belUphill.pin != -1:
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bba.u32(wire.belUphill.bel.id, "uphill_bel_idx")
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bba.u32(portpins[ddrg.to_str(wire.belUphill.pin)], "uphill_bel_pin")
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else:
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write_loc(-1, -1, "bel_uphill.rel_bel_loc")
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bba.u32(0xFFFFFFFF, "bel_uphill.bel_index")
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bba.u32(0, "bel_uphill.port")
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bba.r("loc%d_wire%d_downbels" % (idx, wire_idx) if len(downbels) > 0 else None, "bels_downhill")
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if len(bels) > 0:
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for bel_idx in range(len(bels)):
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bel, beltype, pins = bels[bel_idx]
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bba.r("loc%d_wire%d_downbels" % (idx, wire_idx) if len(wire.belsDownhill) > 0 else None, "bels_downhill")
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if len(loctype.bels) > 0:
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for bel_idx in range(len(loctype.bels)):
|
||||
bel = loctype.bels[bel_idx]
|
||||
bba.l("loc%d_bel%d_wires" % (idx, bel_idx), "BelPortPOD")
|
||||
for pin in pins:
|
||||
port, wire = pin
|
||||
write_loc(wire[0], wire[1], "rel_wire_loc")
|
||||
bba.u32(wire[2], "wire_index")
|
||||
bba.u32(port, "port")
|
||||
for pin in bel.wires:
|
||||
write_loc(pin.wire.rel, "rel_wire_loc")
|
||||
bba.u32(pin.wire.id, "wire_index")
|
||||
bba.u32(portpins[ddrg.to_str(pin.pin)], "port")
|
||||
bba.l("loc%d_bels" % idx, "BelInfoPOD")
|
||||
for bel_idx in range(len(bels)):
|
||||
bel, beltype, pins = bels[bel_idx]
|
||||
bba.s(bel, "name")
|
||||
bba.u32(bel_types[beltype], "type")
|
||||
bba.u32(len(pins), "num_bel_wires")
|
||||
for bel_idx in range(len(loctype.bels)):
|
||||
bel = loctype.bels[bel_idx]
|
||||
bba.s(ddrg.to_str(bel.name), "name")
|
||||
bba.u32(bel_types[ddrg.to_str(bel.type)], "type")
|
||||
bba.u32(len(bel.wires), "num_bel_wires")
|
||||
bba.r("loc%d_bel%d_wires" % (idx, bel_idx), "bel_wires")
|
||||
|
||||
bba.l("locations", "LocationTypePOD")
|
||||
for loctype, idx in sorted(location_types.items(), key=lambda x: x[1]):
|
||||
wires, arcs, bels = loctype
|
||||
bba.u32(len(bels), "num_bels")
|
||||
bba.u32(len(wires), "num_wires")
|
||||
bba.u32(len(arcs), "num_pips")
|
||||
bba.r("loc%d_bels" % idx if len(bels) > 0 else None, "bel_data")
|
||||
bba.r("loc%d_wires" % idx if len(wires) > 0 else None, "wire_data")
|
||||
bba.r("loc%d_pips" % idx if len(arcs) > 0 else None, "pips_data")
|
||||
for idx in range(len(loctypes)):
|
||||
loctype = ddrg.locationTypes[loctypes[idx]]
|
||||
bba.u32(len(loctype.bels), "num_bels")
|
||||
bba.u32(len(loctype.wires), "num_wires")
|
||||
bba.u32(len(loctype.arcs), "num_pips")
|
||||
bba.r("loc%d_bels" % idx if len(loctype.bels) > 0 else None, "bel_data")
|
||||
bba.r("loc%d_wires" % idx if len(loctype.wires) > 0 else None, "wire_data")
|
||||
bba.r("loc%d_pips" % idx if len(loctype.arcs) > 0 else None, "pips_data")
|
||||
|
||||
bba.l("location_types", "int32_t")
|
||||
for y in range(0, max_row+1):
|
||||
for x in range(0, max_col+1):
|
||||
bba.u32(type_at_location[x, y], "loctype")
|
||||
bba.u32(loctypes.index(ddrg.typeAtLocation[pytrellis.Location(x, y)]), "loctype")
|
||||
|
||||
bba.l("tiletype_names", "RelPtr<char>")
|
||||
for tt in tiletype_names:
|
||||
@ -659,28 +448,11 @@ def main():
|
||||
print("Initialising chip...")
|
||||
chip = pytrellis.Chip(dev_names[args.device])
|
||||
print("Building routing graph...")
|
||||
rg = chip.get_routing_graph()
|
||||
ddrg = pytrellis.make_dedup_chipdb(chip)
|
||||
max_row = chip.get_max_row()
|
||||
max_col = chip.get_max_col()
|
||||
print("Indexing wires...")
|
||||
for y in range(0, max_row + 1):
|
||||
for x in range(0, max_col + 1):
|
||||
import_location_wires(rg, x, y)
|
||||
print("Indexing arcs...")
|
||||
for y in range(0, max_row + 1):
|
||||
for x in range(0, max_col + 1):
|
||||
index_location_arcs(rg, x, y)
|
||||
print("Adding bels...")
|
||||
for y in range(0, max_row + 1):
|
||||
for x in range(0, max_col + 1):
|
||||
add_bels(chip, x, y)
|
||||
print("Importing tiles...")
|
||||
for y in range(0, max_row + 1):
|
||||
for x in range(0, max_col + 1):
|
||||
print(" At R{}C{}".format(y, x))
|
||||
import_location(rg, x, y)
|
||||
print("{} unique location types".format(len(location_types)))
|
||||
bba = write_database(args.device, "le")
|
||||
print("{} unique location types".format(len(ddrg.locationTypes)))
|
||||
bba = write_database(args.device, ddrg, "le")
|
||||
|
||||
|
||||
if args.c_file:
|
||||
|
||||
Loading…
Reference in New Issue
Block a user