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Remove PLL from picorv32, allow errors in pnr

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This commit is contained in:
Eddie Hung 2018-12-27 23:28:12 -08:00
parent 84d038360d
commit 04757865fe
3 changed files with 19 additions and 7 deletions
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6
xc7/picorv32.pcf
View File

@ -1,3 +1,3 @@
NET "pll.clkin1" PERIOD = 8 nS ;
#PIN "clk_pin" = BEL "clk.PAD" PINNAME PAD;
#PIN "clk_pin" CLOCK_DEDICATED_ROUTE = FALSE;
NET "clki" PERIOD = 8 nS ;
PIN "clki_pin" = BEL "clki.PAD" PINNAME PAD;
PIN "clki_pin" CLOCK_DEDICATED_ROUTE = FALSE;

4
xc7/picorv32.sh
View File

@ -3,7 +3,9 @@ set -ex
rm -f picorv32.v
wget https://raw.githubusercontent.com/cliffordwolf/picorv32/master/picorv32.v
yosys picorv32.ys
../nextpnr-xc7 --json picorv32.json --xdl picorv32.xdl --pcf picorv32.pcf --freq 150
set +e
../nextpnr-xc7 --json picorv32.json --xdl picorv32.xdl --pcf picorv32.pcf --freq 125
set -e
xdl -xdl2ncd picorv32.xdl
#bitgen -w blinky.ncd -g UnconstrainedPins:Allow
trce picorv32.ncd -v 10

16
xc7/picorv32_top.v
View File

@ -1,5 +1,5 @@
module top (
input clk, resetn,
input clki, resetn,
output trap,
output mem_valid,
@ -12,7 +12,17 @@ module top (
input [31:0] mem_rdata
);
clk_wiz_v3_6 pll(.CLK_IN1(clk), .CLK_OUT1(gclk));
wire clk;
BUFGCTRL clk_gb (
.I0(clki),
.CE0(1'b1),
.CE1(1'b0),
.S0(1'b1),
.S1(1'b0),
.IGNORE0(1'b0),
.IGNORE1(1'b0),
.O(clk)
);
picorv32 #(
.ENABLE_COUNTERS(0),
@ -20,7 +30,7 @@ module top (
.CATCH_MISALIGN(0),
.CATCH_ILLINSN(0)
) cpu (
.clk (gclk ),
.clk (clk ),
.resetn (resetn ),
.trap (trap ),
.mem_valid(mem_valid),