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clangformat and more cleanup

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This commit is contained in:
Eddie Hung 2019-01-10 15:04:51 -08:00
parent 74e84cf65e
commit 04c08b7bc6
15 changed files with 54 additions and 1294 deletions
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2
common/place_common.cc
View File

@ -38,7 +38,7 @@ wirelen_t get_net_metric(const Context *ctx, const NetInfo *net, MetricType type
return 0;
int clock_count;
if (ctx->getPortTimingClass(driver_cell, net->driver.port, clock_count) == TMG_IGNORE)
return 0;
return 0;
bool timing_driven = ctx->timing_driven && type == MetricType::COST &&
ctx->getPortTimingClass(driver_cell, net->driver.port, clock_count) != TMG_IGNORE;
delay_t negative_slack = 0;

4
gui/application.cc
View File

@ -51,8 +51,8 @@ Application::Application(int &argc, char **argv) : QApplication(argc, argv)
bool Application::notify(QObject *receiver, QEvent *event)
{
bool retVal = true;
//try {
retVal = QApplication::notify(receiver, event);
// try {
retVal = QApplication::notify(receiver, event);
/*} catch (assertion_failure ex) {
QString msg;
QTextStream out(&msg);

2
gui/designwidget.cc
View File

@ -714,7 +714,7 @@ void DesignWidget::onSelectionChanged(int num, const QItemSelection &, const QIt
addProperty(topItem, QVariant::String, "Bound Net", ctx->nameOf(ctx->getBoundPipNet(pip)), ElementType::NET);
WireId conflict = ctx->getConflictingPipWire(pip);
addProperty(topItem, QVariant::String, "Conflicting Wire",
(conflict!=WireId() ? ctx->getWireName(conflict).c_str(ctx) : ""), ElementType::WIRE);
(conflict != WireId() ? ctx->getWireName(conflict).c_str(ctx) : ""), ElementType::WIRE);
addProperty(topItem, QVariant::String, "Conflicting Net", ctx->nameOf(ctx->getConflictingPipNet(pip)),
ElementType::NET);
addProperty(topItem, QVariant::String, "Src Wire", ctx->getWireName(ctx->getPipSrcWire(pip)).c_str(ctx),

41
xc7/arch.cc
View File

@ -41,12 +41,12 @@ TorcInfo::TorcInfo(BaseCtx *ctx, const std::string &inDeviceName, const std::str
std::cmatch what;
tile_to_xy.resize(tiles.getTileCount());
for (TileIndex tileIndex(0); tileIndex < tiles.getTileCount(); tileIndex++) {
const auto &tileInfo = tiles.getTileInfo(tileIndex);
const auto &tileInfo = tiles.getTileInfo(tileIndex);
if (!std::regex_match(tileInfo.getName(), what, re_loc))
throw;
const auto x = boost::lexical_cast<int>(what.str(1));
const auto y = boost::lexical_cast<int>(what.str(2));
tile_to_xy[tileIndex] = std::make_pair(x,y);
tile_to_xy[tileIndex] = std::make_pair(x, y);
}
bel_to_site_index.reserve(sites.getSiteCount() * 4);
@ -60,7 +60,7 @@ TorcInfo::TorcInfo(BaseCtx *ctx, const std::string &inDeviceName, const std::str
const auto &pd = site.getPrimitiveDefPtr();
const auto &type = pd->getName();
int x, y;
std::tie(x,y) = tile_to_xy[site.getTileIndex()];
std::tie(x, y) = tile_to_xy[site.getTileIndex()];
if (type == "SLICEL" || type == "SLICEM") {
bel_to_site_index.push_back(i);
@ -144,9 +144,9 @@ TorcInfo::TorcInfo(BaseCtx *ctx, const std::string &inDeviceName, const std::str
// expand all of the arcs
TilewireVector::const_iterator sep = segment.begin();
TilewireVector::const_iterator see = segment.end();
while(sep < see) {
while (sep < see) {
// expand the tilewire sinks
const Tilewire& tilewire = *sep++;
const Tilewire &tilewire = *sep++;
const auto &tileInfo = tiles.getTileInfo(tilewire.getTileIndex());
const auto &tileTypeName = tiles.getTileTypeName(tileInfo.getTypeIndex());
@ -268,7 +268,7 @@ TorcInfo::TorcInfo(BaseCtx *ctx, const std::string &inDeviceName, const std::str
bool global_tile = false;
arcs.clear();
//const_cast<DDB &>(*ddb).expandSegmentSinks(currentTilewire, arcs, DDB::eExpandDirectionNone,
// const_cast<DDB &>(*ddb).expandSegmentSinks(currentTilewire, arcs, DDB::eExpandDirectionNone,
// false /* inUseTied */, true /*inUseRegular */,
// true /* inUseIrregular */, !clb /* inUseRoutethrough */);
{
@ -278,21 +278,22 @@ TorcInfo::TorcInfo(BaseCtx *ctx, const std::string &inDeviceName, const std::str
// expand all of the arcs
TilewireVector::const_iterator sep = segment.begin();
TilewireVector::const_iterator see = segment.end();
while(sep < see) {
while (sep < see) {
// expand the tilewire sinks
const Tilewire& tilewire = *sep++;
const Tilewire &tilewire = *sep++;
const auto &tileInfo = tiles.getTileInfo(tilewire.getTileIndex());
const auto &tileTypeName = tiles.getTileTypeName(tileInfo.getTypeIndex());
global_tile = global_tile || boost::starts_with(tileTypeName, "CLK") || boost::starts_with(tileTypeName, "HCLK") || boost::starts_with(tileTypeName, "CFG");
global_tile = global_tile || boost::starts_with(tileTypeName, "CLK") ||
boost::starts_with(tileTypeName, "HCLK") || boost::starts_with(tileTypeName, "CFG");
TilewireVector sinks;
const_cast<DDB &>(*ddb).expandTilewireSinks(tilewire, sinks, false /*inUseTied*/, true /*inUseRegular*/, true /*inUseIrregular*/,
!clb /* inUseRoutethrough */);
const_cast<DDB &>(*ddb).expandTilewireSinks(tilewire, sinks, false /*inUseTied*/, true /*inUseRegular*/,
true /*inUseIrregular*/, !clb /* inUseRoutethrough */);
// rewrite the sinks as arcs
TilewireVector::const_iterator sip = sinks.begin();
TilewireVector::const_iterator sie = sinks.end();
while(sip < sie) {
while (sip < sie) {
Arc a(tilewire, *sip++);
// Disable BUFG I0 -> O routethrough
@ -330,8 +331,8 @@ TorcInfo::TorcInfo(BaseCtx *ctx, const std::string &inDeviceName, const std::str
height = (int)tiles.getRowCount();
width = (int)tiles.getColCount();
}
TorcInfo::TorcInfo(const std::string& inDeviceName, const std::string &inPackageName)
: ddb(new DDB(inDeviceName, inPackageName)), sites(ddb->getSites()), tiles(ddb->getTiles()),
TorcInfo::TorcInfo(const std::string &inDeviceName, const std::string &inPackageName)
: ddb(new DDB(inDeviceName, inPackageName)), sites(ddb->getSites()), tiles(ddb->getTiles()),
segments(ddb->getSegments())
{
}
@ -401,19 +402,18 @@ IdString Arch::archArgsToId(ArchArgs args) const
// -----------------------------------------------------------------------
static bool endsWith(const std::string& str, const std::string& suffix)
static bool endsWith(const std::string &str, const std::string &suffix)
{
return str.size() >= suffix.size() && 0 == str.compare(str.size()-suffix.size(), suffix.size(), suffix);
return str.size() >= suffix.size() && 0 == str.compare(str.size() - suffix.size(), suffix.size(), suffix);
}
BelId Arch::getBelByName(IdString name) const
{
std::string n = name.str(this);
int ndx = 0;
if (endsWith(n,"_A") || endsWith(n,"_B") || endsWith(n,"_C") || endsWith(n,"_D"))
{
if (endsWith(n, "_A") || endsWith(n, "_B") || endsWith(n, "_C") || endsWith(n, "_D")) {
ndx = (int)(n.back() - 'A');
n = n.substr(0,n.size()-2);
n = n.substr(0, n.size() - 2);
}
auto it = torc_info->sites.findSiteIndex(n);
if (it != SiteIndex(-1)) {
@ -612,7 +612,7 @@ IdString Arch::getGroupName(GroupId group) const
std::string suffix;
switch (group.type) {
NPNR_ASSERT("TODO");
NPNR_ASSERT("TODO");
default:
return IdString();
}
@ -726,7 +726,6 @@ std::vector<GraphicElement> Arch::getDecalGraphics(DecalId decal) const
el.y2 = y + logic_cell_y2 + (z)*logic_cell_pitch;
ret.push_back(el);
}
}
return ret;

11
xc7/arch.h
View File

@ -103,7 +103,7 @@ struct TorcInfo
l.y = (int)ewi.mTileRow;
return l;
}
WireId tilewire_to_wire(const Tilewire &tw) const
{
const auto &segment = segments.getTilewireSegment(tw);
@ -122,14 +122,14 @@ struct TorcInfo
std::vector<Tilewire> wire_to_tilewire;
int num_wires;
std::vector<DelayInfo> wire_to_delay;
//std::vector<std::vector<int>> wire_to_pips_uphill;
// std::vector<std::vector<int>> wire_to_pips_uphill;
std::vector<std::vector<PipId>> wire_to_pips_downhill;
std::vector<Arc> pip_to_arc;
int num_pips;
int width;
int height;
std::vector<bool> wire_is_global;
std::vector<std::pair<int,int>> tile_to_xy;
std::vector<std::pair<int, int>> tile_to_xy;
TorcInfo(const std::string &inDeviceName, const std::string &inPackageName);
};
@ -253,10 +253,7 @@ struct PipIterator
void operator++() { cursor++; }
bool operator!=(const PipIterator &other) const { return cursor != other.cursor; }
PipId operator*() const
{
return *cursor;
}
PipId operator*() const { return *cursor; }
};
struct PipRange

7
xc7/arch_place.cc
View File

@ -59,18 +59,17 @@ bool Arch::isValidBelForCell(CellInfo *cell, BelId bel) const
if (cell->type == id("XC7_LC")) {
std::array<const CellInfo *, 4> bel_cells;
size_t num_cells = 0;
Loc bel_loc = getBelLocation(bel);
for (auto bel_other : getBelsByTile(bel_loc.x, bel_loc.y)) {
CellInfo *ci_other = getBoundBelCell(bel_other);
if (ci_other != nullptr && bel_other != bel)
bel_cells[num_cells++] = ci_other;
}
bel_cells[num_cells++] = cell;
return logicCellsCompatible(bel_cells.data(), num_cells);
}
else {
} else {
return true;
}
}

2
xc7/arch_pybindings.cc
View File

@ -35,7 +35,7 @@ void arch_wrap_python()
class_<WireId>("WireId").def_readwrite("index", &WireId::index);
class_<PipId>("PipId").def_readwrite("index", &PipId::index);
class_<PipId>("PipId").def_readwrite("index", &PipId::index);
class_<BelPin>("BelPin").def_readwrite("bel", &BelPin::bel).def_readwrite("pin", &BelPin::pin);

11
xc7/archdefs.h
View File

@ -96,17 +96,6 @@ struct GroupId
enum : int8_t
{
TYPE_NONE,
TYPE_FRAME,
TYPE_MAIN_SW,
TYPE_LOCAL_SW,
TYPE_LC0_SW,
TYPE_LC1_SW,
TYPE_LC2_SW,
TYPE_LC3_SW,
TYPE_LC4_SW,
TYPE_LC5_SW,
TYPE_LC6_SW,
TYPE_LC7_SW
} type = TYPE_NONE;
int8_t x = 0, y = 0;

20
xc7/cells.cc
View File

@ -68,10 +68,10 @@ std::unique_ptr<CellInfo> create_xc7_cell(Context *ctx, IdString type, std::stri
add_port(ctx, new_cell.get(), "OMUX", PORT_OUT);
add_port(ctx, new_cell.get(), "COUT", PORT_OUT);
} else if (type == ctx->id("IOBUF")) {
if (ctx->args.type == ArchArgs::Z020)
new_cell->type = id_IOB33;
else
new_cell->type = id_IOB18;
if (ctx->args.type == ArchArgs::Z020)
new_cell->type = id_IOB33;
else
new_cell->type = id_IOB18;
add_port(ctx, new_cell.get(), "I", PORT_OUT);
add_port(ctx, new_cell.get(), "O", PORT_IN);
} else if (type == id_BUFGCTRL) {
@ -120,8 +120,7 @@ void dff_to_lc(const Context *ctx, CellInfo *dff, CellInfo *lc, bool pass_thru_l
if (get_net_or_empty(dff, id_S) != gnd_net) {
lc->params[id_SR] = "SRHIGH";
replace_port(dff, id_S, lc, id_SR);
}
else
} else
disconnect_port(ctx, dff, id_S);
lc->params[ctx->id("SYNC_ATTR")] = "SYNC";
} else if (*citer == 'R') {
@ -129,8 +128,7 @@ void dff_to_lc(const Context *ctx, CellInfo *dff, CellInfo *lc, bool pass_thru_l
if (get_net_or_empty(dff, id_R) != gnd_net) {
lc->params[id_SR] = "SRLOW";
replace_port(dff, id_R, lc, id_SR);
}
else
} else
disconnect_port(ctx, dff, id_R);
lc->params[ctx->id("SYNC_ATTR")] = "SYNC";
} else if (*citer == 'C') {
@ -138,8 +136,7 @@ void dff_to_lc(const Context *ctx, CellInfo *dff, CellInfo *lc, bool pass_thru_l
if (get_net_or_empty(dff, id_CLR) != gnd_net) {
lc->params[id_SR] = "SRLOW";
replace_port(dff, id_CLR, lc, id_SR);
}
else
} else
disconnect_port(ctx, dff, id_CLR);
lc->params[ctx->id("SYNC_ATTR")] = "ASYNC";
} else {
@ -148,8 +145,7 @@ void dff_to_lc(const Context *ctx, CellInfo *dff, CellInfo *lc, bool pass_thru_l
if (get_net_or_empty(dff, id_PRE) != gnd_net) {
lc->params[id_SR] = "SRHIGH";
replace_port(dff, id_PRE, lc, id_SR);
}
else
} else
disconnect_port(ctx, dff, id_PRE);
lc->params[ctx->id("SYNC_ATTR")] = "ASYNC";
}

3
xc7/delay.cc
View File

@ -49,8 +49,7 @@ delay_t Arch::estimateDelay(WireId src, WireId dst) const
return div_LH.quot * 360 + div_LVB.quot * 300 + div_LV.quot * 350 +
(div_H6.quot + div_H4.quot + div_V6.quot + div_V4.quot) * 210 + (div_H2.quot + div_V2.quot) * 170 +
(num_H1 + num_V1) * 150;
}
else {
} else {
auto src_y = src_loc.second;
auto dst_y = dst_loc.second;
auto div_src_y = std::div(src_y, 52);

742
xc7/gfx.cc
View File

@ -21,746 +21,4 @@
NEXTPNR_NAMESPACE_BEGIN
void gfxTileWire(std::vector<GraphicElement> &g, int x, int y, GfxTileWireId id, GraphicElement::style_t style)
{
GraphicElement el;
el.type = GraphicElement::TYPE_LINE;
el.style = style;
// Horizontal Span-4 Wires
if (id >= TILE_WIRE_SP4_H_L_36 && id <= TILE_WIRE_SP4_H_L_47) {
int idx = (id - TILE_WIRE_SP4_H_L_36) + 48;
float y1 = y + 1.0 - (0.03 + 0.0025 * (60 - (idx ^ 1)));
float y2 = y + 1.0 - (0.03 + 0.0025 * (60 - idx));
el.x1 = x;
el.x2 = x + 0.01;
el.y1 = y1;
el.y2 = y1;
g.push_back(el);
el.x1 = x + 0.01;
el.x2 = x + 0.02;
el.y1 = y1;
el.y2 = y2;
g.push_back(el);
el.x1 = x + 0.02;
el.x2 = x + 0.9;
el.y1 = y2;
el.y2 = y2;
g.push_back(el);
el.x1 = x + main_swbox_x1 + 0.0025 * (idx + 35);
el.x2 = el.x1;
el.y1 = y2;
el.y2 = y + main_swbox_y2;
g.push_back(el);
}
if (id >= TILE_WIRE_SP4_H_R_0 && id <= TILE_WIRE_SP4_H_R_47) {
int idx = id - TILE_WIRE_SP4_H_R_0;
float y1 = y + 1.0 - (0.03 + 0.0025 * (60 - idx));
float y2 = y + 1.0 - (0.03 + 0.0025 * (60 - (idx ^ 1)));
float y3 = y + 1.0 - (0.03 + 0.0025 * (60 - (idx ^ 1) - 12));
if (idx >= 12) {
el.x1 = x;
el.x2 = x + 0.01;
el.y1 = y1;
el.y2 = y1;
g.push_back(el);
el.x1 = x + 0.01;
el.x2 = x + 0.02;
el.y1 = y1;
el.y2 = y2;
g.push_back(el);
}
el.x1 = x + 0.02;
el.x2 = x + 0.9;
el.y1 = y2;
el.y2 = y2;
g.push_back(el);
el.x1 = x + 0.9;
el.x2 = x + 1.0;
el.y1 = y2;
el.y2 = y3;
g.push_back(el);
el.x1 = x + main_swbox_x1 + 0.0025 * ((idx ^ 1) + 35);
el.x2 = el.x1;
el.y1 = y2;
el.y2 = y + main_swbox_y2;
g.push_back(el);
}
// Vertical Span-4 Wires
if (id >= TILE_WIRE_SP4_V_T_36 && id <= TILE_WIRE_SP4_V_T_47) {
int idx = (id - TILE_WIRE_SP4_V_T_36) + 48;
float x1 = x + 0.03 + 0.0025 * (60 - (idx ^ 1));
float x2 = x + 0.03 + 0.0025 * (60 - idx);
el.y1 = y + 1.00;
el.y2 = y + 0.99;
el.x1 = x1;
el.x2 = x1;
g.push_back(el);
el.y1 = y + 0.99;
el.y2 = y + 0.98;
el.x1 = x1;
el.x2 = x2;
g.push_back(el);
el.y1 = y + 0.98;
el.y2 = y + 0.10;
el.x1 = x2;
el.x2 = x2;
g.push_back(el);
el.y1 = y + 1.0 - (0.03 + 0.0025 * (270 - idx));
el.y2 = el.y1;
el.x1 = x2;
el.x2 = x + main_swbox_x1;
g.push_back(el);
}
if (id >= TILE_WIRE_SP4_V_B_0 && id <= TILE_WIRE_SP4_V_B_47) {
int idx = id - TILE_WIRE_SP4_V_B_0;
float x1 = x + 0.03 + 0.0025 * (60 - idx);
float x2 = x + 0.03 + 0.0025 * (60 - (idx ^ 1));
float x3 = x + 0.03 + 0.0025 * (60 - (idx ^ 1) - 12);
if (idx >= 12) {
el.y1 = y + 1.00;
el.y2 = y + 0.99;
el.x1 = x1;
el.x2 = x1;
g.push_back(el);
el.y1 = y + 0.99;
el.y2 = y + 0.98;
el.x1 = x1;
el.x2 = x2;
g.push_back(el);
}
el.y1 = y + 0.98;
el.y2 = y + 0.10;
el.x1 = x2;
el.x2 = x2;
g.push_back(el);
el.y1 = y + 0.10;
el.y2 = y;
el.x1 = x2;
el.x2 = x3;
g.push_back(el);
el.y1 = y + 1.0 - (0.03 + 0.0025 * (145 - (idx ^ 1)));
el.y2 = el.y1;
el.x1 = x;
el.x2 = x2;
g.push_back(el);
el.y1 = y + 1.0 - (0.03 + 0.0025 * (270 - (idx ^ 1)));
el.y2 = el.y1;
el.x1 = x2;
el.x2 = x + main_swbox_x1;
g.push_back(el);
}
// Horizontal Span-12 Wires
if (id >= TILE_WIRE_SP12_H_L_22 && id <= TILE_WIRE_SP12_H_L_23) {
int idx = (id - TILE_WIRE_SP12_H_L_22) + 24;
float y1 = y + 1.0 - (0.03 + 0.0025 * (90 - (idx ^ 1)));
float y2 = y + 1.0 - (0.03 + 0.0025 * (90 - idx));
el.x1 = x;
el.x2 = x + 0.01;
el.y1 = y1;
el.y2 = y1;
g.push_back(el);
el.x1 = x + 0.01;
el.x2 = x + 0.02;
el.y1 = y1;
el.y2 = y2;
g.push_back(el);
el.x1 = x + 0.02;
el.x2 = x + 0.98333;
el.y1 = y2;
el.y2 = y2;
g.push_back(el);
el.x1 = x + main_swbox_x1 + 0.0025 * (idx + 5);
el.x2 = el.x1;
el.y1 = y2;
el.y2 = y + main_swbox_y2;
g.push_back(el);
}
if (id >= TILE_WIRE_SP12_H_R_0 && id <= TILE_WIRE_SP12_H_R_23) {
int idx = id - TILE_WIRE_SP12_H_R_0;
float y1 = y + 1.0 - (0.03 + 0.0025 * (90 - idx));
float y2 = y + 1.0 - (0.03 + 0.0025 * (90 - (idx ^ 1)));
float y3 = y + 1.0 - (0.03 + 0.0025 * (90 - (idx ^ 1) - 2));
if (idx >= 2) {
el.x1 = x;
el.x2 = x + 0.01;
el.y1 = y1;
el.y2 = y1;
g.push_back(el);
el.x1 = x + 0.01;
el.x2 = x + 0.02;
el.y1 = y1;
el.y2 = y2;
g.push_back(el);
}
el.x1 = x + 0.02;
el.x2 = x + 0.98333;
el.y1 = y2;
el.y2 = y2;
g.push_back(el);
el.x1 = x + 0.98333;
el.x2 = x + 1.0;
el.y1 = y2;
el.y2 = y3;
g.push_back(el);
el.x1 = x + main_swbox_x1 + 0.0025 * ((idx ^ 1) + 5);
el.x2 = el.x1;
el.y1 = y2;
el.y2 = y + main_swbox_y2;
g.push_back(el);
}
// Vertical Right Span-4
if (id >= TILE_WIRE_SP4_R_V_B_0 && id <= TILE_WIRE_SP4_R_V_B_47) {
int idx = id - TILE_WIRE_SP4_R_V_B_0;
float y1 = y + 1.0 - (0.03 + 0.0025 * (145 - (idx ^ 1)));
el.y1 = y1;
el.y2 = y1;
el.x1 = x + main_swbox_x2;
el.x2 = x + 1.0;
g.push_back(el);
}
// Vertical Span-12 Wires
if (id >= TILE_WIRE_SP12_V_T_22 && id <= TILE_WIRE_SP12_V_T_23) {
int idx = (id - TILE_WIRE_SP12_V_T_22) + 24;
float x1 = x + 0.03 + 0.0025 * (90 - (idx ^ 1));
float x2 = x + 0.03 + 0.0025 * (90 - idx);
el.y1 = y + 1.00;
el.y2 = y + 0.99;
el.x1 = x1;
el.x2 = x1;
g.push_back(el);
el.y1 = y + 0.99;
el.y2 = y + 0.98;
el.x1 = x1;
el.x2 = x2;
g.push_back(el);
el.y1 = y + 0.98;
el.y2 = y + 0.01667;
el.x1 = x2;
el.x2 = x2;
g.push_back(el);
el.y1 = y + 1.0 - (0.03 + 0.0025 * (300 - idx));
el.y2 = el.y1;
el.x1 = x2;
el.x2 = x + main_swbox_x1;
g.push_back(el);
}
if (id >= TILE_WIRE_SP12_V_B_0 && id <= TILE_WIRE_SP12_V_B_23) {
int idx = id - TILE_WIRE_SP12_V_B_0;
float x1 = x + 0.03 + 0.0025 * (90 - idx);
float x2 = x + 0.03 + 0.0025 * (90 - (idx ^ 1));
float x3 = x + 0.03 + 0.0025 * (90 - (idx ^ 1) - 2);
if (idx >= 2) {
el.y1 = y + 1.00;
el.y2 = y + 0.99;
el.x1 = x1;
el.x2 = x1;
g.push_back(el);
el.y1 = y + 0.99;
el.y2 = y + 0.98;
el.x1 = x1;
el.x2 = x2;
g.push_back(el);
}
el.y1 = y + 0.98;
el.y2 = y + 0.01667;
el.x1 = x2;
el.x2 = x2;
g.push_back(el);
el.y1 = y + 0.01667;
el.y2 = y;
el.x1 = x2;
el.x2 = x3;
g.push_back(el);
el.y1 = y + 1.0 - (0.03 + 0.0025 * (300 - (idx ^ 1)));
el.y2 = el.y1;
el.x1 = x2;
el.x2 = x + main_swbox_x1;
g.push_back(el);
}
// Global2Local
if (id >= TILE_WIRE_GLB2LOCAL_0 && id <= TILE_WIRE_GLB2LOCAL_3) {
int idx = id - TILE_WIRE_GLB2LOCAL_0;
el.x1 = x + main_swbox_x1 + 0.005 * (idx + 5);
el.x2 = el.x1;
el.y1 = y + main_swbox_y1;
el.y2 = el.y1 - 0.02;
g.push_back(el);
}
// GlobalNets
if (id >= TILE_WIRE_GLB_NETWK_0 && id <= TILE_WIRE_GLB_NETWK_7) {
int idx = id - TILE_WIRE_GLB_NETWK_0;
el.x1 = x + main_swbox_x1 - 0.05;
el.x2 = x + main_swbox_x1;
el.y1 = y + main_swbox_y1 + 0.005 * (13 - idx);
el.y2 = el.y1;
g.push_back(el);
}
// Neighbours
if (id >= TILE_WIRE_NEIGH_OP_BNL_0 && id <= TILE_WIRE_NEIGH_OP_TOP_7) {
int idx = id - TILE_WIRE_NEIGH_OP_BNL_0;
el.y1 = y + main_swbox_y2 - (0.0025 * (idx + 10) + 0.01 * (idx / 8));
el.y2 = el.y1;
el.x1 = x + main_swbox_x1 - 0.05;
el.x2 = x + main_swbox_x1;
g.push_back(el);
}
// Local Tracks
if (id >= TILE_WIRE_LOCAL_G0_0 && id <= TILE_WIRE_LOCAL_G3_7) {
int idx = id - TILE_WIRE_LOCAL_G0_0;
el.x1 = x + main_swbox_x2;
el.x2 = x + local_swbox_x1;
float yoff = y + (local_swbox_y1 + local_swbox_y2) / 2 - 0.005 * 16 - 0.075;
el.y1 = yoff + 0.005 * idx + 0.05 * (idx / 8);
el.y2 = el.y1;
g.push_back(el);
}
// LC Inputs
if (id >= TILE_WIRE_LUTFF_0_IN_0 && id <= TILE_WIRE_LUTFF_7_IN_3) {
int idx = id - TILE_WIRE_LUTFF_0_IN_0;
int z = idx / 4;
int input = idx % 4;
el.x1 = x + local_swbox_x2;
el.x2 = x + lut_swbox_x1;
el.y1 = y + (logic_cell_y1 + logic_cell_y2) / 2 - 0.0075 + (0.005 * input) + z * logic_cell_pitch;
el.y2 = el.y1;
g.push_back(el);
}
if (id >= TILE_WIRE_LUTFF_0_IN_0_LUT && id <= TILE_WIRE_LUTFF_7_IN_3_LUT) {
int idx = id - TILE_WIRE_LUTFF_0_IN_0_LUT;
int z = idx / 4;
int input = idx % 4;
el.x1 = x + lut_swbox_x2;
el.x2 = x + logic_cell_x1;
el.y1 = y + (logic_cell_y1 + logic_cell_y2) / 2 - 0.0075 + (0.005 * input) + z * logic_cell_pitch;
el.y2 = el.y1;
g.push_back(el);
}
// LC Outputs
if (id >= TILE_WIRE_LUTFF_0_OUT && id <= TILE_WIRE_LUTFF_7_OUT) {
int idx = id - TILE_WIRE_LUTFF_0_OUT;
float y1 = y + 1.0 - (0.03 + 0.0025 * (152 + idx));
el.y1 = y1;
el.y2 = y1;
el.x1 = x + main_swbox_x2;
el.x2 = x + 0.97 + 0.0025 * (7 - idx);
g.push_back(el);
el.y1 = y1;
el.y2 = y + (logic_cell_y1 + logic_cell_y2) / 2 + idx * logic_cell_pitch;
el.x1 = el.x2;
g.push_back(el);
el.y1 = el.y2;
el.x1 = x + logic_cell_x2;
g.push_back(el);
}
// LC Control
if (id >= TILE_WIRE_LUTFF_GLOBAL_CEN && id <= TILE_WIRE_LUTFF_GLOBAL_S_R) {
int idx = id - TILE_WIRE_LUTFF_GLOBAL_CEN;
el.x1 = x + main_swbox_x2 - 0.005 * (idx + 5);
el.x2 = el.x1;
el.y1 = y + main_swbox_y1;
el.y2 = el.y1 - 0.005 * (idx + 2);
g.push_back(el);
el.y1 = el.y2;
el.x2 = x + logic_cell_x2 - 0.005 * (2 - idx + 5);
g.push_back(el);
el.y2 = y + logic_cell_y1;
el.x1 = el.x2;
g.push_back(el);
for (int i = 0; i < 7; i++) {
el.y1 = y + logic_cell_y2 + i * logic_cell_pitch;
el.y2 = y + logic_cell_y1 + (i + 1) * logic_cell_pitch;
g.push_back(el);
}
}
// LC Cascade
if (id >= TILE_WIRE_LUTFF_0_LOUT && id <= TILE_WIRE_LUTFF_6_LOUT) {
int idx = id - TILE_WIRE_LUTFF_0_LOUT;
el.x1 = x + logic_cell_x1 + 0.005 * 5;
el.x2 = el.x1;
el.y1 = y + logic_cell_y2 + idx * logic_cell_pitch;
el.y2 = y + logic_cell_y1 + (idx + 1) * logic_cell_pitch;
g.push_back(el);
}
// Carry Chain
if (id >= TILE_WIRE_LUTFF_0_COUT && id <= TILE_WIRE_LUTFF_7_COUT) {
int idx = id - TILE_WIRE_LUTFF_0_COUT;
el.x1 = x + logic_cell_x1 + 0.005 * 3;
el.x2 = el.x1;
el.y1 = y + logic_cell_y2 + idx * logic_cell_pitch;
el.y2 = y + (idx < 7 ? logic_cell_y1 + (idx + 1) * logic_cell_pitch : 1.0);
g.push_back(el);
}
if (id == TILE_WIRE_CARRY_IN) {
el.x1 = x + logic_cell_x1 + 0.005 * 3;
el.x2 = el.x1;
el.y1 = y;
el.y2 = y + 0.01;
g.push_back(el);
}
if (id == TILE_WIRE_CARRY_IN_MUX) {
el.x1 = x + logic_cell_x1 + 0.005 * 3;
el.x2 = el.x1;
el.y1 = y + 0.02;
el.y2 = y + logic_cell_y1;
g.push_back(el);
}
}
static bool getWireXY_main(GfxTileWireId id, float &x, float &y)
{
// Horizontal Span-4 Wires
if (id >= TILE_WIRE_SP4_H_L_36 && id <= TILE_WIRE_SP4_H_L_47) {
int idx = (id - TILE_WIRE_SP4_H_L_36) + 48;
x = main_swbox_x1 + 0.0025 * (idx + 35);
y = main_swbox_y2;
return true;
}
if (id >= TILE_WIRE_SP4_H_R_0 && id <= TILE_WIRE_SP4_H_R_47) {
int idx = id - TILE_WIRE_SP4_H_R_0;
x = main_swbox_x1 + 0.0025 * ((idx ^ 1) + 35);
y = main_swbox_y2;
return true;
}
// Vertical Span-4 Wires
if (id >= TILE_WIRE_SP4_V_T_36 && id <= TILE_WIRE_SP4_V_T_47) {
int idx = (id - TILE_WIRE_SP4_V_T_36) + 48;
y = 1.0 - (0.03 + 0.0025 * (270 - idx));
x = main_swbox_x1;
return true;
}
if (id >= TILE_WIRE_SP4_V_B_0 && id <= TILE_WIRE_SP4_V_B_47) {
int idx = id - TILE_WIRE_SP4_V_B_0;
y = 1.0 - (0.03 + 0.0025 * (270 - (idx ^ 1)));
x = main_swbox_x1;
return true;
}
// Horizontal Span-12 Wires
if (id >= TILE_WIRE_SP12_H_L_22 && id <= TILE_WIRE_SP12_H_L_23) {
int idx = (id - TILE_WIRE_SP12_H_L_22) + 24;
x = main_swbox_x1 + 0.0025 * (idx + 5);
y = main_swbox_y2;
return true;
}
if (id >= TILE_WIRE_SP12_H_R_0 && id <= TILE_WIRE_SP12_H_R_23) {
int idx = id - TILE_WIRE_SP12_H_R_0;
x = main_swbox_x1 + 0.0025 * ((idx ^ 1) + 5);
y = main_swbox_y2;
return true;
}
// Vertical Right Span-4
if (id >= TILE_WIRE_SP4_R_V_B_0 && id <= TILE_WIRE_SP4_R_V_B_47) {
int idx = id - TILE_WIRE_SP4_R_V_B_0;
y = 1.0 - (0.03 + 0.0025 * (145 - (idx ^ 1)));
x = main_swbox_x2;
return true;
}
// Vertical Span-12 Wires
if (id >= TILE_WIRE_SP12_V_T_22 && id <= TILE_WIRE_SP12_V_T_23) {
int idx = (id - TILE_WIRE_SP12_V_T_22) + 24;
y = 1.0 - (0.03 + 0.0025 * (300 - idx));
x = main_swbox_x1;
return true;
}
if (id >= TILE_WIRE_SP12_V_B_0 && id <= TILE_WIRE_SP12_V_B_23) {
int idx = id - TILE_WIRE_SP12_V_B_0;
y = 1.0 - (0.03 + 0.0025 * (300 - (idx ^ 1)));
x = main_swbox_x1;
return true;
}
// Global2Local
if (id >= TILE_WIRE_GLB2LOCAL_0 && id <= TILE_WIRE_GLB2LOCAL_3) {
int idx = id - TILE_WIRE_GLB2LOCAL_0;
x = main_swbox_x1 + 0.005 * (idx + 5);
y = main_swbox_y1;
return true;
}
// GlobalNets
if (id >= TILE_WIRE_GLB_NETWK_0 && id <= TILE_WIRE_GLB_NETWK_7) {
int idx = id - TILE_WIRE_GLB_NETWK_0;
x = main_swbox_x1;
y = main_swbox_y1 + 0.005 * (13 - idx);
return true;
}
// Neighbours
if (id >= TILE_WIRE_NEIGH_OP_BNL_0 && id <= TILE_WIRE_NEIGH_OP_TOP_7) {
int idx = id - TILE_WIRE_NEIGH_OP_BNL_0;
y = main_swbox_y2 - (0.0025 * (idx + 10) + 0.01 * (idx / 8));
x = main_swbox_x1;
return true;
}
// Local Tracks
if (id >= TILE_WIRE_LOCAL_G0_0 && id <= TILE_WIRE_LOCAL_G3_7) {
int idx = id - TILE_WIRE_LOCAL_G0_0;
float yoff = (local_swbox_y1 + local_swbox_y2) / 2 - 0.005 * 16 - 0.075;
x = main_swbox_x2;
y = yoff + 0.005 * idx + 0.05 * (idx / 8);
return true;
}
// LC Outputs
if (id >= TILE_WIRE_LUTFF_0_OUT && id <= TILE_WIRE_LUTFF_7_OUT) {
int idx = id - TILE_WIRE_LUTFF_0_OUT;
y = 1.0 - (0.03 + 0.0025 * (152 + idx));
x = main_swbox_x2;
return true;
}
// LC Control
if (id >= TILE_WIRE_LUTFF_GLOBAL_CEN && id <= TILE_WIRE_LUTFF_GLOBAL_S_R) {
int idx = id - TILE_WIRE_LUTFF_GLOBAL_CEN;
x = main_swbox_x2 - 0.005 * (idx + 5);
y = main_swbox_y1;
return true;
}
return false;
}
static bool getWireXY_local(GfxTileWireId id, float &x, float &y)
{
if (id >= TILE_WIRE_LOCAL_G0_0 && id <= TILE_WIRE_LOCAL_G3_7) {
int idx = id - TILE_WIRE_LOCAL_G0_0;
float yoff = (local_swbox_y1 + local_swbox_y2) / 2 - 0.005 * 16 - 0.075;
x = local_swbox_x1;
y = yoff + 0.005 * idx + 0.05 * (idx / 8);
return true;
}
if (id >= TILE_WIRE_LUTFF_0_IN_0 && id <= TILE_WIRE_LUTFF_7_IN_3) {
int idx = id - TILE_WIRE_LUTFF_0_IN_0;
int z = idx / 4;
int input = idx % 4;
x = local_swbox_x2;
y = (logic_cell_y1 + logic_cell_y2) / 2 - 0.0075 + (0.005 * input) + z * logic_cell_pitch;
return true;
}
return false;
}
void pipGfx(std::vector<GraphicElement> &g, int x, int y, float x1, float y1, float x2, float y2, float swx1,
float swy1, float swx2, float swy2, GraphicElement::style_t style)
{
float tx = 0.5 * (x1 + x2);
float ty = 0.5 * (y1 + y2);
GraphicElement el;
el.type = GraphicElement::TYPE_ARROW;
el.style = style;
if (fabsf(x1 - swx1) < 0.001 && fabsf(x2 - swx1) < 0.001) {
tx = x1 + 0.25 * fabsf(y1 - y2);
goto edge_pip;
}
if (fabsf(x1 - swx2) < 0.001 && fabsf(x2 - swx2) < 0.001) {
tx = x1 - 0.25 * fabsf(y1 - y2);
goto edge_pip;
}
if (fabsf(y1 - swy1) < 0.001 && fabsf(y2 - swy1) < 0.001) {
ty = y1 + 0.25 * fabsf(x1 - x2);
goto edge_pip;
}
if (fabsf(y1 - swy1) < 0.001 && fabsf(y2 - swy1) < 0.001) {
ty = y1 + 0.25 * fabsf(x1 - x2);
goto edge_pip;
}
el.x1 = x + x1;
el.y1 = y + y1;
el.x2 = x + x2;
el.y2 = y + y2;
g.push_back(el);
return;
edge_pip:
el.x1 = x + x1;
el.y1 = y + y1;
el.x2 = x + tx;
el.y2 = y + ty;
g.push_back(el);
el.x1 = x + tx;
el.y1 = y + ty;
el.x2 = x + x2;
el.y2 = y + y2;
g.push_back(el);
}
void gfxTilePip(std::vector<GraphicElement> &g, int x, int y, GfxTileWireId src, GfxTileWireId dst,
GraphicElement::style_t style)
{
float x1, y1, x2, y2;
if (getWireXY_main(src, x1, y1) && getWireXY_main(dst, x2, y2)) {
pipGfx(g, x, y, x1, y1, x2, y2, main_swbox_x1, main_swbox_y1, main_swbox_x2, main_swbox_y2, style);
return;
}
if (getWireXY_local(src, x1, y1) && getWireXY_local(dst, x2, y2)) {
pipGfx(g, x, y, x1, y1, x2, y2, local_swbox_x1, local_swbox_y1, local_swbox_x2, local_swbox_y2, style);
return;
}
if (TILE_WIRE_LUTFF_0_IN_0_LUT <= src && src <= TILE_WIRE_LUTFF_7_IN_3_LUT && TILE_WIRE_LUTFF_0_OUT <= dst &&
dst <= TILE_WIRE_LUTFF_7_OUT) {
int lut_idx = (src - TILE_WIRE_LUTFF_0_IN_0_LUT) / 4;
int in_idx = (src - TILE_WIRE_LUTFF_0_IN_0_LUT) % 4;
GraphicElement el;
el.type = GraphicElement::TYPE_ARROW;
el.style = style;
el.x1 = x + logic_cell_x1;
el.x2 = x + logic_cell_x2;
el.y1 = y + (logic_cell_y1 + logic_cell_y2) / 2 - 0.0075 + (0.005 * in_idx) + lut_idx * logic_cell_pitch;
el.y2 = y + (logic_cell_y1 + logic_cell_y2) / 2 + lut_idx * logic_cell_pitch;
g.push_back(el);
return;
}
if (TILE_WIRE_LUTFF_0_IN_0 <= src && src <= TILE_WIRE_LUTFF_7_IN_3 && TILE_WIRE_LUTFF_0_IN_0_LUT <= dst &&
dst <= TILE_WIRE_LUTFF_7_IN_3_LUT) {
int lut_idx = (src - TILE_WIRE_LUTFF_0_IN_0) / 4;
int in_idx = (src - TILE_WIRE_LUTFF_0_IN_0) % 4;
int out_idx = (dst - TILE_WIRE_LUTFF_0_IN_0_LUT) % 4;
GraphicElement el;
el.type = GraphicElement::TYPE_ARROW;
el.style = style;
el.x1 = x + lut_swbox_x1;
el.x2 = x + lut_swbox_x2;
el.y1 = y + (logic_cell_y1 + logic_cell_y2) / 2 - 0.0075 + (0.005 * in_idx) + lut_idx * logic_cell_pitch;
el.y2 = y + (logic_cell_y1 + logic_cell_y2) / 2 - 0.0075 + (0.005 * out_idx) + lut_idx * logic_cell_pitch;
g.push_back(el);
return;
}
if (src == TILE_WIRE_CARRY_IN && dst == TILE_WIRE_CARRY_IN_MUX) {
GraphicElement el;
el.type = GraphicElement::TYPE_ARROW;
el.style = style;
el.x1 = x + logic_cell_x1 + 0.005 * 3;
el.x2 = el.x1;
el.y1 = y + 0.01;
el.y2 = y + 0.02;
g.push_back(el);
return;
}
}
NEXTPNR_NAMESPACE_END

475
xc7/gfx.h
View File

@ -43,481 +43,6 @@ const float logic_cell_y1 = 0.05;
const float logic_cell_y2 = 0.10;
const float logic_cell_pitch = 0.0625;
enum GfxTileWireId
{
TILE_WIRE_GLB2LOCAL_0,
TILE_WIRE_GLB2LOCAL_1,
TILE_WIRE_GLB2LOCAL_2,
TILE_WIRE_GLB2LOCAL_3,
TILE_WIRE_GLB_NETWK_0,
TILE_WIRE_GLB_NETWK_1,
TILE_WIRE_GLB_NETWK_2,
TILE_WIRE_GLB_NETWK_3,
TILE_WIRE_GLB_NETWK_4,
TILE_WIRE_GLB_NETWK_5,
TILE_WIRE_GLB_NETWK_6,
TILE_WIRE_GLB_NETWK_7,
TILE_WIRE_LOCAL_G0_0,
TILE_WIRE_LOCAL_G0_1,
TILE_WIRE_LOCAL_G0_2,
TILE_WIRE_LOCAL_G0_3,
TILE_WIRE_LOCAL_G0_4,
TILE_WIRE_LOCAL_G0_5,
TILE_WIRE_LOCAL_G0_6,
TILE_WIRE_LOCAL_G0_7,
TILE_WIRE_LOCAL_G1_0,
TILE_WIRE_LOCAL_G1_1,
TILE_WIRE_LOCAL_G1_2,
TILE_WIRE_LOCAL_G1_3,
TILE_WIRE_LOCAL_G1_4,
TILE_WIRE_LOCAL_G1_5,
TILE_WIRE_LOCAL_G1_6,
TILE_WIRE_LOCAL_G1_7,
TILE_WIRE_LOCAL_G2_0,
TILE_WIRE_LOCAL_G2_1,
TILE_WIRE_LOCAL_G2_2,
TILE_WIRE_LOCAL_G2_3,
TILE_WIRE_LOCAL_G2_4,
TILE_WIRE_LOCAL_G2_5,
TILE_WIRE_LOCAL_G2_6,
TILE_WIRE_LOCAL_G2_7,
TILE_WIRE_LOCAL_G3_0,
TILE_WIRE_LOCAL_G3_1,
TILE_WIRE_LOCAL_G3_2,
TILE_WIRE_LOCAL_G3_3,
TILE_WIRE_LOCAL_G3_4,
TILE_WIRE_LOCAL_G3_5,
TILE_WIRE_LOCAL_G3_6,
TILE_WIRE_LOCAL_G3_7,
TILE_WIRE_LUTFF_0_IN_0,
TILE_WIRE_LUTFF_0_IN_1,
TILE_WIRE_LUTFF_0_IN_2,
TILE_WIRE_LUTFF_0_IN_3,
TILE_WIRE_LUTFF_1_IN_0,
TILE_WIRE_LUTFF_1_IN_1,
TILE_WIRE_LUTFF_1_IN_2,
TILE_WIRE_LUTFF_1_IN_3,
TILE_WIRE_LUTFF_2_IN_0,
TILE_WIRE_LUTFF_2_IN_1,
TILE_WIRE_LUTFF_2_IN_2,
TILE_WIRE_LUTFF_2_IN_3,
TILE_WIRE_LUTFF_3_IN_0,
TILE_WIRE_LUTFF_3_IN_1,
TILE_WIRE_LUTFF_3_IN_2,
TILE_WIRE_LUTFF_3_IN_3,
TILE_WIRE_LUTFF_4_IN_0,
TILE_WIRE_LUTFF_4_IN_1,
TILE_WIRE_LUTFF_4_IN_2,
TILE_WIRE_LUTFF_4_IN_3,
TILE_WIRE_LUTFF_5_IN_0,
TILE_WIRE_LUTFF_5_IN_1,
TILE_WIRE_LUTFF_5_IN_2,
TILE_WIRE_LUTFF_5_IN_3,
TILE_WIRE_LUTFF_6_IN_0,
TILE_WIRE_LUTFF_6_IN_1,
TILE_WIRE_LUTFF_6_IN_2,
TILE_WIRE_LUTFF_6_IN_3,
TILE_WIRE_LUTFF_7_IN_0,
TILE_WIRE_LUTFF_7_IN_1,
TILE_WIRE_LUTFF_7_IN_2,
TILE_WIRE_LUTFF_7_IN_3,
TILE_WIRE_LUTFF_0_IN_0_LUT,
TILE_WIRE_LUTFF_0_IN_1_LUT,
TILE_WIRE_LUTFF_0_IN_2_LUT,
TILE_WIRE_LUTFF_0_IN_3_LUT,
TILE_WIRE_LUTFF_1_IN_0_LUT,
TILE_WIRE_LUTFF_1_IN_1_LUT,
TILE_WIRE_LUTFF_1_IN_2_LUT,
TILE_WIRE_LUTFF_1_IN_3_LUT,
TILE_WIRE_LUTFF_2_IN_0_LUT,
TILE_WIRE_LUTFF_2_IN_1_LUT,
TILE_WIRE_LUTFF_2_IN_2_LUT,
TILE_WIRE_LUTFF_2_IN_3_LUT,
TILE_WIRE_LUTFF_3_IN_0_LUT,
TILE_WIRE_LUTFF_3_IN_1_LUT,
TILE_WIRE_LUTFF_3_IN_2_LUT,
TILE_WIRE_LUTFF_3_IN_3_LUT,
TILE_WIRE_LUTFF_4_IN_0_LUT,
TILE_WIRE_LUTFF_4_IN_1_LUT,
TILE_WIRE_LUTFF_4_IN_2_LUT,
TILE_WIRE_LUTFF_4_IN_3_LUT,
TILE_WIRE_LUTFF_5_IN_0_LUT,
TILE_WIRE_LUTFF_5_IN_1_LUT,
TILE_WIRE_LUTFF_5_IN_2_LUT,
TILE_WIRE_LUTFF_5_IN_3_LUT,
TILE_WIRE_LUTFF_6_IN_0_LUT,
TILE_WIRE_LUTFF_6_IN_1_LUT,
TILE_WIRE_LUTFF_6_IN_2_LUT,
TILE_WIRE_LUTFF_6_IN_3_LUT,
TILE_WIRE_LUTFF_7_IN_0_LUT,
TILE_WIRE_LUTFF_7_IN_1_LUT,
TILE_WIRE_LUTFF_7_IN_2_LUT,
TILE_WIRE_LUTFF_7_IN_3_LUT,
TILE_WIRE_LUTFF_0_LOUT,
TILE_WIRE_LUTFF_1_LOUT,
TILE_WIRE_LUTFF_2_LOUT,
TILE_WIRE_LUTFF_3_LOUT,
TILE_WIRE_LUTFF_4_LOUT,
TILE_WIRE_LUTFF_5_LOUT,
TILE_WIRE_LUTFF_6_LOUT,
TILE_WIRE_LUTFF_0_OUT,
TILE_WIRE_LUTFF_1_OUT,
TILE_WIRE_LUTFF_2_OUT,
TILE_WIRE_LUTFF_3_OUT,
TILE_WIRE_LUTFF_4_OUT,
TILE_WIRE_LUTFF_5_OUT,
TILE_WIRE_LUTFF_6_OUT,
TILE_WIRE_LUTFF_7_OUT,
TILE_WIRE_LUTFF_0_COUT,
TILE_WIRE_LUTFF_1_COUT,
TILE_WIRE_LUTFF_2_COUT,
TILE_WIRE_LUTFF_3_COUT,
TILE_WIRE_LUTFF_4_COUT,
TILE_WIRE_LUTFF_5_COUT,
TILE_WIRE_LUTFF_6_COUT,
TILE_WIRE_LUTFF_7_COUT,
TILE_WIRE_LUTFF_GLOBAL_CEN,
TILE_WIRE_LUTFF_GLOBAL_CLK,
TILE_WIRE_LUTFF_GLOBAL_S_R,
TILE_WIRE_CARRY_IN,
TILE_WIRE_CARRY_IN_MUX,
TILE_WIRE_NEIGH_OP_BNL_0,
TILE_WIRE_NEIGH_OP_BNL_1,
TILE_WIRE_NEIGH_OP_BNL_2,
TILE_WIRE_NEIGH_OP_BNL_3,
TILE_WIRE_NEIGH_OP_BNL_4,
TILE_WIRE_NEIGH_OP_BNL_5,
TILE_WIRE_NEIGH_OP_BNL_6,
TILE_WIRE_NEIGH_OP_BNL_7,
TILE_WIRE_NEIGH_OP_BNR_0,
TILE_WIRE_NEIGH_OP_BNR_1,
TILE_WIRE_NEIGH_OP_BNR_2,
TILE_WIRE_NEIGH_OP_BNR_3,
TILE_WIRE_NEIGH_OP_BNR_4,
TILE_WIRE_NEIGH_OP_BNR_5,
TILE_WIRE_NEIGH_OP_BNR_6,
TILE_WIRE_NEIGH_OP_BNR_7,
TILE_WIRE_NEIGH_OP_BOT_0,
TILE_WIRE_NEIGH_OP_BOT_1,
TILE_WIRE_NEIGH_OP_BOT_2,
TILE_WIRE_NEIGH_OP_BOT_3,
TILE_WIRE_NEIGH_OP_BOT_4,
TILE_WIRE_NEIGH_OP_BOT_5,
TILE_WIRE_NEIGH_OP_BOT_6,
TILE_WIRE_NEIGH_OP_BOT_7,
TILE_WIRE_NEIGH_OP_LFT_0,
TILE_WIRE_NEIGH_OP_LFT_1,
TILE_WIRE_NEIGH_OP_LFT_2,
TILE_WIRE_NEIGH_OP_LFT_3,
TILE_WIRE_NEIGH_OP_LFT_4,
TILE_WIRE_NEIGH_OP_LFT_5,
TILE_WIRE_NEIGH_OP_LFT_6,
TILE_WIRE_NEIGH_OP_LFT_7,
TILE_WIRE_NEIGH_OP_RGT_0,
TILE_WIRE_NEIGH_OP_RGT_1,
TILE_WIRE_NEIGH_OP_RGT_2,
TILE_WIRE_NEIGH_OP_RGT_3,
TILE_WIRE_NEIGH_OP_RGT_4,
TILE_WIRE_NEIGH_OP_RGT_5,
TILE_WIRE_NEIGH_OP_RGT_6,
TILE_WIRE_NEIGH_OP_RGT_7,
TILE_WIRE_NEIGH_OP_TNL_0,
TILE_WIRE_NEIGH_OP_TNL_1,
TILE_WIRE_NEIGH_OP_TNL_2,
TILE_WIRE_NEIGH_OP_TNL_3,
TILE_WIRE_NEIGH_OP_TNL_4,
TILE_WIRE_NEIGH_OP_TNL_5,
TILE_WIRE_NEIGH_OP_TNL_6,
TILE_WIRE_NEIGH_OP_TNL_7,
TILE_WIRE_NEIGH_OP_TNR_0,
TILE_WIRE_NEIGH_OP_TNR_1,
TILE_WIRE_NEIGH_OP_TNR_2,
TILE_WIRE_NEIGH_OP_TNR_3,
TILE_WIRE_NEIGH_OP_TNR_4,
TILE_WIRE_NEIGH_OP_TNR_5,
TILE_WIRE_NEIGH_OP_TNR_6,
TILE_WIRE_NEIGH_OP_TNR_7,
TILE_WIRE_NEIGH_OP_TOP_0,
TILE_WIRE_NEIGH_OP_TOP_1,
TILE_WIRE_NEIGH_OP_TOP_2,
TILE_WIRE_NEIGH_OP_TOP_3,
TILE_WIRE_NEIGH_OP_TOP_4,
TILE_WIRE_NEIGH_OP_TOP_5,
TILE_WIRE_NEIGH_OP_TOP_6,
TILE_WIRE_NEIGH_OP_TOP_7,
TILE_WIRE_SP4_V_B_0,
TILE_WIRE_SP4_V_B_1,
TILE_WIRE_SP4_V_B_2,
TILE_WIRE_SP4_V_B_3,
TILE_WIRE_SP4_V_B_4,
TILE_WIRE_SP4_V_B_5,
TILE_WIRE_SP4_V_B_6,
TILE_WIRE_SP4_V_B_7,
TILE_WIRE_SP4_V_B_8,
TILE_WIRE_SP4_V_B_9,
TILE_WIRE_SP4_V_B_10,
TILE_WIRE_SP4_V_B_11,
TILE_WIRE_SP4_V_B_12,
TILE_WIRE_SP4_V_B_13,
TILE_WIRE_SP4_V_B_14,
TILE_WIRE_SP4_V_B_15,
TILE_WIRE_SP4_V_B_16,
TILE_WIRE_SP4_V_B_17,
TILE_WIRE_SP4_V_B_18,
TILE_WIRE_SP4_V_B_19,
TILE_WIRE_SP4_V_B_20,
TILE_WIRE_SP4_V_B_21,
TILE_WIRE_SP4_V_B_22,
TILE_WIRE_SP4_V_B_23,
TILE_WIRE_SP4_V_B_24,
TILE_WIRE_SP4_V_B_25,
TILE_WIRE_SP4_V_B_26,
TILE_WIRE_SP4_V_B_27,
TILE_WIRE_SP4_V_B_28,
TILE_WIRE_SP4_V_B_29,
TILE_WIRE_SP4_V_B_30,
TILE_WIRE_SP4_V_B_31,
TILE_WIRE_SP4_V_B_32,
TILE_WIRE_SP4_V_B_33,
TILE_WIRE_SP4_V_B_34,
TILE_WIRE_SP4_V_B_35,
TILE_WIRE_SP4_V_B_36,
TILE_WIRE_SP4_V_B_37,
TILE_WIRE_SP4_V_B_38,
TILE_WIRE_SP4_V_B_39,
TILE_WIRE_SP4_V_B_40,
TILE_WIRE_SP4_V_B_41,
TILE_WIRE_SP4_V_B_42,
TILE_WIRE_SP4_V_B_43,
TILE_WIRE_SP4_V_B_44,
TILE_WIRE_SP4_V_B_45,
TILE_WIRE_SP4_V_B_46,
TILE_WIRE_SP4_V_B_47,
TILE_WIRE_SP4_V_T_36,
TILE_WIRE_SP4_V_T_37,
TILE_WIRE_SP4_V_T_38,
TILE_WIRE_SP4_V_T_39,
TILE_WIRE_SP4_V_T_40,
TILE_WIRE_SP4_V_T_41,
TILE_WIRE_SP4_V_T_42,
TILE_WIRE_SP4_V_T_43,
TILE_WIRE_SP4_V_T_44,
TILE_WIRE_SP4_V_T_45,
TILE_WIRE_SP4_V_T_46,
TILE_WIRE_SP4_V_T_47,
TILE_WIRE_SP4_R_V_B_0,
TILE_WIRE_SP4_R_V_B_1,
TILE_WIRE_SP4_R_V_B_2,
TILE_WIRE_SP4_R_V_B_3,
TILE_WIRE_SP4_R_V_B_4,
TILE_WIRE_SP4_R_V_B_5,
TILE_WIRE_SP4_R_V_B_6,
TILE_WIRE_SP4_R_V_B_7,
TILE_WIRE_SP4_R_V_B_8,
TILE_WIRE_SP4_R_V_B_9,
TILE_WIRE_SP4_R_V_B_10,
TILE_WIRE_SP4_R_V_B_11,
TILE_WIRE_SP4_R_V_B_12,
TILE_WIRE_SP4_R_V_B_13,
TILE_WIRE_SP4_R_V_B_14,
TILE_WIRE_SP4_R_V_B_15,
TILE_WIRE_SP4_R_V_B_16,
TILE_WIRE_SP4_R_V_B_17,
TILE_WIRE_SP4_R_V_B_18,
TILE_WIRE_SP4_R_V_B_19,
TILE_WIRE_SP4_R_V_B_20,
TILE_WIRE_SP4_R_V_B_21,
TILE_WIRE_SP4_R_V_B_22,
TILE_WIRE_SP4_R_V_B_23,
TILE_WIRE_SP4_R_V_B_24,
TILE_WIRE_SP4_R_V_B_25,
TILE_WIRE_SP4_R_V_B_26,
TILE_WIRE_SP4_R_V_B_27,
TILE_WIRE_SP4_R_V_B_28,
TILE_WIRE_SP4_R_V_B_29,
TILE_WIRE_SP4_R_V_B_30,
TILE_WIRE_SP4_R_V_B_31,
TILE_WIRE_SP4_R_V_B_32,
TILE_WIRE_SP4_R_V_B_33,
TILE_WIRE_SP4_R_V_B_34,
TILE_WIRE_SP4_R_V_B_35,
TILE_WIRE_SP4_R_V_B_36,
TILE_WIRE_SP4_R_V_B_37,
TILE_WIRE_SP4_R_V_B_38,
TILE_WIRE_SP4_R_V_B_39,
TILE_WIRE_SP4_R_V_B_40,
TILE_WIRE_SP4_R_V_B_41,
TILE_WIRE_SP4_R_V_B_42,
TILE_WIRE_SP4_R_V_B_43,
TILE_WIRE_SP4_R_V_B_44,
TILE_WIRE_SP4_R_V_B_45,
TILE_WIRE_SP4_R_V_B_46,
TILE_WIRE_SP4_R_V_B_47,
TILE_WIRE_SP4_H_L_36,
TILE_WIRE_SP4_H_L_37,
TILE_WIRE_SP4_H_L_38,
TILE_WIRE_SP4_H_L_39,
TILE_WIRE_SP4_H_L_40,
TILE_WIRE_SP4_H_L_41,
TILE_WIRE_SP4_H_L_42,
TILE_WIRE_SP4_H_L_43,
TILE_WIRE_SP4_H_L_44,
TILE_WIRE_SP4_H_L_45,
TILE_WIRE_SP4_H_L_46,
TILE_WIRE_SP4_H_L_47,
TILE_WIRE_SP4_H_R_0,
TILE_WIRE_SP4_H_R_1,
TILE_WIRE_SP4_H_R_2,
TILE_WIRE_SP4_H_R_3,
TILE_WIRE_SP4_H_R_4,
TILE_WIRE_SP4_H_R_5,
TILE_WIRE_SP4_H_R_6,
TILE_WIRE_SP4_H_R_7,
TILE_WIRE_SP4_H_R_8,
TILE_WIRE_SP4_H_R_9,
TILE_WIRE_SP4_H_R_10,
TILE_WIRE_SP4_H_R_11,
TILE_WIRE_SP4_H_R_12,
TILE_WIRE_SP4_H_R_13,
TILE_WIRE_SP4_H_R_14,
TILE_WIRE_SP4_H_R_15,
TILE_WIRE_SP4_H_R_16,
TILE_WIRE_SP4_H_R_17,
TILE_WIRE_SP4_H_R_18,
TILE_WIRE_SP4_H_R_19,
TILE_WIRE_SP4_H_R_20,
TILE_WIRE_SP4_H_R_21,
TILE_WIRE_SP4_H_R_22,
TILE_WIRE_SP4_H_R_23,
TILE_WIRE_SP4_H_R_24,
TILE_WIRE_SP4_H_R_25,
TILE_WIRE_SP4_H_R_26,
TILE_WIRE_SP4_H_R_27,
TILE_WIRE_SP4_H_R_28,
TILE_WIRE_SP4_H_R_29,
TILE_WIRE_SP4_H_R_30,
TILE_WIRE_SP4_H_R_31,
TILE_WIRE_SP4_H_R_32,
TILE_WIRE_SP4_H_R_33,
TILE_WIRE_SP4_H_R_34,
TILE_WIRE_SP4_H_R_35,
TILE_WIRE_SP4_H_R_36,
TILE_WIRE_SP4_H_R_37,
TILE_WIRE_SP4_H_R_38,
TILE_WIRE_SP4_H_R_39,
TILE_WIRE_SP4_H_R_40,
TILE_WIRE_SP4_H_R_41,
TILE_WIRE_SP4_H_R_42,
TILE_WIRE_SP4_H_R_43,
TILE_WIRE_SP4_H_R_44,
TILE_WIRE_SP4_H_R_45,
TILE_WIRE_SP4_H_R_46,
TILE_WIRE_SP4_H_R_47,
TILE_WIRE_SP12_V_B_0,
TILE_WIRE_SP12_V_B_1,
TILE_WIRE_SP12_V_B_2,
TILE_WIRE_SP12_V_B_3,
TILE_WIRE_SP12_V_B_4,
TILE_WIRE_SP12_V_B_5,
TILE_WIRE_SP12_V_B_6,
TILE_WIRE_SP12_V_B_7,
TILE_WIRE_SP12_V_B_8,
TILE_WIRE_SP12_V_B_9,
TILE_WIRE_SP12_V_B_10,
TILE_WIRE_SP12_V_B_11,
TILE_WIRE_SP12_V_B_12,
TILE_WIRE_SP12_V_B_13,
TILE_WIRE_SP12_V_B_14,
TILE_WIRE_SP12_V_B_15,
TILE_WIRE_SP12_V_B_16,
TILE_WIRE_SP12_V_B_17,
TILE_WIRE_SP12_V_B_18,
TILE_WIRE_SP12_V_B_19,
TILE_WIRE_SP12_V_B_20,
TILE_WIRE_SP12_V_B_21,
TILE_WIRE_SP12_V_B_22,
TILE_WIRE_SP12_V_B_23,
TILE_WIRE_SP12_V_T_22,
TILE_WIRE_SP12_V_T_23,
TILE_WIRE_SP12_H_R_0,
TILE_WIRE_SP12_H_R_1,
TILE_WIRE_SP12_H_R_2,
TILE_WIRE_SP12_H_R_3,
TILE_WIRE_SP12_H_R_4,
TILE_WIRE_SP12_H_R_5,
TILE_WIRE_SP12_H_R_6,
TILE_WIRE_SP12_H_R_7,
TILE_WIRE_SP12_H_R_8,
TILE_WIRE_SP12_H_R_9,
TILE_WIRE_SP12_H_R_10,
TILE_WIRE_SP12_H_R_11,
TILE_WIRE_SP12_H_R_12,
TILE_WIRE_SP12_H_R_13,
TILE_WIRE_SP12_H_R_14,
TILE_WIRE_SP12_H_R_15,
TILE_WIRE_SP12_H_R_16,
TILE_WIRE_SP12_H_R_17,
TILE_WIRE_SP12_H_R_18,
TILE_WIRE_SP12_H_R_19,
TILE_WIRE_SP12_H_R_20,
TILE_WIRE_SP12_H_R_21,
TILE_WIRE_SP12_H_R_22,
TILE_WIRE_SP12_H_R_23,
TILE_WIRE_SP12_H_L_22,
TILE_WIRE_SP12_H_L_23,
TILE_WIRE_PLLIN,
TILE_WIRE_PLLOUT_A,
TILE_WIRE_PLLOUT_B
};
void gfxTileWire(std::vector<GraphicElement> &g, int x, int y, GfxTileWireId id, GraphicElement::style_t style);
void gfxTilePip(std::vector<GraphicElement> &g, int x, int y, GfxTileWireId src, GfxTileWireId dst,
GraphicElement::style_t style);
NEXTPNR_NAMESPACE_END
#endif // GFX_H

5
xc7/main.cc
View File

@ -85,9 +85,7 @@ void Xc7CommandHandler::customBitstream(Context *ctx)
}
}
void Xc7CommandHandler::setupArchContext(Context *ctx)
{
}
void Xc7CommandHandler::setupArchContext(Context *ctx) {}
std::unique_ptr<Context> Xc7CommandHandler::createContext()
{
@ -101,7 +99,6 @@ std::unique_ptr<Context> Xc7CommandHandler::createContext()
chipArgs.package = "ffg1926";
}
if (chipArgs.type == ArchArgs::NONE) {
chipArgs.type = ArchArgs::Z020;
chipArgs.package = "clg400";

6
xc7/pack.cc
View File

@ -128,14 +128,14 @@ static bool net_is_constant(const Context *ctx, NetInfo *net, bool &value)
// Pack carry logic
static void pack_carries(Context *ctx)
{
//log_info("Packing carries..\n");
// log_info("Packing carries..\n");
// TODO
}
// "Pack" RAMs
static void pack_ram(Context *ctx)
{
//log_info("Packing RAMs..\n");
// log_info("Packing RAMs..\n");
// TODO
}
@ -550,7 +550,7 @@ static void pack_special(Context *ctx)
ci->params.emplace(ctx->id("TMUX_MUX_SEL"), "00");
ci->params.emplace(ctx->id("VLF_HIGH_DIS_B"), "TRUE");
ci->params.emplace(ctx->id("VLF_HIGH_PWDN_B"), "TRUE");
//ci->params.emplace(ctx->id("MMCME2_ADV:mmcm_adv_inst:");
// ci->params.emplace(ctx->id("MMCME2_ADV:mmcm_adv_inst:");
ci->params.emplace(ctx->id("ANALOG_MISC"), "0000");
ci->params.emplace(ctx->id("AVDD_COMP_SET"), "011");
ci->params.emplace(ctx->id("AVDD_VBG_PD"), "110");

17
xc7/xdl.cc
View File

@ -19,13 +19,13 @@
*
*/
#include "xdl.h"
#include <boost/range/adaptor/reversed.hpp>
#include <cctype>
#include <vector>
#include "cells.h"
#include "log.h"
#include "nextpnr.h"
#include "util.h"
#include <boost/range/adaptor/reversed.hpp>
#include "torc/Physical.hpp"
using namespace torc::architecture::xilinx;
@ -68,7 +68,8 @@ DesignSharedPtr create_torc_design(const Context *ctx)
const char *type;
if (cell.second->type == id_SLICE_LUT6)
type = "SLICEL";
else if (cell.second->type == id_IOB33 || cell.second->type == id_IOB18 || cell.second->type == id_BUFGCTRL || cell.second->type == id_PS7 || cell.second->type == id_MMCME2_ADV)
else if (cell.second->type == id_IOB33 || cell.second->type == id_IOB18 || cell.second->type == id_BUFGCTRL ||
cell.second->type == id_PS7 || cell.second->type == id_MMCME2_ADV)
type = cell.second->type.c_str(ctx);
else
log_error("Unsupported cell type '%s'.\n", cell.second->type.c_str(ctx));
@ -187,7 +188,6 @@ DesignSharedPtr create_torc_design(const Context *ctx)
instPtr->setConfig("SYNC_ATTR", "", cell.second->params.at(ctx->id("SYNC_ATTR")));
if (get_net_or_empty(cell.second.get(), ctx->id("CE")))
instPtr->setConfig("CEUSEDMUX", "", "IN");
}
} else if (cell.second->type == id_IOB33) {
if (get_net_or_empty(cell.second.get(), id_I)) {
@ -211,8 +211,9 @@ DesignSharedPtr create_torc_design(const Context *ctx)
instPtr->setConfig("DRIVE", "", "12");
instPtr->setConfig("SLEW", "", "SLOW");
}
} else if (cell.second->type == id_BUFGCTRL || cell.second->type == id_PS7 || cell.second->type == id_MMCME2_ADV) {
for (const auto& i : cell.second->params)
} else if (cell.second->type == id_BUFGCTRL || cell.second->type == id_PS7 ||
cell.second->type == id_MMCME2_ADV) {
for (const auto &i : cell.second->params)
instPtr->setConfig(i.first.str(ctx), "", i.second);
} else
log_error("Unsupported cell type '%s'.\n", cell.second->type.c_str(ctx));
@ -247,10 +248,10 @@ DesignSharedPtr create_torc_design(const Context *ctx)
if (user.cell->type == id_SLICE_LUT6 && (pin_name[0] == 'I' || pin_name[0] == 'O')) {
const auto lut = bel_to_lut(user.cell->bel);
pin_name[0] = lut[0];
}
else {
} else {
// e.g. Convert DDRARB[0] -> DDRARB0
pin_name.erase(std::remove_if(pin_name.begin(), pin_name.end(), boost::is_any_of("[]")), pin_name.end());
pin_name.erase(std::remove_if(pin_name.begin(), pin_name.end(), boost::is_any_of("[]")),
pin_name.end());
}
pinPtr = Factory::newInstancePinPtr(instPtr, pin_name);
netPtr->addSink(pinPtr);