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Merge branch 'xc7' into xc7_gui

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This commit is contained in:
Eddie Hung 2018-12-28 00:03:01 -08:00
commit 0514fb9042
54 changed files with 280 additions and 5305 deletions
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2
.gitignore vendored
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@ -47,3 +47,5 @@ xilinx_device_details.xml
*_fpga_editor.*
*.twr
*.twx
*.nlf
*.sdf

3
.gitmodules vendored Normal file
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@ -0,0 +1,3 @@
[submodule "torc"]
path = torc
url = https://github.com/eddiehung/torc

13
README.md
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@ -1,6 +1,19 @@
nextpnr -- a portable FPGA place and route tool
===============================================
***
### NB: This nextpnr-xc7 branch is *unofficial*, *very* proof-of-concept, *very* experimental, *very* unoptimised, and is provided with *no support whatsoever*. Use at your own risk!
#### It leverages a [torc](https://github.com/torc-isi/torc) fork with minimal changes (those necessary to support building on later versions of gcc) to target XDL-compatible devices.
### Note that torc is licensed under GPLv3 which differs from nextpnr's ISC license, thus please respect the limitations imposed by both licenses.
Currently, only LUT1-6, IOB, BUFGCTRL, MMCME2_ADV are supported for xc7z020 and xc7vx680t (but trivial to add others).
The following example shell scripts are available:
* blinky.sh -- generates blinky.bit that flashes (with a delay) the 4 LEDs on a ZYBO Z7
* blinky_sim.sh -- post place-and-route simulation, without any delays (requires [GHDL](https://github.com/ghdl/ghdl))
* picorv32.sh -- just places-and-routes picorv32.ncd (no testbench)
* attosoc.sh -- generates attosoc.bit of a self-stimulating picorv32 device that displays (with a delay) prime numbers to the LEDs -- when testing on hardware, consider using a PLL (MMCM) to meet timing
* attosoc_sim.sh -- post place-and-route simulation of a self-stimulating picorv32 device, without any delays (requires [GHDL](https://github.com/ghdl/ghdl))
***
nextpnr aims to be a vendor neutral, timing driven, FOSS FPGA place and route
tool.

4
common/router1.cc
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@ -633,11 +633,7 @@ struct Router1
next_qw.penalty = next_penalty;
next_qw.bonus = next_bonus;
if (cfg.useEstimate) {
#ifdef ARCH_XC7
next_qw.togo = ctx->estimateDelay(next_wire, imux_wire);
#else
next_qw.togo = ctx->estimateDelay(next_wire, dst_wire);
#endif
delay_t this_est = next_qw.delay + next_qw.togo;
if (this_est / 2 - cfg.estimatePrecision > best_est)
continue;

1
torc Submodule

@ -0,0 +1 @@
Subproject commit a5a4ec057eae3ed07ed2acb9da13404808e37211

177
xc7/125MHz_to_60MHz.v
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@ -1,177 +0,0 @@
// file: clk_wiz_v3_6.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// "Output Output Phase Duty Pk-to-Pk Phase"
// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
//----------------------------------------------------------------------------
// CLK_OUT1____60.000______0.000______50.0______231.736____234.038
//
//----------------------------------------------------------------------------
// "Input Clock Freq (MHz) Input Jitter (UI)"
//----------------------------------------------------------------------------
// __primary_________125.000____________0.010
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "clk_wiz_v3_6,clk_wiz_v3_6,{component_name=clk_wiz_v3_6,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=MMCM_ADV,num_out_clk=1,clkin1_period=8.000,clkin2_period=10.000,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}" *)
module clk_wiz_v3_6
(// Clock in ports
input CLK_IN1,
// Clock out ports
output CLK_OUT1
);
// Input buffering
//------------------------------------
assign clkin1 = CLK_IN1;
// Clocking primitive
//------------------------------------
// Instantiation of the MMCM primitive
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire [15:0] do_unused;
wire drdy_unused;
wire psdone_unused;
wire locked_unused;
wire clkfbout;
wire clkfboutb_unused;
wire clkout0b_unused;
wire clkout1_unused;
wire clkout1b_unused;
wire clkout2_unused;
wire clkout2b_unused;
wire clkout3_unused;
wire clkout3b_unused;
wire clkout4_unused;
wire clkout5_unused;
wire clkout6_unused;
wire clkfbstopped_unused;
wire clkinstopped_unused;
MMCME2_ADV
#(.BANDWIDTH ("OPTIMIZED"),
.CLKOUT4_CASCADE ("FALSE"),
.COMPENSATION ("ZHOLD"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (5),
.CLKFBOUT_MULT_F (40.500),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_DIVIDE_F (16.875),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKIN1_PERIOD (8.000),
.REF_JITTER1 (0.010))
mmcm_adv_inst
// Output clocks
(.CLKFBOUT (clkfbout),
.CLKFBOUTB (clkfboutb_unused),
.CLKOUT0 (clkout0),
.CLKOUT0B (clkout0b_unused),
.CLKOUT1 (clkout1_unused),
.CLKOUT1B (clkout1b_unused),
.CLKOUT2 (clkout2_unused),
.CLKOUT2B (clkout2b_unused),
.CLKOUT3 (clkout3_unused),
.CLKOUT3B (clkout3b_unused),
.CLKOUT4 (clkout4_unused),
.CLKOUT5 (clkout5_unused),
.CLKOUT6 (clkout6_unused),
// Input clock control
.CLKFBIN (clkfbout),
.CLKIN1 (clkin1),
.CLKIN2 (1'b0),
// Tied to always select the primary input clock
.CLKINSEL (1'b1),
// Ports for dynamic reconfiguration
.DADDR (7'h0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'h0),
.DO (do_unused),
.DRDY (drdy_unused),
.DWE (1'b0),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (psdone_unused),
// Other control and status signals
.LOCKED (locked_unused),
.CLKINSTOPPED (clkinstopped_unused),
.CLKFBSTOPPED (clkfbstopped_unused),
.PWRDWN (1'b0),
.RST (1'b0));
// Output buffering
//-----------------------------------
//BUFG clkout1_buf
// (.O (CLK_OUT1),
// .I (clkout0));
// BUFG not currently supported
BUFGCTRL clkout1_buf (
.I0(clkout0),
.CE0(1'b1),
.S0(1'b1),
.O(CLK_OUT1)
);
endmodule

47
xc7/arch.cc
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@ -20,6 +20,7 @@
#include <algorithm>
#include <cmath>
#include <regex>
#include "cells.h"
#include "gfx.h"
#include "log.h"
@ -36,12 +37,12 @@ std::unique_ptr<const TorcInfo> torc_info;
TorcInfo::TorcInfo(BaseCtx *ctx, const std::string &inDeviceName, const std::string &inPackageName)
: TorcInfo(inDeviceName, inPackageName)
{
static const boost::regex re_loc(".+_X(\\d+)Y(\\d+)");
boost::cmatch what;
static const std::regex re_loc(".+_X(\\d+)Y(\\d+)");
std::cmatch what;
tile_to_xy.resize(tiles.getTileCount());
for (TileIndex tileIndex(0); tileIndex < tiles.getTileCount(); tileIndex++) {
const auto &tileInfo = tiles.getTileInfo(tileIndex);
if (!boost::regex_match(tileInfo.getName(), what, re_loc))
if (!std::regex_match(tileInfo.getName(), what, re_loc))
throw;
const auto x = boost::lexical_cast<int>(what.str(1));
const auto y = boost::lexical_cast<int>(what.str(2));
@ -68,7 +69,7 @@ TorcInfo::TorcInfo(BaseCtx *ctx, const std::string &inDeviceName, const std::str
bel_to_site_index.push_back(i);
site_index_to_type[i] = id_SLICE_LUT6;
const auto site_name = site.getName();
if (!boost::regex_match(site_name.c_str(), what, re_loc))
if (!std::regex_match(site_name.c_str(), what, re_loc))
throw;
const auto sx = boost::lexical_cast<int>(what.str(1));
if ((sx & 1) == 0) {
@ -110,16 +111,16 @@ TorcInfo::TorcInfo(BaseCtx *ctx, const std::string &inDeviceName, const std::str
bel_to_site_index.shrink_to_fit();
bel_to_loc.shrink_to_fit();
const boost::regex re_124("(.+_)?[NESW][NESWLR](\\d)((BEG(_[NS])?)|(END(_[NS])?)|[A-E])?\\d(_\\d)?");
const boost::regex re_L("(.+_)?L(H|V|VB)(_L)?\\d+(_\\d)?");
const boost::regex re_BYP("BYP(_ALT)?\\d");
const boost::regex re_BYP_B("BYP_[BL]\\d");
const boost::regex re_BOUNCE_NS("(BYP|FAN)_BOUNCE_[NS]3_\\d");
const boost::regex re_FAN("FAN(_ALT)?\\d");
const boost::regex re_CLB_I1_6("CLBL[LM]_(L|LL|M)_[A-D]([1-6])");
const boost::regex bufg_i("CLK_BUFG_BUFGCTRL\\d+_I0");
const boost::regex bufg_o("CLK_BUFG_BUFGCTRL\\d+_O");
const boost::regex hrow("CLK_HROW_CLK[01]_[34]");
const std::regex re_124("(.+_)?[NESW][NESWLR](\\d)((BEG(_[NS])?)|(END(_[NS])?)|[A-E])?\\d(_\\d)?");
const std::regex re_L("(.+_)?L(H|V|VB)(_L)?\\d+(_\\d)?");
const std::regex re_BYP("BYP(_ALT)?\\d");
const std::regex re_BYP_B("BYP_[BL]\\d");
const std::regex re_BOUNCE_NS("(BYP|FAN)_BOUNCE_[NS]3_\\d");
const std::regex re_FAN("FAN(_ALT)?\\d");
const std::regex re_CLB_I1_6("CLBL[LM]_(L|LL|M)_[A-D]([1-6])");
const std::regex bufg_i("CLK_BUFG_BUFGCTRL\\d+_I0");
const std::regex bufg_o("CLK_BUFG_BUFGCTRL\\d+_O");
const std::regex hrow("CLK_HROW_CLK[01]_[34]");
std::unordered_map</*TileTypeIndex*/ unsigned, std::vector<delay_t>> delay_lookup;
std::unordered_map<Segments::SegmentReference, TileIndex> segment_to_anchor;
Tilewire currentTilewire;
@ -171,7 +172,7 @@ TorcInfo::TorcInfo(BaseCtx *ctx, const std::string &inDeviceName, const std::str
for (WireIndex wireIndex(0); wireIndex < wireCount; wireIndex++) {
const WireInfo &wireInfo = tiles.getWireInfo(tileTypeIndex, wireIndex);
auto wire_name = wireInfo.getName();
if (boost::regex_match(wire_name, what, re_124)) {
if (std::regex_match(wire_name, what, re_124)) {
switch (what.str(2)[0]) {
case '1':
tile_delays[wireIndex] = 150;
@ -188,7 +189,7 @@ TorcInfo::TorcInfo(BaseCtx *ctx, const std::string &inDeviceName, const std::str
default:
throw;
}
} else if (boost::regex_match(wire_name, what, re_L)) {
} else if (std::regex_match(wire_name, what, re_L)) {
std::string l(what[2]);
if (l == "H")
tile_delays[wireIndex] = 360;
@ -198,12 +199,12 @@ TorcInfo::TorcInfo(BaseCtx *ctx, const std::string &inDeviceName, const std::str
tile_delays[wireIndex] = 350;
else
throw;
} else if (boost::regex_match(wire_name, what, re_BYP)) {
} else if (std::regex_match(wire_name, what, re_BYP)) {
tile_delays[wireIndex] = 190;
} else if (boost::regex_match(wire_name, what, re_BYP_B)) {
} else if (boost::regex_match(wire_name, what, re_FAN)) {
} else if (std::regex_match(wire_name, what, re_BYP_B)) {
} else if (std::regex_match(wire_name, what, re_FAN)) {
tile_delays[wireIndex] = 190;
} else if (boost::regex_match(wire_name, what, re_CLB_I1_6)) {
} else if (std::regex_match(wire_name, what, re_CLB_I1_6)) {
switch (what.str(2)[0]) {
case '1':
tile_delays[wireIndex] = 280;
@ -297,9 +298,9 @@ TorcInfo::TorcInfo(BaseCtx *ctx, const std::string &inDeviceName, const std::str
// Disable BUFG I0 -> O routethrough
if (clk_tile) {
ewi.set(a.getSourceTilewire());
if (boost::regex_match(ewi.mWireName, bufg_i)) {
if (std::regex_match(ewi.mWireName, bufg_i)) {
ewi.set(a.getSinkTilewire());
if (boost::regex_match(ewi.mWireName, bufg_o))
if (std::regex_match(ewi.mWireName, bufg_o))
continue;
}
}
@ -307,7 +308,7 @@ TorcInfo::TorcInfo(BaseCtx *ctx, const std::string &inDeviceName, const std::str
// Disable entering HROW from INT_[LR].CLK[01]
if (boost::starts_with(tileTypeName, "CLK_HROW")) {
ewi.set(a.getSourceTilewire());
if (boost::regex_match(ewi.mWireName, hrow))
if (std::regex_match(ewi.mWireName, hrow))
continue;
}

7
xc7/attosoc.pcf
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@ -2,8 +2,7 @@ COMP "led[0]" LOCATE = SITE "M14" LEVEL 1;
COMP "led[1]" LOCATE = SITE "M15" LEVEL 1;
COMP "led[2]" LOCATE = SITE "G14" LEVEL 1;
COMP "led[3]" LOCATE = SITE "D18" LEVEL 1;
COMP "clk" LOCATE = SITE "K17" LEVEL 1;
COMP "pll.mmcm_adv_inst" LOCATE = SITE "MMCME2_ADV_X1Y2" LEVEL 1;
COMP "clki" LOCATE = SITE "K17" LEVEL 1;
NET "pll.clkin1" PERIOD = 8 nS ;
#PIN "clk_pin" = BEL "clk.PAD" PINNAME PAD;
#PIN "clk_pin" CLOCK_DEDICATED_ROUTE = FALSE;
PIN "clki_pin" = BEL "clki.PAD" PINNAME PAD;
PIN "clki_pin" CLOCK_DEDICATED_ROUTE = FALSE;

15
xc7/attosoc.sh
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@ -1,12 +1,13 @@
#!/bin/bash
#set -ex
#rm -f picorv32.v
#wget https://raw.githubusercontent.com/cliffordwolf/picorv32/master/picorv32.v
set -ex
rm -f picorv32.v attosoc.v
wget https://raw.githubusercontent.com/cliffordwolf/picorv32/master/picorv32.v
wget https://raw.githubusercontent.com/SymbiFlow/prjtrellis/master/examples/picorv32_versa5g/attosoc.v
ln -sf firmware_slow.hex firmware.hex
yosys attosoc.ys
../nextpnr-xc7 --json attosoc.json --xdl attosoc.xdl --pcf attosoc.pcf --freq 150 |& tee attosoc.log
set +e
../nextpnr-xc7 --json attosoc.json --xdl attosoc.xdl --pcf attosoc.pcf --freq 125
set -e
xdl -xdl2ncd attosoc.xdl
bitgen -w attosoc.ncd -g UnconstrainedPins:Allow
trce attosoc.ncd -v 10
netgen -sim -ofmt vhdl attosoc.ncd -w attosoc_pnr.vhd
ghdl -c -fexplicit --no-vital-checks --ieee=synopsys -Pxilinx-ise attosoc_tb.vhd attosoc_pnr.vhd -r testbench

127
xc7/attosoc.v
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@ -1,127 +0,0 @@
/*
* ECP5 PicoRV32 demo
*
* Copyright (C) 2017 Clifford Wolf <clifford@clifford.at>
* Copyright (C) 2018 David Shah <dave@ds0.me>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
`ifdef PICORV32_V
`error "attosoc.v must be read before picorv32.v!"
`endif
`define PICORV32_REGS picosoc_regs
module attosoc (
input clk,
output reg [7:0] led
);
reg [5:0] reset_cnt = 0;
wire resetn = &reset_cnt;
always @(posedge clk) begin
reset_cnt <= reset_cnt + !resetn;
end
parameter integer MEM_WORDS = 256;
parameter [31:0] STACKADDR = (4*MEM_WORDS); // end of memory
parameter [31:0] PROGADDR_RESET = 32'h 0000_0000; // ROM at 0x0
parameter integer ROM_BYTES = 256;
reg [7:0] rom [0:ROM_BYTES-1];
wire [31:0] rom_rdata = {rom[mem_addr+3], rom[mem_addr+2], rom[mem_addr+1], rom[mem_addr+0]};
initial $readmemh("firmware.hex", rom);
wire mem_valid;
wire mem_instr;
wire mem_ready;
wire [31:0] mem_addr;
wire [31:0] mem_wdata;
wire [3:0] mem_wstrb;
wire [31:0] mem_rdata;
wire rom_ready = mem_valid && mem_addr[31:24] == 8'h00;
wire iomem_valid;
wire iomem_ready;
wire [31:0] iomem_addr;
wire [31:0] iomem_wdata;
wire [3:0] iomem_wstrb;
wire [31:0] iomem_rdata;
assign iomem_valid = mem_valid && (mem_addr[31:24] > 8'h 01);
assign iomem_ready = 1'b1;
assign iomem_wstrb = mem_wstrb;
assign iomem_addr = mem_addr;
assign iomem_wdata = mem_wdata;
wire [31:0] spimemio_cfgreg_do;
always @(posedge clk)
if (iomem_valid && iomem_wstrb[0])
led <= iomem_wdata[7:0];
assign mem_ready = (iomem_valid && iomem_ready) || rom_ready;
assign mem_rdata = rom_rdata;
picorv32 #(
.STACKADDR(STACKADDR),
.PROGADDR_RESET(PROGADDR_RESET),
.PROGADDR_IRQ(32'h 0000_0000),
.BARREL_SHIFTER(0),
.COMPRESSED_ISA(0),
.ENABLE_MUL(0),
.ENABLE_DIV(0),
.ENABLE_IRQ(0),
.ENABLE_IRQ_QREGS(0)
) cpu (
.clk (clk ),
.resetn (resetn ),
.mem_valid (mem_valid ),
.mem_instr (mem_instr ),
.mem_ready (mem_ready ),
.mem_addr (mem_addr ),
.mem_wdata (mem_wdata ),
.mem_wstrb (mem_wstrb ),
.mem_rdata (mem_rdata )
);
endmodule
// Implementation note:
// Replace the following two modules with wrappers for your SRAM cells.
module picosoc_regs (
input clk, wen,
input [5:0] waddr,
input [5:0] raddr1,
input [5:0] raddr2,
input [31:0] wdata,
output [31:0] rdata1,
output [31:0] rdata2
);
reg [31:0] regs [0:31];
always @(posedge clk)
if (wen) regs[waddr[4:0]] <= wdata;
assign rdata1 = regs[raddr1[4:0]];
assign rdata2 = regs[raddr2[4:0]];
endmodule

1
xc7/attosoc.ys
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@ -1,7 +1,6 @@
read_verilog attosoc_top.v
read_verilog attosoc.v
read_verilog picorv32.v
read_verilog 125MHz_to_60MHz.v
#synth_xilinx -top picorv32

16
xc7/attosoc_sim.sh Executable file
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@ -0,0 +1,16 @@
#!/bin/bash
set -ex
rm -f picorv32.v attosoc.v
wget https://raw.githubusercontent.com/cliffordwolf/picorv32/master/picorv32.v
wget https://raw.githubusercontent.com/SymbiFlow/prjtrellis/master/examples/picorv32_versa5g/attosoc.v
ln -sf firmware_fast.hex firmware.hex
yosys attosoc.ys
set +e
../nextpnr-xc7 --json attosoc.json --xdl attosoc.xdl --pcf attosoc.pcf --freq 125
set -e
xdl -xdl2ncd attosoc.xdl
#bitgen -w attosoc.ncd -g UnconstrainedPins:Allow
trce attosoc.ncd -v 10
netgen -sim -ofmt vhdl attosoc.ncd -w attosoc_pnr.vhd
ghdl -c -fexplicit --no-vital-checks --ieee=synopsys -Pxilinx-ise attosoc_tb.vhd attosoc_pnr.vhd -r testbench

2
xc7/attosoc_tb.vhd
View File

@ -14,7 +14,7 @@ begin
wait for 4 ns;
end process;
uut: entity work.name port map(clk_PAD_PAD => clk, led_0_OUTBUF_OUT => led(0), led_1_OUTBUF_OUT => led(1), led_2_OUTBUF_OUT => led(2), led_3_OUTBUF_OUT => led(3));
uut: entity work.name port map(clki_PAD_PAD => clk, led_0_OUTBUF_OUT => led(0), led_1_OUTBUF_OUT => led(1), led_2_OUTBUF_OUT => led(2), led_3_OUTBUF_OUT => led(3));
process
begin

19
xc7/attosoc_top.v
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@ -1,15 +1,24 @@
module top (
input clk,
input clki,
output [3:0] led
);
(* keep *)
wire led_unused;
wire gclk;
clk_wiz_v3_6 pll(.CLK_IN1(clk), .CLK_OUT1(gclk));
//assign gclk = clk;
attosoc soc(.clk(gclk), .led({led_unused, led}));
wire clk;
BUFGCTRL clk_gb (
.I0(clki),
.CE0(1'b1),
.CE1(1'b0),
.S0(1'b1),
.S1(1'b0),
.IGNORE0(1'b0),
.IGNORE1(1'b0),
.O(clk)
);
attosoc soc(.clk(clk), .led({led_unused, led}));
endmodule

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xc7/benchmark/.gitignore vendored
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hx8kdemo.log
hx8kdemo.blif
hx8kdemo.json
hx8kdemo_[an][0-9].asc
hx8kdemo_[an][0-9].log
report_[an][0-9].txt

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xc7/benchmark/hx8kdemo.pcf
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# Pinout for the iCE40-HX8K Breakout Board
set_io clk J3
set_io flash_csb R12
set_io flash_clk R11
set_io flash_io0 P12
set_io flash_io1 P11
# for QSPI mode the flash chip on the iCE40-HX8K Breakout Board
# must be replaced with one that supports QSPI and the IO2 and IO3
# pins must be soldered to T9 and P8 (center on J3)
set_io flash_io2 T9
set_io flash_io3 P8
set_io ser_tx B12
set_io ser_rx B10
# left on J3
set_io debug_ser_tx T1
set_io debug_ser_rx R3
# right on J3
set_io debug_flash_csb T15
set_io debug_flash_clk R16
set_io debug_flash_io0 N12
set_io debug_flash_io1 P13
set_io debug_flash_io2 T13
set_io debug_flash_io3 T14
set_io leds[7] B5 # D9
set_io leds[6] B4 # D8
set_io leds[5] A2 # D7
set_io leds[4] A1 # D6
set_io leds[3] C5 # D5
set_io leds[2] C4 # D4
set_io leds[1] B3 # D3
set_io leds[0] C3 # D2

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xc7/benchmark/hx8kdemo.v
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/*
* PicoSoC - A simple example SoC using PicoRV32
*
* Copyright (C) 2017 Clifford Wolf <clifford@clifford.at>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
module hx8kdemo (
input clk,
output ser_tx,
input ser_rx,
output [7:0] leds,
output flash_csb,
output flash_clk,
inout flash_io0,
inout flash_io1,
inout flash_io2,
inout flash_io3,
output debug_ser_tx,
output debug_ser_rx,
output debug_flash_csb,
output debug_flash_clk,
output debug_flash_io0,
output debug_flash_io1,
output debug_flash_io2,
output debug_flash_io3
);
reg [5:0] reset_cnt = 0;
wire resetn = &reset_cnt;
always @(posedge clk) begin
reset_cnt <= reset_cnt + !resetn;
end
wire flash_io0_oe, flash_io0_do, flash_io0_di;
wire flash_io1_oe, flash_io1_do, flash_io1_di;
wire flash_io2_oe, flash_io2_do, flash_io2_di;
wire flash_io3_oe, flash_io3_do, flash_io3_di;
SB_IO #(
.PIN_TYPE(6'b 1010_01),
.PULLUP(1'b 0)
) flash_io_buf [3:0] (
.PACKAGE_PIN({flash_io3, flash_io2, flash_io1, flash_io0}),
.OUTPUT_ENABLE({flash_io3_oe, flash_io2_oe, flash_io1_oe, flash_io0_oe}),
.D_OUT_0({flash_io3_do, flash_io2_do, flash_io1_do, flash_io0_do}),
.D_IN_0({flash_io3_di, flash_io2_di, flash_io1_di, flash_io0_di})
);
wire iomem_valid;
reg iomem_ready;
wire [3:0] iomem_wstrb;
wire [31:0] iomem_addr;
wire [31:0] iomem_wdata;
reg [31:0] iomem_rdata;
reg [31:0] gpio;
assign leds = gpio;
always @(posedge clk) begin
if (!resetn) begin
gpio <= 0;
end else begin
iomem_ready <= 0;
if (iomem_valid && !iomem_ready && iomem_addr[31:24] == 8'h 03) begin
iomem_ready <= 1;
iomem_rdata <= gpio;
if (iomem_wstrb[0]) gpio[ 7: 0] <= iomem_wdata[ 7: 0];
if (iomem_wstrb[1]) gpio[15: 8] <= iomem_wdata[15: 8];
if (iomem_wstrb[2]) gpio[23:16] <= iomem_wdata[23:16];
if (iomem_wstrb[3]) gpio[31:24] <= iomem_wdata[31:24];
end
end
end
picosoc soc (
.clk (clk ),
.resetn (resetn ),
.ser_tx (ser_tx ),
.ser_rx (ser_rx ),
.flash_csb (flash_csb ),
.flash_clk (flash_clk ),
.flash_io0_oe (flash_io0_oe),
.flash_io1_oe (flash_io1_oe),
.flash_io2_oe (flash_io2_oe),
.flash_io3_oe (flash_io3_oe),
.flash_io0_do (flash_io0_do),
.flash_io1_do (flash_io1_do),
.flash_io2_do (flash_io2_do),
.flash_io3_do (flash_io3_do),
.flash_io0_di (flash_io0_di),
.flash_io1_di (flash_io1_di),
.flash_io2_di (flash_io2_di),
.flash_io3_di (flash_io3_di),
.irq_5 (1'b0 ),
.irq_6 (1'b0 ),
.irq_7 (1'b0 ),
.iomem_valid (iomem_valid ),
.iomem_ready (iomem_ready ),
.iomem_wstrb (iomem_wstrb ),
.iomem_addr (iomem_addr ),
.iomem_wdata (iomem_wdata ),
.iomem_rdata (iomem_rdata )
);
assign debug_ser_tx = ser_tx;
assign debug_ser_rx = ser_rx;
assign debug_flash_csb = flash_csb;
assign debug_flash_clk = flash_clk;
assign debug_flash_io0 = flash_io0_di;
assign debug_flash_io1 = flash_io1_di;
assign debug_flash_io2 = flash_io2_di;
assign debug_flash_io3 = flash_io3_di;
endmodule

2977
xc7/benchmark/picorv32.v
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xc7/benchmark/picosoc.v
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/*
* PicoSoC - A simple example SoC using PicoRV32
*
* Copyright (C) 2017 Clifford Wolf <clifford@clifford.at>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
`ifndef PICORV32_REGS
`ifdef PICORV32_V
`error "picosoc.v must be read before picorv32.v!"
`endif
`define PICORV32_REGS picosoc_regs
`endif
module picosoc (
input clk,
input resetn,
output iomem_valid,
input iomem_ready,
output [ 3:0] iomem_wstrb,
output [31:0] iomem_addr,
output [31:0] iomem_wdata,
input [31:0] iomem_rdata,
input irq_5,
input irq_6,
input irq_7,
output ser_tx,
input ser_rx,
output flash_csb,
output flash_clk,
output flash_io0_oe,
output flash_io1_oe,
output flash_io2_oe,
output flash_io3_oe,
output flash_io0_do,
output flash_io1_do,
output flash_io2_do,
output flash_io3_do,
input flash_io0_di,
input flash_io1_di,
input flash_io2_di,
input flash_io3_di
);
parameter integer MEM_WORDS = 256;
parameter [31:0] STACKADDR = (4*MEM_WORDS); // end of memory
parameter [31:0] PROGADDR_RESET = 32'h 0010_0000; // 1 MB into flash
reg [31:0] irq;
wire irq_stall = 0;
wire irq_uart = 0;
always @* begin
irq = 0;
irq[3] = irq_stall;
irq[4] = irq_uart;
irq[5] = irq_5;
irq[6] = irq_6;
irq[7] = irq_7;
end
wire mem_valid;
wire mem_instr;
wire mem_ready;
wire [31:0] mem_addr;
wire [31:0] mem_wdata;
wire [3:0] mem_wstrb;
wire [31:0] mem_rdata;
wire spimem_ready;
wire [31:0] spimem_rdata;
reg ram_ready;
wire [31:0] ram_rdata;
assign iomem_valid = mem_valid && (mem_addr[31:24] > 8'h 01);
assign iomem_wstrb = mem_wstrb;
assign iomem_addr = mem_addr;
assign iomem_wdata = mem_wdata;
wire spimemio_cfgreg_sel = mem_valid && (mem_addr == 32'h 0200_0000);
wire [31:0] spimemio_cfgreg_do;
wire simpleuart_reg_div_sel = mem_valid && (mem_addr == 32'h 0200_0004);
wire [31:0] simpleuart_reg_div_do;
wire simpleuart_reg_dat_sel = mem_valid && (mem_addr == 32'h 0200_0008);
wire [31:0] simpleuart_reg_dat_do;
wire simpleuart_reg_dat_wait;
assign mem_ready = (iomem_valid && iomem_ready) || spimem_ready || ram_ready || spimemio_cfgreg_sel ||
simpleuart_reg_div_sel || (simpleuart_reg_dat_sel && !simpleuart_reg_dat_wait);
assign mem_rdata = (iomem_valid && iomem_ready) ? iomem_rdata : spimem_ready ? spimem_rdata : ram_ready ? ram_rdata :
spimemio_cfgreg_sel ? spimemio_cfgreg_do : simpleuart_reg_div_sel ? simpleuart_reg_div_do :
simpleuart_reg_dat_sel ? simpleuart_reg_dat_do : 32'h 0000_0000;
picorv32 #(
.STACKADDR(STACKADDR),
.PROGADDR_RESET(PROGADDR_RESET),
.PROGADDR_IRQ(32'h 0000_0000),
.BARREL_SHIFTER(1),
.COMPRESSED_ISA(1),
.ENABLE_MUL(1),
.ENABLE_DIV(1),
.ENABLE_IRQ(1),
.ENABLE_IRQ_QREGS(0)
) cpu (
.clk (clk ),
.resetn (resetn ),
.mem_valid (mem_valid ),
.mem_instr (mem_instr ),
.mem_ready (mem_ready ),
.mem_addr (mem_addr ),
.mem_wdata (mem_wdata ),
.mem_wstrb (mem_wstrb ),
.mem_rdata (mem_rdata ),
.irq (irq )
);
spimemio spimemio (
.clk (clk),
.resetn (resetn),
.valid (mem_valid && mem_addr >= 4*MEM_WORDS && mem_addr < 32'h 0200_0000),
.ready (spimem_ready),
.addr (mem_addr[23:0]),
.rdata (spimem_rdata),
.flash_csb (flash_csb ),
.flash_clk (flash_clk ),
.flash_io0_oe (flash_io0_oe),
.flash_io1_oe (flash_io1_oe),
.flash_io2_oe (flash_io2_oe),
.flash_io3_oe (flash_io3_oe),
.flash_io0_do (flash_io0_do),
.flash_io1_do (flash_io1_do),
.flash_io2_do (flash_io2_do),
.flash_io3_do (flash_io3_do),
.flash_io0_di (flash_io0_di),
.flash_io1_di (flash_io1_di),
.flash_io2_di (flash_io2_di),
.flash_io3_di (flash_io3_di),
.cfgreg_we(spimemio_cfgreg_sel ? mem_wstrb : 4'b 0000),
.cfgreg_di(mem_wdata),
.cfgreg_do(spimemio_cfgreg_do)
);
simpleuart simpleuart (
.clk (clk ),
.resetn (resetn ),
.ser_tx (ser_tx ),
.ser_rx (ser_rx ),
.reg_div_we (simpleuart_reg_div_sel ? mem_wstrb : 4'b 0000),
.reg_div_di (mem_wdata),
.reg_div_do (simpleuart_reg_div_do),
.reg_dat_we (simpleuart_reg_dat_sel ? mem_wstrb[0] : 1'b 0),
.reg_dat_re (simpleuart_reg_dat_sel && !mem_wstrb),
.reg_dat_di (mem_wdata),
.reg_dat_do (simpleuart_reg_dat_do),
.reg_dat_wait(simpleuart_reg_dat_wait)
);
always @(posedge clk)
ram_ready <= mem_valid && !mem_ready && mem_addr < 4*MEM_WORDS;
picosoc_mem #(.WORDS(MEM_WORDS)) memory (
.clk(clk),
.wen((mem_valid && !mem_ready && mem_addr < 4*MEM_WORDS) ? mem_wstrb : 4'b0),
.addr(mem_addr[23:2]),
.wdata(mem_wdata),
.rdata(ram_rdata)
);
endmodule
// Implementation note:
// Replace the following two modules with wrappers for your SRAM cells.
module picosoc_regs (
input clk, wen,
input [5:0] waddr,
input [5:0] raddr1,
input [5:0] raddr2,
input [31:0] wdata,
output [31:0] rdata1,
output [31:0] rdata2
);
reg [31:0] regs [0:31];
always @(posedge clk)
if (wen) regs[waddr[4:0]] <= wdata;
assign rdata1 = regs[raddr1[4:0]];
assign rdata2 = regs[raddr2[4:0]];
endmodule
module picosoc_mem #(
parameter integer WORDS = 256
) (
input clk,
input [3:0] wen,
input [21:0] addr,
input [31:0] wdata,
output reg [31:0] rdata
);
reg [31:0] mem [0:WORDS-1];
always @(posedge clk) begin
rdata <= mem[addr];
if (wen[0]) mem[addr][ 7: 0] <= wdata[ 7: 0];
if (wen[1]) mem[addr][15: 8] <= wdata[15: 8];
if (wen[2]) mem[addr][23:16] <= wdata[23:16];
if (wen[3]) mem[addr][31:24] <= wdata[31:24];
end
endmodule

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xc7/benchmark/report.ipynb
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{
"cells": [
{
"cell_type": "code",
"execution_count": null,
"metadata": {
"collapsed": false
},
"outputs": [],
"source": [
"%matplotlib inline\n",
"import numpy as np\n",
"import matplotlib.pyplot as plt\n",
"import subprocess, re\n",
"\n",
"gitrev = subprocess.getoutput(\"git rev-parse --short HEAD\")\n",
"\n",
"data_a = np.zeros((10, 2))\n",
"data_n = np.zeros((10, 2))\n",
"\n",
"for i in range(10):\n",
" try:\n",
" with open(\"report_a%d.txt\" % i, \"r\") as f:\n",
" for line in f:\n",
" if line.startswith(\"Total path delay:\"):\n",
" data_a[i, 0] = float(line.split()[3])\n",
" except:\n",
" data_a[i, 0] = 1.0\n",
" \n",
" try:\n",
" with open(\"report_n%d.txt\" % i, \"r\") as f:\n",
" for line in f:\n",
" if line.startswith(\"Total path delay:\"):\n",
" data_n[i, 0] = float(line.split()[3])\n",
" except:\n",
" data_n[i, 0] = 1.0\n",
" \n",
" with open(\"hx8kdemo_a%d.log\" % i, \"r\") as f:\n",
" for line in f:\n",
" match = re.match(r\"real\\s+(\\d+)m(\\d+)\", line)\n",
" if match:\n",
" data_a[i, 1] = float(match.group(1)) + float(match.group(2))/60\n",
" \n",
" with open(\"hx8kdemo_n%d.log\" % i, \"r\") as f:\n",
" for line in f:\n",
" match = re.match(r\"real\\s+(\\d+)m(\\d+)\", line)\n",
" if match:\n",
" data_n[i, 1] = float(match.group(1)) + float(match.group(2))/60\n",
"\n",
"plt.figure(figsize=(9,3))\n",
"plt.title(\"nextpnr -- ice40/benchmark/ -- %s\" % gitrev)\n",
"plt.bar(np.arange(10), data_a[:, 0], color='blue')\n",
"plt.bar(15+np.arange(10), data_n[:, 0], color='red')\n",
"plt.ylabel('Longest path (ns)')\n",
"plt.xticks([5, 20], [\"arachne-pnr\", \"nextpnr\"])\n",
"plt.xlim(-2, 27)\n",
"plt.show()\n",
"\n",
"plt.figure(figsize=(9,3))\n",
"plt.title(\"nextpnr -- ice40/benchmark/ -- %s\" % gitrev)\n",
"plt.bar(np.arange(10), data_a[:, 1], color='blue')\n",
"plt.bar(15+np.arange(10), data_n[:, 1], color='red')\n",
"plt.ylabel('Runtime (minutes)')\n",
"plt.xticks([5, 20], [\"arachne-pnr\", \"nextpnr\"])\n",
"plt.xlim(-2, 27)\n",
"plt.show()"
]
}
],
"metadata": {
"kernelspec": {
"display_name": "Python 3",
"language": "python",
"name": "python3"
},
"language_info": {
"codemirror_mode": {
"name": "ipython",
"version": 3
},
"file_extension": ".py",
"mimetype": "text/x-python",
"name": "python",
"nbconvert_exporter": "python",
"pygments_lexer": "ipython3",
"version": "3.5.2"
}
},
"nbformat": 4,
"nbformat_minor": 1
}

137
xc7/benchmark/simpleuart.v
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/*
* PicoSoC - A simple example SoC using PicoRV32
*
* Copyright (C) 2017 Clifford Wolf <clifford@clifford.at>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
module simpleuart (
input clk,
input resetn,
output ser_tx,
input ser_rx,
input [3:0] reg_div_we,
input [31:0] reg_div_di,
output [31:0] reg_div_do,
input reg_dat_we,
input reg_dat_re,
input [31:0] reg_dat_di,
output [31:0] reg_dat_do,
output reg_dat_wait
);
reg [31:0] cfg_divider;
reg [3:0] recv_state;
reg [31:0] recv_divcnt;
reg [7:0] recv_pattern;
reg [7:0] recv_buf_data;
reg recv_buf_valid;
reg [9:0] send_pattern;
reg [3:0] send_bitcnt;
reg [31:0] send_divcnt;
reg send_dummy;
assign reg_div_do = cfg_divider;
assign reg_dat_wait = reg_dat_we && (send_bitcnt || send_dummy);
assign reg_dat_do = recv_buf_valid ? recv_buf_data : ~0;
always @(posedge clk) begin
if (!resetn) begin
cfg_divider <= 1;
end else begin
if (reg_div_we[0]) cfg_divider[ 7: 0] <= reg_div_di[ 7: 0];
if (reg_div_we[1]) cfg_divider[15: 8] <= reg_div_di[15: 8];
if (reg_div_we[2]) cfg_divider[23:16] <= reg_div_di[23:16];
if (reg_div_we[3]) cfg_divider[31:24] <= reg_div_di[31:24];
end
end
always @(posedge clk) begin
if (!resetn) begin
recv_state <= 0;
recv_divcnt <= 0;
recv_pattern <= 0;
recv_buf_data <= 0;
recv_buf_valid <= 0;
end else begin
recv_divcnt <= recv_divcnt + 1;
if (reg_dat_re)
recv_buf_valid <= 0;
case (recv_state)
0: begin
if (!ser_rx)
recv_state <= 1;
recv_divcnt <= 0;
end
1: begin
if (2*recv_divcnt > cfg_divider) begin
recv_state <= 2;
recv_divcnt <= 0;
end
end
10: begin
if (recv_divcnt > cfg_divider) begin
recv_buf_data <= recv_pattern;
recv_buf_valid <= 1;
recv_state <= 0;
end
end
default: begin
if (recv_divcnt > cfg_divider) begin
recv_pattern <= {ser_rx, recv_pattern[7:1]};
recv_state <= recv_state + 1;
recv_divcnt <= 0;
end
end
endcase
end
end
assign ser_tx = send_pattern[0];
always @(posedge clk) begin
if (reg_div_we)
send_dummy <= 1;
send_divcnt <= send_divcnt + 1;
if (!resetn) begin
send_pattern <= ~0;
send_bitcnt <= 0;
send_divcnt <= 0;
send_dummy <= 1;
end else begin
if (send_dummy && !send_bitcnt) begin
send_pattern <= ~0;
send_bitcnt <= 15;
send_divcnt <= 0;
send_dummy <= 0;
end else
if (reg_dat_we && !send_bitcnt) begin
send_pattern <= {1'b1, reg_dat_di[7:0], 1'b0};
send_bitcnt <= 10;
send_divcnt <= 0;
end else
if (send_divcnt > cfg_divider && send_bitcnt) begin
send_pattern <= {1'b1, send_pattern[9:1]};
send_bitcnt <= send_bitcnt - 1;
send_divcnt <= 0;
end
end
end
endmodule

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xc7/benchmark/spimemio.v
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/*
* PicoSoC - A simple example SoC using PicoRV32
*
* Copyright (C) 2017 Clifford Wolf <clifford@clifford.at>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
module spimemio (
input clk, resetn,
input valid,
output ready,
input [23:0] addr,
output reg [31:0] rdata,
output flash_csb,
output flash_clk,
output flash_io0_oe,
output flash_io1_oe,
output flash_io2_oe,
output flash_io3_oe,
output flash_io0_do,
output flash_io1_do,
output flash_io2_do,
output flash_io3_do,
input flash_io0_di,
input flash_io1_di,
input flash_io2_di,
input flash_io3_di,
input [3:0] cfgreg_we,
input [31:0] cfgreg_di,
output [31:0] cfgreg_do
);
reg xfer_resetn;
reg din_valid;
wire din_ready;
reg [7:0] din_data;
reg [3:0] din_tag;
reg din_cont;
reg din_qspi;
reg din_ddr;
reg din_rd;
wire dout_valid;
wire [7:0] dout_data;
wire [3:0] dout_tag;
reg [23:0] buffer;
reg [23:0] rd_addr;
reg rd_valid;
reg rd_wait;
reg rd_inc;
assign ready = valid && (addr == rd_addr) && rd_valid;
wire jump = valid && !ready && (addr != rd_addr+4) && rd_valid;
reg softreset;
reg config_en; // cfgreg[31]
reg config_ddr; // cfgreg[22]
reg config_qspi; // cfgreg[21]
reg config_cont; // cfgreg[20]
reg [3:0] config_dummy; // cfgreg[19:16]
reg [3:0] config_oe; // cfgreg[11:8]
reg config_csb; // cfgreg[5]
reg config_clk; // cfgref[4]
reg [3:0] config_do; // cfgreg[3:0]
assign cfgreg_do[31] = config_en;
assign cfgreg_do[30:23] = 0;
assign cfgreg_do[22] = config_ddr;
assign cfgreg_do[21] = config_qspi;
assign cfgreg_do[20] = config_cont;
assign cfgreg_do[19:16] = config_dummy;
assign cfgreg_do[15:12] = 0;
assign cfgreg_do[11:8] = {flash_io3_oe, flash_io2_oe, flash_io1_oe, flash_io0_oe};
assign cfgreg_do[7:6] = 0;
assign cfgreg_do[5] = flash_csb;
assign cfgreg_do[4] = flash_clk;
assign cfgreg_do[3:0] = {flash_io3_di, flash_io2_di, flash_io1_di, flash_io0_di};
always @(posedge clk) begin
softreset <= !config_en || cfgreg_we;
if (!resetn) begin
softreset <= 1;
config_en <= 1;
config_csb <= 0;
config_clk <= 0;
config_oe <= 0;
config_do <= 0;
config_ddr <= 0;
config_qspi <= 0;
config_cont <= 0;
config_dummy <= 8;
end else begin
if (cfgreg_we[0]) begin
config_csb <= cfgreg_di[5];
config_clk <= cfgreg_di[4];
config_do <= cfgreg_di[3:0];
end
if (cfgreg_we[1]) begin
config_oe <= cfgreg_di[11:8];
end
if (cfgreg_we[2]) begin
config_ddr <= cfgreg_di[22];
config_qspi <= cfgreg_di[21];
config_cont <= cfgreg_di[20];
config_dummy <= cfgreg_di[19:16];
end
if (cfgreg_we[3]) begin
config_en <= cfgreg_di[31];
end
end
end
wire xfer_csb;
wire xfer_clk;
wire xfer_io0_oe;
wire xfer_io1_oe;
wire xfer_io2_oe;
wire xfer_io3_oe;
wire xfer_io0_do;
wire xfer_io1_do;
wire xfer_io2_do;
wire xfer_io3_do;
reg xfer_io0_90;
reg xfer_io1_90;
reg xfer_io2_90;
reg xfer_io3_90;
always @(negedge clk) begin
xfer_io0_90 <= xfer_io0_do;
xfer_io1_90 <= xfer_io1_do;
xfer_io2_90 <= xfer_io2_do;
xfer_io3_90 <= xfer_io3_do;
end
assign flash_csb = config_en ? xfer_csb : config_csb;
assign flash_clk = config_en ? xfer_clk : config_clk;
assign flash_io0_oe = config_en ? xfer_io0_oe : config_oe[0];
assign flash_io1_oe = config_en ? xfer_io1_oe : config_oe[1];
assign flash_io2_oe = config_en ? xfer_io2_oe : config_oe[2];
assign flash_io3_oe = config_en ? xfer_io3_oe : config_oe[3];
assign flash_io0_do = config_en ? (config_ddr ? xfer_io0_90 : xfer_io0_do) : config_do[0];
assign flash_io1_do = config_en ? (config_ddr ? xfer_io1_90 : xfer_io1_do) : config_do[1];
assign flash_io2_do = config_en ? (config_ddr ? xfer_io2_90 : xfer_io2_do) : config_do[2];
assign flash_io3_do = config_en ? (config_ddr ? xfer_io3_90 : xfer_io3_do) : config_do[3];
wire xfer_dspi = din_ddr && !din_qspi;
wire xfer_ddr = din_ddr && din_qspi;
spimemio_xfer xfer (
.clk (clk ),
.resetn (xfer_resetn ),
.din_valid (din_valid ),
.din_ready (din_ready ),
.din_data (din_data ),
.din_tag (din_tag ),
.din_cont (din_cont ),
.din_dspi (xfer_dspi ),
.din_qspi (din_qspi ),
.din_ddr (xfer_ddr ),
.din_rd (din_rd ),
.dout_valid (dout_valid ),
.dout_data (dout_data ),
.dout_tag (dout_tag ),
.flash_csb (xfer_csb ),
.flash_clk (xfer_clk ),
.flash_io0_oe (xfer_io0_oe ),
.flash_io1_oe (xfer_io1_oe ),
.flash_io2_oe (xfer_io2_oe ),
.flash_io3_oe (xfer_io3_oe ),
.flash_io0_do (xfer_io0_do ),
.flash_io1_do (xfer_io1_do ),
.flash_io2_do (xfer_io2_do ),
.flash_io3_do (xfer_io3_do ),
.flash_io0_di (flash_io0_di),
.flash_io1_di (flash_io1_di),
.flash_io2_di (flash_io2_di),
.flash_io3_di (flash_io3_di)
);
reg [3:0] state;
always @(posedge clk) begin
xfer_resetn <= 1;
din_valid <= 0;
if (!resetn || softreset) begin
state <= 0;
xfer_resetn <= 0;
rd_valid <= 0;
din_tag <= 0;
din_cont <= 0;
din_qspi <= 0;
din_ddr <= 0;
din_rd <= 0;
end else begin
if (dout_valid && dout_tag == 1) buffer[ 7: 0] <= dout_data;
if (dout_valid && dout_tag == 2) buffer[15: 8] <= dout_data;
if (dout_valid && dout_tag == 3) buffer[23:16] <= dout_data;
if (dout_valid && dout_tag == 4) begin
rdata <= {dout_data, buffer};
rd_addr <= rd_inc ? rd_addr + 4 : addr;
rd_valid <= 1;
rd_wait <= rd_inc;
rd_inc <= 1;
end
if (valid)
rd_wait <= 0;
case (state)
0: begin
din_valid <= 1;
din_data <= 8'h ff;
din_tag <= 0;
if (din_ready) begin
din_valid <= 0;
state <= 1;
end
end
1: begin
if (dout_valid) begin
xfer_resetn <= 0;
state <= 2;
end
end
2: begin
din_valid <= 1;
din_data <= 8'h ab;
din_tag <= 0;
if (din_ready) begin
din_valid <= 0;
state <= 3;
end
end
3: begin
if (dout_valid) begin
xfer_resetn <= 0;
state <= 4;
end
end
4: begin
rd_inc <= 0;
din_valid <= 1;
din_tag <= 0;
case ({config_ddr, config_qspi})
2'b11: din_data <= 8'h ED;
2'b01: din_data <= 8'h EB;
2'b10: din_data <= 8'h BB;
2'b00: din_data <= 8'h 03;
endcase
if (din_ready) begin
din_valid <= 0;
state <= 5;
end
end
5: begin
if (valid && !ready) begin
din_valid <= 1;
din_tag <= 0;
din_data <= addr[23:16];
din_qspi <= config_qspi;
din_ddr <= config_ddr;
if (din_ready) begin
din_valid <= 0;
state <= 6;
end
end
end
6: begin
din_valid <= 1;
din_tag <= 0;
din_data <= addr[15:8];
if (din_ready) begin
din_valid <= 0;
state <= 7;
end
end
7: begin
din_valid <= 1;
din_tag <= 0;
din_data <= addr[7:0];
if (din_ready) begin
din_valid <= 0;
din_data <= 0;
state <= config_qspi || config_ddr ? 8 : 9;
end
end
8: begin
din_valid <= 1;
din_tag <= 0;
din_data <= config_cont ? 8'h A5 : 8'h FF;
if (din_ready) begin
din_rd <= 1;
din_data <= config_dummy;
din_valid <= 0;
state <= 9;
end
end
9: begin
din_valid <= 1;
din_tag <= 1;
if (din_ready) begin
din_valid <= 0;
state <= 10;
end
end
10: begin
din_valid <= 1;
din_data <= 8'h 00;
din_tag <= 2;
if (din_ready) begin
din_valid <= 0;
state <= 11;
end
end
11: begin
din_valid <= 1;
din_tag <= 3;
if (din_ready) begin
din_valid <= 0;
state <= 12;
end
end
12: begin
if (!rd_wait || valid) begin
din_valid <= 1;
din_tag <= 4;
if (din_ready) begin
din_valid <= 0;
state <= 9;
end
end
end
endcase
if (jump) begin
rd_inc <= 0;
rd_valid <= 0;
xfer_resetn <= 0;
if (config_cont) begin
state <= 5;
end else begin
state <= 4;
din_qspi <= 0;
din_ddr <= 0;
end
din_rd <= 0;
end
end
end
endmodule
module spimemio_xfer (
input clk, resetn,
input din_valid,
output din_ready,
input [7:0] din_data,
input [3:0] din_tag,
input din_cont,
input din_dspi,
input din_qspi,
input din_ddr,
input din_rd,
output dout_valid,
output [7:0] dout_data,
output [3:0] dout_tag,
output reg flash_csb,
output reg flash_clk,
output reg flash_io0_oe,
output reg flash_io1_oe,
output reg flash_io2_oe,
output reg flash_io3_oe,
output reg flash_io0_do,
output reg flash_io1_do,
output reg flash_io2_do,
output reg flash_io3_do,
input flash_io0_di,
input flash_io1_di,
input flash_io2_di,
input flash_io3_di
);
reg [7:0] obuffer;
reg [7:0] ibuffer;
reg [3:0] count;
reg [3:0] dummy_count;
reg xfer_cont;
reg xfer_dspi;
reg xfer_qspi;
reg xfer_ddr;
reg xfer_ddr_q;
reg xfer_rd;
reg [3:0] xfer_tag;
reg [3:0] xfer_tag_q;
reg [7:0] next_obuffer;
reg [7:0] next_ibuffer;
reg [3:0] next_count;
reg fetch;
reg next_fetch;
reg last_fetch;
always @(posedge clk) begin
xfer_ddr_q <= xfer_ddr;
xfer_tag_q <= xfer_tag;
end
assign din_ready = din_valid && resetn && next_fetch;
assign dout_valid = (xfer_ddr_q ? fetch && !last_fetch : next_fetch && !fetch) && resetn;
assign dout_data = ibuffer;
assign dout_tag = xfer_tag_q;
always @* begin
flash_io0_oe = 0;
flash_io1_oe = 0;
flash_io2_oe = 0;
flash_io3_oe = 0;
flash_io0_do = 0;
flash_io1_do = 0;
flash_io2_do = 0;
flash_io3_do = 0;
next_obuffer = obuffer;
next_ibuffer = ibuffer;
next_count = count;
next_fetch = 0;
if (dummy_count == 0) begin
casez ({xfer_ddr, xfer_qspi, xfer_dspi})
3'b 000: begin
flash_io0_oe = 1;
flash_io0_do = obuffer[7];
if (flash_clk) begin
next_obuffer = {obuffer[6:0], 1'b 0};
next_count = count - |count;
end else begin
next_ibuffer = {ibuffer[6:0], flash_io1_di};
end
next_fetch = (next_count == 0);
end
3'b 01?: begin
flash_io0_oe = !xfer_rd;
flash_io1_oe = !xfer_rd;
flash_io2_oe = !xfer_rd;
flash_io3_oe = !xfer_rd;
flash_io0_do = obuffer[4];
flash_io1_do = obuffer[5];
flash_io2_do = obuffer[6];
flash_io3_do = obuffer[7];
if (flash_clk) begin
next_obuffer = {obuffer[3:0], 4'b 0000};
next_count = count - {|count, 2'b00};
end else begin
next_ibuffer = {ibuffer[3:0], flash_io3_di, flash_io2_di, flash_io1_di, flash_io0_di};
end
next_fetch = (next_count == 0);
end
3'b 11?: begin
flash_io0_oe = !xfer_rd;
flash_io1_oe = !xfer_rd;
flash_io2_oe = !xfer_rd;
flash_io3_oe = !xfer_rd;
flash_io0_do = obuffer[4];
flash_io1_do = obuffer[5];
flash_io2_do = obuffer[6];
flash_io3_do = obuffer[7];
next_obuffer = {obuffer[3:0], 4'b 0000};
next_ibuffer = {ibuffer[3:0], flash_io3_di, flash_io2_di, flash_io1_di, flash_io0_di};
next_count = count - {|count, 2'b00};
next_fetch = (next_count == 0);
end
3'b ??1: begin
flash_io0_oe = !xfer_rd;
flash_io1_oe = !xfer_rd;
flash_io0_do = obuffer[6];
flash_io1_do = obuffer[7];
if (flash_clk) begin
next_obuffer = {obuffer[5:0], 2'b 00};
next_count = count - {|count, 1'b0};
end else begin
next_ibuffer = {ibuffer[5:0], flash_io1_di, flash_io0_di};
end
next_fetch = (next_count == 0);
end
endcase
end
end
always @(posedge clk) begin
if (!resetn) begin
fetch <= 1;
last_fetch <= 1;
flash_csb <= 1;
flash_clk <= 0;
count <= 0;
dummy_count <= 0;
xfer_tag <= 0;
xfer_cont <= 0;
xfer_dspi <= 0;
xfer_qspi <= 0;
xfer_ddr <= 0;
xfer_rd <= 0;
end else begin
fetch <= next_fetch;
last_fetch <= xfer_ddr ? fetch : 1;
if (dummy_count) begin
flash_clk <= !flash_clk && !flash_csb;
dummy_count <= dummy_count - flash_clk;
end else
if (count) begin
flash_clk <= !flash_clk && !flash_csb;
obuffer <= next_obuffer;
ibuffer <= next_ibuffer;
count <= next_count;
end
if (din_valid && din_ready) begin
flash_csb <= 0;
flash_clk <= 0;
count <= 8;
dummy_count <= din_rd ? din_data : 0;
obuffer <= din_data;
xfer_tag <= din_tag;
xfer_cont <= din_cont;
xfer_dspi <= din_dspi;
xfer_qspi <= din_qspi;
xfer_ddr <= din_ddr;
xfer_rd <= din_rd;
end
end
end
endmodule

10
xc7/blinky.sh
View File

@ -1,14 +1,6 @@
#!/bin/bash
set -ex
yosys blinky.ys
../nextpnr-xc7 --json blinky.json --pcf blinky.pcf --xdl blinky.xdl --freq 150
../nextpnr-xc7 --json blinky.json --pcf blinky.pcf --xdl blinky.xdl --freq 125
xdl -xdl2ncd blinky.xdl
bitgen -w blinky.ncd -g UnconstrainedPins:Allow
trce blinky.ncd -v 10
#netgen -ofmt verilog -w blinky.ncd blinky_chip.v -tm blinky -insert_glbl true
#iverilog -o blinky_tb blinky_chip.v blinky_tb.v -y/opt/Xilinx/14.7/ISE_DS/ISE/verilog/src/simprims/
#vvp -N ./blinky_tb
#xdl -xdl2ncd blinky.xdl -nopips blinky_map.ncd
#par -w blinky_map.ncd blinky_par.ncd blinky.pcf
#bitgen -w blinky_par.ncd -g UnconstrainedPins:Allow

7
xc7/blinky.v
View File

@ -5,8 +5,7 @@ module blinky (
output led2,
output led3
);
//`include "ps7.vh"
wire clk;
BUFGCTRL clk_gb (
.I0(clki),
.CE0(1'b1),
@ -19,7 +18,7 @@ module blinky (
);
localparam BITS = 4;
localparam LOG2DELAY = 23;
parameter LOG2DELAY = 23;
reg [BITS+LOG2DELAY-1:0] counter = 0;
reg [BITS-1:0] outcnt;
@ -29,5 +28,5 @@ module blinky (
outcnt <= counter >> LOG2DELAY;
end
assign {led0, led1, led2, led3} = outcnt /*^ (outcnt >> 1)*/;
assign {led0, led1, led2, led3} = outcnt ^ (outcnt >> 1);
endmodule

8
xc7/blinky_sim.sh Executable file
View File

@ -0,0 +1,8 @@
#!/bin/bash
set -ex
yosys blinky_sim.ys
../nextpnr-xc7 --json blinky.json --pcf blinky.pcf --xdl blinky.xdl --freq 125
xdl -xdl2ncd blinky.xdl
trce blinky.ncd -v 10
netgen -sim -ofmt vhdl blinky.ncd -w blinky_pnr.vhd
ghdl -c -fexplicit --no-vital-checks --ieee=synopsys -Pxilinx-ise blinky_tb.vhd blinky_pnr.vhd -r testbench

54
xc7/blinky_sim.ys Normal file
View File

@ -0,0 +1,54 @@
read_verilog blinky.v
chparam -set LOG2DELAY 0
#synth_xilinx -top blinky
#begin:
read_verilog -lib +/xilinx/cells_sim.v
read_verilog -lib +/xilinx/cells_xtra.v
# read_verilog -lib +/xilinx/brams_bb.v
# read_verilog -lib +/xilinx/drams_bb.v
hierarchy -check -top blinky
#flatten: (only if -flatten)
proc
flatten
#coarse:
synth -run coarse
#bram:
# memory_bram -rules +/xilinx/brams.txt
# techmap -map +/xilinx/brams_map.v
#
#dram:
# memory_bram -rules +/xilinx/drams.txt
# techmap -map +/xilinx/drams_map.v
fine:
opt -fast -full
memory_map
dffsr2dff
# dff2dffe
opt -full
techmap -map +/techmap.v #-map +/xilinx/arith_map.v
opt -fast
map_luts:
abc -luts 2:2,3,6:5 #,10,20 [-dff]
clean
map_cells:
techmap -map +/xilinx/cells_map.v
dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT
clean
check:
hierarchy -check
stat
check -noinit
#edif: (only if -edif)
# write_edif <file-name>
write_json blinky.json

25
xc7/blinky_tb.v
View File

@ -1,25 +0,0 @@
module blinky_tb;
reg clk;
always #5 clk = (clk === 1'b0);
wire led0, led1, led2, led3;
blinky uut (
.\clki.PAD.PAD (clk),
.\led0.OUTBUF.OUT (led0),
.\led1.OUTBUF.OUT (led1),
.\led2.OUTBUF.OUT (led2),
.\led3.OUTBUF.OUT (led3)
);
initial begin
// $dumpfile("blinky_tb.vcd");
// $dumpvars(0, blinky_tb);
$monitor(led0, led1, led2, led3);
//repeat (10) begin
// repeat (900000) @(posedge clk);
// $display(led0, led1, led2, led3);
//end
//$finish;
end
endmodule

25
xc7/blinky_tb.vhd Normal file
View File

@ -0,0 +1,25 @@
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity testbench is
end entity;
architecture rtl of testbench is
signal clk : STD_LOGIC;
signal led : STD_LOGIC_VECTOR(3 downto 0);
begin
process begin
clk <= '0';
wait for 4 ns;
clk <= '1';
wait for 4 ns;
end process;
uut: entity work.name port map(clki_PAD_PAD => clk, led0_OUTBUF_OUT => led(0), led1_OUTBUF_OUT => led(1), led2_OUTBUF_OUT => led(2), led3_OUTBUF_OUT => led(3));
process
begin
report std_logic'image(led(3)) & std_logic'image(led(2)) & std_logic'image(led(1)) & std_logic'image(led(0));
wait on led;
end process;
end rtl;

4
xc7/carry_tests/.gitignore vendored
View File

@ -1,4 +0,0 @@
*.vcd
*_out.v
*.out

9
xc7/carry_tests/counter.v
View File

@ -1,9 +0,0 @@
module top(input clk, cen, rst, ina, inb, output outa, outb, outc, outd);
reg [15:0] ctr = 0;
always @(posedge clk)
ctr <= ctr + 1'b1;
assign {outa, outb, outc, outd} = ctr[15:12];
endmodule

23
xc7/carry_tests/counter_tb.v
View File

@ -1,23 +0,0 @@
module counter_tb;
reg clk;
always #5 clk = (clk === 1'b0);
wire outa, outb, outc, outd;
chip uut (
.clk(clk),
.cen(1'b1),
.rst(1'b0),
.outa(outa),
.outb(outb),
.outc(outc),
.outd(outd)
);
initial begin
$dumpfile("counter_tb.vcd");
$dumpvars(0, counter_tb);
repeat (100000) @(posedge clk);
$finish;
end
endmodule

10
xc7/carry_tests/test.pcf
View File

@ -1,10 +0,0 @@
set_io clk 1
set_io cen 2
set_io rst 3
set_io ina 4
set_io inb 7
set_io outa 8
set_io outb 9
set_io outc 10
set_io outd 11

9
xc7/carry_tests/test.sh
View File

@ -1,9 +0,0 @@
#!/usr/bin/env bash
set -ex
NAME=${1%.v}
yosys -p "synth_ice40 -top top; write_json ${NAME}.json" $1
../../nextpnr-ice40 --json ${NAME}.json --pcf test.pcf --asc ${NAME}.asc --verbose
icebox_vlog -p test.pcf -L ${NAME}.asc > ${NAME}_out.v
iverilog -o ${NAME}_sim.out ${NAME}_tb.v ${NAME}_out.v
vvp ${NAME}_sim.out

24
xc7/cells.cc
View File

@ -118,40 +118,40 @@ void dff_to_lc(const Context *ctx, CellInfo *dff, CellInfo *lc, bool pass_thru_l
if (*citer == 'S') {
citer++;
if (get_net_or_empty(dff, id_S) != gnd_net) {
lc->params[id_SR] = "SRHIGH";
lc->params[ctx->id("SYNC_ATTR")] = "SYNC";
lc->params[id_SR] = "SRHIGH";
replace_port(dff, id_S, lc, id_SR);
}
}
else
disconnect_port(ctx, dff, id_S);
lc->params[ctx->id("SYNC_ATTR")] = "SYNC";
} else if (*citer == 'R') {
citer++;
if (get_net_or_empty(dff, id_R) != gnd_net) {
lc->params[id_SR] = "SRLOW";
lc->params[ctx->id("SYNC_ATTR")] = "SYNC";
lc->params[id_SR] = "SRLOW";
replace_port(dff, id_R, lc, id_SR);
}
}
else
disconnect_port(ctx, dff, id_R);
lc->params[ctx->id("SYNC_ATTR")] = "SYNC";
} else if (*citer == 'C') {
citer++;
if (get_net_or_empty(dff, id_CLR) != gnd_net) {
lc->params[id_SR] = "SRLOW";
lc->params[ctx->id("SYNC_ATTR")] = "ASYNC";
lc->params[id_SR] = "SRLOW";
replace_port(dff, id_CLR, lc, id_SR);
}
}
else
disconnect_port(ctx, dff, id_CLR);
lc->params[ctx->id("SYNC_ATTR")] = "ASYNC";
} else {
NPNR_ASSERT(*citer == 'P');
citer++;
if (get_net_or_empty(dff, id_PRE) != gnd_net) {
lc->params[id_SR] = "SRHIGH";
lc->params[ctx->id("SYNC_ATTR")] = "ASYNC";
lc->params[id_SR] = "SRHIGH";
replace_port(dff, id_PRE, lc, id_SR);
}
}
else
disconnect_port(ctx, dff, id_PRE);
lc->params[ctx->id("SYNC_ATTR")] = "ASYNC";
}
}

130
xc7/family.cmake
View File

@ -1,71 +1,73 @@
include_directories(/opt/torc/src)
#include_directories(torc/externals/zlib)
add_dependencies(nextpnr-${family} torc)
add_custom_target(torc ALL
COMMAND $(MAKE) > /dev/null 2> /dev/null
COMMENT "Building torc (may take some time...)"
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}/torc/src)
find_package(Boost REQUIRED COMPONENTS serialization iostreams ${boost_libs} ${boost_python_lib})
include_directories(torc/src)
target_link_libraries(
nextpnr-${family}
PRIVATE /opt/torc/src/torc/architecture/Arc.o
PRIVATE /opt/torc/src/torc/architecture/ArcUsage.o
PRIVATE /opt/torc/src/torc/architecture/Array.o
PRIVATE /opt/torc/src/torc/architecture/DDB.o
PRIVATE /opt/torc/src/torc/architecture/DDBConsoleStreams.o
PRIVATE /opt/torc/src/torc/architecture/DDBStreamHelper.o
PRIVATE /opt/torc/src/torc/architecture/DigestStream.o
PRIVATE /opt/torc/src/torc/architecture/ExtendedWireInfo.o
PRIVATE /opt/torc/src/torc/architecture/InstancePin.o
PRIVATE /opt/torc/src/torc/architecture/OutputStreamHelpers.o
PRIVATE /opt/torc/src/torc/architecture/Package.o
PRIVATE /opt/torc/src/torc/architecture/Pad.o
PRIVATE /opt/torc/src/torc/architecture/PrimitiveConn.o
PRIVATE /opt/torc/src/torc/architecture/PrimitiveDef.o
PRIVATE /opt/torc/src/torc/architecture/PrimitiveElement.o
PRIVATE /opt/torc/src/torc/architecture/PrimitiveElementPin.o
PRIVATE /opt/torc/src/torc/architecture/PrimitivePin.o
PRIVATE /opt/torc/src/torc/architecture/Segments.o
PRIVATE /opt/torc/src/torc/architecture/Site.o
PRIVATE /opt/torc/src/torc/architecture/Sites.o
PRIVATE /opt/torc/src/torc/architecture/Tiles.o
PRIVATE /opt/torc/src/torc/architecture/TileInfo.o
PRIVATE /opt/torc/src/torc/architecture/Tilewire.o
PRIVATE /opt/torc/src/torc/architecture/Versions.o
PRIVATE /opt/torc/src/torc/architecture/VprExporter.o
PRIVATE /opt/torc/src/torc/architecture/WireInfo.o
PRIVATE /opt/torc/src/torc/architecture/WireUsage.o
PRIVATE /opt/torc/src/torc/architecture/XdlImporter.o
PRIVATE /opt/torc/src/torc/architecture/XilinxDatabaseTypes.o
nextpnr-${family} PRIVATE
PRIVATE /opt/torc/src/torc/common/Annotated.o
PRIVATE /opt/torc/src/torc/common/DeviceDesignator.o
PRIVATE /opt/torc/src/torc/common/Devices.o
PRIVATE /opt/torc/src/torc/common/DirectoryTree.o
PRIVATE /opt/torc/src/torc/common/DottedVersion.o
PRIVATE /opt/torc/src/torc/common/NullOutputStream.o
PRIVATE boost_regex
${CMAKE_CURRENT_SOURCE_DIR}/torc/src/torc/architecture/Arc.o
${CMAKE_CURRENT_SOURCE_DIR}/torc/src/torc/architecture/ArcUsage.o
${CMAKE_CURRENT_SOURCE_DIR}/torc/src/torc/architecture/Array.o
${CMAKE_CURRENT_SOURCE_DIR}/torc/src/torc/architecture/DDB.o
${CMAKE_CURRENT_SOURCE_DIR}/torc/src/torc/architecture/DDBConsoleStreams.o
${CMAKE_CURRENT_SOURCE_DIR}/torc/src/torc/architecture/DDBStreamHelper.o
${CMAKE_CURRENT_SOURCE_DIR}/torc/src/torc/architecture/DigestStream.o
${CMAKE_CURRENT_SOURCE_DIR}/torc/src/torc/architecture/ExtendedWireInfo.o
${CMAKE_CURRENT_SOURCE_DIR}/torc/src/torc/architecture/InstancePin.o
${CMAKE_CURRENT_SOURCE_DIR}/torc/src/torc/architecture/OutputStreamHelpers.o
${CMAKE_CURRENT_SOURCE_DIR}/torc/src/torc/architecture/Package.o
${CMAKE_CURRENT_SOURCE_DIR}/torc/src/torc/architecture/Pad.o
${CMAKE_CURRENT_SOURCE_DIR}/torc/src/torc/architecture/PrimitiveConn.o
${CMAKE_CURRENT_SOURCE_DIR}/torc/src/torc/architecture/PrimitiveDef.o
${CMAKE_CURRENT_SOURCE_DIR}/torc/src/torc/architecture/PrimitiveElement.o
${CMAKE_CURRENT_SOURCE_DIR}/torc/src/torc/architecture/PrimitiveElementPin.o
${CMAKE_CURRENT_SOURCE_DIR}/torc/src/torc/architecture/PrimitivePin.o
${CMAKE_CURRENT_SOURCE_DIR}/torc/src/torc/architecture/Segments.o
${CMAKE_CURRENT_SOURCE_DIR}/torc/src/torc/architecture/Site.o
${CMAKE_CURRENT_SOURCE_DIR}/torc/src/torc/architecture/Sites.o
${CMAKE_CURRENT_SOURCE_DIR}/torc/src/torc/architecture/Tiles.o
${CMAKE_CURRENT_SOURCE_DIR}/torc/src/torc/architecture/TileInfo.o
${CMAKE_CURRENT_SOURCE_DIR}/torc/src/torc/architecture/Tilewire.o
${CMAKE_CURRENT_SOURCE_DIR}/torc/src/torc/architecture/Versions.o
${CMAKE_CURRENT_SOURCE_DIR}/torc/src/torc/architecture/VprExporter.o
${CMAKE_CURRENT_SOURCE_DIR}/torc/src/torc/architecture/WireInfo.o
${CMAKE_CURRENT_SOURCE_DIR}/torc/src/torc/architecture/WireUsage.o
${CMAKE_CURRENT_SOURCE_DIR}/torc/src/torc/architecture/XdlImporter.o
${CMAKE_CURRENT_SOURCE_DIR}/torc/src/torc/architecture/XilinxDatabaseTypes.o
PRIVATE /opt/torc/src/torc/externals/zlib/zfstream.o
PRIVATE z
${CMAKE_CURRENT_SOURCE_DIR}/torc/src/torc/common/Annotated.o
${CMAKE_CURRENT_SOURCE_DIR}/torc/src/torc/common/DeviceDesignator.o
${CMAKE_CURRENT_SOURCE_DIR}/torc/src/torc/common/Devices.o
${CMAKE_CURRENT_SOURCE_DIR}/torc/src/torc/common/DirectoryTree.o
${CMAKE_CURRENT_SOURCE_DIR}/torc/src/torc/common/DottedVersion.o
${CMAKE_CURRENT_SOURCE_DIR}/torc/src/torc/common/NullOutputStream.o
PRIVATE /opt/torc/src/torc/physical/Circuit.o
PRIVATE /opt/torc/src/torc/physical/ConfigMap.o
PRIVATE /opt/torc/src/torc/physical/Config.o
PRIVATE /opt/torc/src/torc/physical/Design.o
PRIVATE /opt/torc/src/torc/physical/Factory.o
PRIVATE /opt/torc/src/torc/physical/Instance.o
PRIVATE /opt/torc/src/torc/physical/InstancePin.o
PRIVATE /opt/torc/src/torc/physical/InstanceReference.o
PRIVATE /opt/torc/src/torc/physical/Module.o
PRIVATE /opt/torc/src/torc/physical/ModuleTransformer.o
PRIVATE /opt/torc/src/torc/physical/Named.o
PRIVATE /opt/torc/src/torc/physical/Net.o
PRIVATE /opt/torc/src/torc/physical/OutputStreamHelpers.o
PRIVATE /opt/torc/src/torc/physical/Pip.o
PRIVATE /opt/torc/src/torc/physical/Port.o
PRIVATE /opt/torc/src/torc/physical/Progenitor.o
PRIVATE /opt/torc/src/torc/physical/Progeny.o
PRIVATE /opt/torc/src/torc/physical/Renamable.o
PRIVATE /opt/torc/src/torc/physical/Routethrough.o
PRIVATE /opt/torc/src/torc/physical/TilewirePlaceholder.o
PRIVATE /opt/torc/src/torc/physical/XdlExporter.o
# PRIVATE /opt/torc/src/torc/physical/XdlImporter.o
${CMAKE_CURRENT_SOURCE_DIR}/torc/src/torc/externals/zlib/zfstream.o
z
${CMAKE_CURRENT_SOURCE_DIR}/torc/src/torc/physical/Circuit.o
${CMAKE_CURRENT_SOURCE_DIR}/torc/src/torc/physical/ConfigMap.o
${CMAKE_CURRENT_SOURCE_DIR}/torc/src/torc/physical/Config.o
${CMAKE_CURRENT_SOURCE_DIR}/torc/src/torc/physical/Design.o
${CMAKE_CURRENT_SOURCE_DIR}/torc/src/torc/physical/Factory.o
${CMAKE_CURRENT_SOURCE_DIR}/torc/src/torc/physical/Instance.o
${CMAKE_CURRENT_SOURCE_DIR}/torc/src/torc/physical/InstancePin.o
${CMAKE_CURRENT_SOURCE_DIR}/torc/src/torc/physical/InstanceReference.o
${CMAKE_CURRENT_SOURCE_DIR}/torc/src/torc/physical/Module.o
${CMAKE_CURRENT_SOURCE_DIR}/torc/src/torc/physical/ModuleTransformer.o
${CMAKE_CURRENT_SOURCE_DIR}/torc/src/torc/physical/Named.o
${CMAKE_CURRENT_SOURCE_DIR}/torc/src/torc/physical/Net.o
${CMAKE_CURRENT_SOURCE_DIR}/torc/src/torc/physical/OutputStreamHelpers.o
${CMAKE_CURRENT_SOURCE_DIR}/torc/src/torc/physical/Pip.o
${CMAKE_CURRENT_SOURCE_DIR}/torc/src/torc/physical/Port.o
${CMAKE_CURRENT_SOURCE_DIR}/torc/src/torc/physical/Progenitor.o
${CMAKE_CURRENT_SOURCE_DIR}/torc/src/torc/physical/Progeny.o
${CMAKE_CURRENT_SOURCE_DIR}/torc/src/torc/physical/Renamable.o
${CMAKE_CURRENT_SOURCE_DIR}/torc/src/torc/physical/Routethrough.o
${CMAKE_CURRENT_SOURCE_DIR}/torc/src/torc/physical/TilewirePlaceholder.o
${CMAKE_CURRENT_SOURCE_DIR}/torc/src/torc/physical/XdlExporter.o
)

6
xc7/firmware_fast.hex Normal file
View File

@ -0,0 +1,6 @@
@00000000
13 04 20 00 B7 04 00 02 13 04 14 00 13 74 F4 0F
13 09 20 00 63 5E 89 00 13 05 04 00 93 05 09 00
EF 00 80 01 63 08 05 00 13 09 19 00 6F F0 9F FE
23 A0 84 00 6F F0 5F FD 93 02 10 00 33 05 B5 40
E3 5E 55 FE 67 80 00 00

0
xc7/firmware.hex → xc7/firmware_slow.hex
View File

14
xc7/icebreaker.pcf
View File

@ -1,14 +0,0 @@
set_io led1 27
set_io led2 25
set_io led3 21
set_io led4 23
set_io led5 26
set_io ledr 11
set_io ledg 37
set_io clki 35
set_io btn1 20
set_io btn2 19
set_io btn3 18
set_io btn_n 10

31
xc7/icebreaker.v
View File

@ -1,31 +0,0 @@
module icebreaker (
input clki,
input btn1,
input btn2,
input btn3,
input btn_n,
output led1,
output led2,
output led3,
output led4,
output led5,
output ledr,
output ledg,
);
wire clk;
SB_GB clk_gb(.USER_SIGNAL_TO_GLOBAL_BUFFER(clki), .GLOBAL_BUFFER_OUTPUT(clk));
localparam BITS = 5;
localparam LOG2DELAY = 22;
reg [BITS+LOG2DELAY-1:0] counter = 0;
reg [BITS-1:0] outcnt;
always @(posedge clk) begin
counter <= counter + 1;
outcnt <= counter >> LOG2DELAY;
end
assign {led1, led2, led3, led4, led5} = outcnt ^ (outcnt >> 1);
assign {ledr, ledg} = ~(!btn_n + btn1 + btn2 + btn3);
endmodule

3
xc7/icebreaker.ys
View File

@ -1,3 +0,0 @@
read_verilog icebreaker.v
synth_ice40 -nocarry -top icebreaker
write_json icebreaker.json

2
xc7/pack_tests/.gitignore vendored
View File

@ -1,2 +0,0 @@
*.vcd
*_out.v

43
xc7/pack_tests/ffmodes.v
View File

@ -1,43 +0,0 @@
module top(input clk, cen, rst, ina, inb, output reg outa, outb, outc, outd);
reg temp0 = 1'b0, temp1 = 1'b0;
initial outa = 1'b0;
initial outb = 1'b0;
initial outc = 1'b0;
initial outd = 1'b0;
always @(posedge clk)
if (cen)
if(rst)
temp0 <= 1'b0;
else
temp0 <= ina;
always @(negedge clk)
if (ina)
if(rst)
temp1 <= 1'b1;
else
temp1 <= inb;
always @(posedge clk or posedge rst)
if(rst)
outa <= 1'b0;
else
outa <= temp0;
always @(posedge clk)
outb <= temp1;
always @(negedge clk)
outc <= temp0;
always @(negedge clk or posedge rst)
if (rst)
outd <= 1'b1;
else
outd <= temp1;
endmodule

27
xc7/pack_tests/locals.v
View File

@ -1,27 +0,0 @@
module top(input clk, cen, rst, ina, inb, output outa, outb, outc, outd);
reg [31:0] temp = 0;
integer i;
always @(posedge clk)
begin
if (cen) begin
if (rst) begin
temp <= 0;
end else begin
temp[0] <= ina;
temp[1] <= inb;
for (i = 2; i < 32; i++) begin
temp[i] <= temp[(i + 3) % 32] ^ temp[(i + 30) % 32] ^ temp[(i + 4) % 16] ^ temp[(i + 2) % 32];
end
end
end
end
assign outa = temp[3];
assign outb = temp[5];
assign outc = temp[9];
assign outd = temp[15];
endmodule

54
xc7/pack_tests/place_constr.v
View File

@ -1,54 +0,0 @@
module top(input clk, cen, rst, ina, inb, output outa, outb, outc, outd);
wire temp0, temp1;
(* BEL="1_1_lc0" *)
SB_LUT4 #(
.LUT_INIT(2'b01)
) lut0 (
.I3(),
.I2(),
.I1(),
.I0(ina),
.O(temp0)
);
(* BEL="1_3_lc0" *)
SB_LUT4 #(
.LUT_INIT(2'b01)
) lut1 (
.I3(),
.I2(),
.I1(),
.I0(inb),
.O(temp1)
);
(* BEL="1_1_lc0" *)
SB_DFF ff0 (
.C(clk),
.D(temp1),
.Q(outa)
);
(* BEL="1_1_lc7" *)
SB_DFF ff1 (
.C(clk),
.D(inb),
.Q(outb)
);
(* BEL="1_6_lc7" *)
SB_DFF ff2 (
.C(clk),
.D(temp1),
.Q(outc)
);
assign outd = 1'b0;
endmodule

10
xc7/pack_tests/test.pcf
View File

@ -1,10 +0,0 @@
set_io clk 1
set_io cen 2
set_io rst 3
set_io ina 4
set_io inb 7
set_io outa 8
set_io outb 9
set_io outc 10
set_io outd 11

16
xc7/pack_tests/test.sh
View File

@ -1,16 +0,0 @@
#!/usr/bin/env bash
set -ex
NAME=${1%.v}
yosys -p "synth_ice40 -nocarry -top top; write_json ${NAME}.json" $1
../../nextpnr-ice40 --json ${NAME}.json --pcf test.pcf --asc ${NAME}.asc
icebox_vlog -p test.pcf ${NAME}.asc > ${NAME}_out.v
yosys -p "read_verilog +/ice40/cells_sim.v;\
rename chip gate;\
read_verilog $1;\
rename top gold;\
hierarchy;\
proc;\
clk2fflogic;\
miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp gold gate miter;\
sat -dump_vcd equiv_${NAME}.vcd -verify-no-timeout -timeout 60 -seq 50 -prove trigger 0 -prove-skip 1 -show-inputs -show-outputs miter" ${NAME}_out.v

6
xc7/picorv32.pcf
View File

@ -1,3 +1,3 @@
NET "pll.clkin1" PERIOD = 8 nS ;
#PIN "clk_pin" = BEL "clk.PAD" PINNAME PAD;
#PIN "clk_pin" CLOCK_DEDICATED_ROUTE = FALSE;
NET "clki" PERIOD = 8 nS ;
PIN "clki_pin" = BEL "clki.PAD" PINNAME PAD;
PIN "clki_pin" CLOCK_DEDICATED_ROUTE = FALSE;

4
xc7/picorv32.sh
View File

@ -3,7 +3,9 @@ set -ex
rm -f picorv32.v
wget https://raw.githubusercontent.com/cliffordwolf/picorv32/master/picorv32.v
yosys picorv32.ys
../nextpnr-xc7 --json picorv32.json --xdl picorv32.xdl --pcf picorv32.pcf --freq 150
set +e
../nextpnr-xc7 --json picorv32.json --xdl picorv32.xdl --pcf picorv32.pcf --freq 125
set -e
xdl -xdl2ncd picorv32.xdl
#bitgen -w blinky.ncd -g UnconstrainedPins:Allow
trce picorv32.ncd -v 10

16
xc7/picorv32_top.v
View File

@ -1,5 +1,5 @@
module top (
input clk, resetn,
input clki, resetn,
output trap,
output mem_valid,
@ -12,7 +12,17 @@ module top (
input [31:0] mem_rdata
);
clk_wiz_v3_6 pll(.CLK_IN1(clk), .CLK_OUT1(gclk));
wire clk;
BUFGCTRL clk_gb (
.I0(clki),
.CE0(1'b1),
.CE1(1'b0),
.S0(1'b1),
.S1(1'b0),
.IGNORE0(1'b0),
.IGNORE1(1'b0),
.O(clk)
);
picorv32 #(
.ENABLE_COUNTERS(0),
@ -20,7 +30,7 @@ module top (
.CATCH_MISALIGN(0),
.CATCH_ILLINSN(0)
) cpu (
.clk (gclk ),
.clk (clk ),
.resetn (resetn ),
.trap (trap ),
.mem_valid(mem_valid),

328
xc7/ps7.vh
View File

@ -1,328 +0,0 @@
(* keep *)
PS7 ps7_stub(
.DDRARB ('b0),
.DMA0ACLK ('b0),
.DMA0DAREADY ('b0),
.DMA0DRLAST ('b0),
.DMA0DRTYPE ('b0),
.DMA0DRVALID ('b0),
.DMA1ACLK ('b0),
.DMA1DAREADY ('b0),
.DMA1DRLAST ('b0),
.DMA1DRTYPE ('b0),
.DMA1DRVALID ('b0),
.DMA2ACLK ('b0),
.DMA2DAREADY ('b0),
.DMA2DRLAST ('b0),
.DMA2DRTYPE ('b0),
.DMA2DRVALID ('b0),
.DMA3ACLK ('b0),
.DMA3DAREADY ('b0),
.DMA3DRLAST ('b0),
.DMA3DRTYPE ('b0),
.DMA3DRVALID ('b0),
.EMIOCAN0PHYRX ('b0),
.EMIOCAN1PHYRX ('b0),
.EMIOENET0EXTINTIN ('b0),
.EMIOENET0GMIICOL ('b0),
.EMIOENET0GMIICRS ('b0),
.EMIOENET0GMIIRXCLK ('b0),
.EMIOENET0GMIIRXD ('b0),
.EMIOENET0GMIIRXDV ('b0),
.EMIOENET0GMIIRXER ('b0),
.EMIOENET0GMIITXCLK ('b0),
.EMIOENET0MDIOI ('b0),
.EMIOENET1EXTINTIN ('b0),
.EMIOENET1GMIICOL ('b0),
.EMIOENET1GMIICRS ('b0),
.EMIOENET1GMIIRXCLK ('b0),
.EMIOENET1GMIIRXD ('b0),
.EMIOENET1GMIIRXDV ('b0),
.EMIOENET1GMIIRXER ('b0),
.EMIOENET1GMIITXCLK ('b0),
.EMIOENET1MDIOI ('b0),
.EMIOGPIOI ('b0),
.EMIOI2C0SCLI ('b0),
.EMIOI2C0SDAI ('b0),
.EMIOI2C1SCLI ('b0),
.EMIOI2C1SDAI ('b0),
.EMIOPJTAGTCK ('b0),
.EMIOPJTAGTDI ('b0),
.EMIOPJTAGTMS ('b0),
.EMIOSDIO0CDN ('b0),
.EMIOSDIO0CLKFB ('b0),
.EMIOSDIO0CMDI ('b0),
.EMIOSDIO0DATAI ('b0),
.EMIOSDIO0WP ('b0),
.EMIOSDIO1CDN ('b0),
.EMIOSDIO1CLKFB ('b0),
.EMIOSDIO1CMDI ('b0),
.EMIOSDIO1DATAI ('b0),
.EMIOSDIO1WP ('b0),
.EMIOSPI0MI ('b0),
.EMIOSPI0SCLKI ('b0),
.EMIOSPI0SI ('b0),
.EMIOSPI0SSIN ('b0),
.EMIOSPI1MI ('b0),
.EMIOSPI1SCLKI ('b0),
.EMIOSPI1SI ('b0),
.EMIOSPI1SSIN ('b0),
.EMIOSRAMINTIN ('b0),
.EMIOTRACECLK ('b0),
.EMIOTTC0CLKI ('b0),
.EMIOTTC1CLKI ('b0),
.EMIOUART0CTSN ('b0),
.EMIOUART0DCDN ('b0),
.EMIOUART0DSRN ('b0),
.EMIOUART0RIN ('b0),
.EMIOUART0RX ('b0),
.EMIOUART1CTSN ('b0),
.EMIOUART1DCDN ('b0),
.EMIOUART1DSRN ('b0),
.EMIOUART1RIN ('b0),
.EMIOUART1RX ('b0),
.EMIOUSB0VBUSPWRFAULT ('b0),
.EMIOUSB1VBUSPWRFAULT ('b0),
.EMIOWDTCLKI ('b0),
.EVENTEVENTI ('b0),
.FCLKCLKTRIGN ('b0),
.FPGAIDLEN ('b0),
.FTMDTRACEINATID ('b0),
.FTMDTRACEINCLOCK ('b0),
.FTMDTRACEINDATA ('b0),
.FTMDTRACEINVALID ('b0),
.FTMTF2PDEBUG ('b0),
.FTMTF2PTRIG ('b0),
.FTMTP2FTRIGACK ('b0),
.IRQF2P ('b0),
.MAXIGP0ACLK ('b0),
.MAXIGP0ARREADY ('b0),
.MAXIGP0AWREADY ('b0),
.MAXIGP0BID ('b0),
.MAXIGP0BRESP ('b0),
.MAXIGP0BVALID ('b0),
.MAXIGP0RDATA ('b0),
.MAXIGP0RID ('b0),
.MAXIGP0RLAST ('b0),
.MAXIGP0RRESP ('b0),
.MAXIGP0RVALID ('b0),
.MAXIGP0WREADY ('b0),
.MAXIGP1ACLK ('b0),
.MAXIGP1ARREADY ('b0),
.MAXIGP1AWREADY ('b0),
.MAXIGP1BID ('b0),
.MAXIGP1BRESP ('b0),
.MAXIGP1BVALID ('b0),
.MAXIGP1RDATA ('b0),
.MAXIGP1RID ('b0),
.MAXIGP1RLAST ('b0),
.MAXIGP1RRESP ('b0),
.MAXIGP1RVALID ('b0),
.MAXIGP1WREADY ('b0),
.SAXIACPACLK ('b0),
.SAXIACPARADDR ('b0),
.SAXIACPARBURST ('b0),
.SAXIACPARCACHE ('b0),
.SAXIACPARID ('b0),
.SAXIACPARLEN ('b0),
.SAXIACPARLOCK ('b0),
.SAXIACPARPROT ('b0),
.SAXIACPARQOS ('b0),
.SAXIACPARSIZE ('b0),
.SAXIACPARUSER ('b0),
.SAXIACPARVALID ('b0),
.SAXIACPAWADDR ('b0),
.SAXIACPAWBURST ('b0),
.SAXIACPAWCACHE ('b0),
.SAXIACPAWID ('b0),
.SAXIACPAWLEN ('b0),
.SAXIACPAWLOCK ('b0),
.SAXIACPAWPROT ('b0),
.SAXIACPAWQOS ('b0),
.SAXIACPAWSIZE ('b0),
.SAXIACPAWUSER ('b0),
.SAXIACPAWVALID ('b0),
.SAXIACPBREADY ('b0),
.SAXIACPRREADY ('b0),
.SAXIACPWDATA ('b0),
.SAXIACPWID ('b0),
.SAXIACPWLAST ('b0),
.SAXIACPWSTRB ('b0),
.SAXIACPWVALID ('b0),
.SAXIGP0ACLK ('b0),
.SAXIGP0ARADDR ('b0),
.SAXIGP0ARBURST ('b0),
.SAXIGP0ARCACHE ('b0),
.SAXIGP0ARID ('b0),
.SAXIGP0ARLEN ('b0),
.SAXIGP0ARLOCK ('b0),
.SAXIGP0ARPROT ('b0),
.SAXIGP0ARQOS ('b0),
.SAXIGP0ARSIZE ('b0),
.SAXIGP0ARVALID ('b0),
.SAXIGP0AWADDR ('b0),
.SAXIGP0AWBURST ('b0),
.SAXIGP0AWCACHE ('b0),
.SAXIGP0AWID ('b0),
.SAXIGP0AWLEN ('b0),
.SAXIGP0AWLOCK ('b0),
.SAXIGP0AWPROT ('b0),
.SAXIGP0AWQOS ('b0),
.SAXIGP0AWSIZE ('b0),
.SAXIGP0AWVALID ('b0),
.SAXIGP0BREADY ('b0),
.SAXIGP0RREADY ('b0),
.SAXIGP0WDATA ('b0),
.SAXIGP0WID ('b0),
.SAXIGP0WLAST ('b0),
.SAXIGP0WSTRB ('b0),
.SAXIGP0WVALID ('b0),
.SAXIGP1ACLK ('b0),
.SAXIGP1ARADDR ('b0),
.SAXIGP1ARBURST ('b0),
.SAXIGP1ARCACHE ('b0),
.SAXIGP1ARID ('b0),
.SAXIGP1ARLEN ('b0),
.SAXIGP1ARLOCK ('b0),
.SAXIGP1ARPROT ('b0),
.SAXIGP1ARQOS ('b0),
.SAXIGP1ARSIZE ('b0),
.SAXIGP1ARVALID ('b0),
.SAXIGP1AWADDR ('b0),
.SAXIGP1AWBURST ('b0),
.SAXIGP1AWCACHE ('b0),
.SAXIGP1AWID ('b0),
.SAXIGP1AWLEN ('b0),
.SAXIGP1AWLOCK ('b0),
.SAXIGP1AWPROT ('b0),
.SAXIGP1AWQOS ('b0),
.SAXIGP1AWSIZE ('b0),
.SAXIGP1AWVALID ('b0),
.SAXIGP1BREADY ('b0),
.SAXIGP1RREADY ('b0),
.SAXIGP1WDATA ('b0),
.SAXIGP1WID ('b0),
.SAXIGP1WLAST ('b0),
.SAXIGP1WSTRB ('b0),
.SAXIGP1WVALID ('b0),
.SAXIHP0ACLK ('b0),
.SAXIHP0ARADDR ('b0),
.SAXIHP0ARBURST ('b0),
.SAXIHP0ARCACHE ('b0),
.SAXIHP0ARID ('b0),
.SAXIHP0ARLEN ('b0),
.SAXIHP0ARLOCK ('b0),
.SAXIHP0ARPROT ('b0),
.SAXIHP0ARQOS ('b0),
.SAXIHP0ARSIZE ('b0),
.SAXIHP0ARVALID ('b0),
.SAXIHP0AWADDR ('b0),
.SAXIHP0AWBURST ('b0),
.SAXIHP0AWCACHE ('b0),
.SAXIHP0AWID ('b0),
.SAXIHP0AWLEN ('b0),
.SAXIHP0AWLOCK ('b0),
.SAXIHP0AWPROT ('b0),
.SAXIHP0AWQOS ('b0),
.SAXIHP0AWSIZE ('b0),
.SAXIHP0AWVALID ('b0),
.SAXIHP0BREADY ('b0),
.SAXIHP0RDISSUECAP1EN ('b0),
.SAXIHP0RREADY ('b0),
.SAXIHP0WDATA ('b0),
.SAXIHP0WID ('b0),
.SAXIHP0WLAST ('b0),
.SAXIHP0WRISSUECAP1EN ('b0),
.SAXIHP0WSTRB ('b0),
.SAXIHP0WVALID ('b0),
.SAXIHP1ACLK ('b0),
.SAXIHP1ARADDR ('b0),
.SAXIHP1ARBURST ('b0),
.SAXIHP1ARCACHE ('b0),
.SAXIHP1ARID ('b0),
.SAXIHP1ARLEN ('b0),
.SAXIHP1ARLOCK ('b0),
.SAXIHP1ARPROT ('b0),
.SAXIHP1ARQOS ('b0),
.SAXIHP1ARSIZE ('b0),
.SAXIHP1ARVALID ('b0),
.SAXIHP1AWADDR ('b0),
.SAXIHP1AWBURST ('b0),
.SAXIHP1AWCACHE ('b0),
.SAXIHP1AWID ('b0),
.SAXIHP1AWLEN ('b0),
.SAXIHP1AWLOCK ('b0),
.SAXIHP1AWPROT ('b0),
.SAXIHP1AWQOS ('b0),
.SAXIHP1AWSIZE ('b0),
.SAXIHP1AWVALID ('b0),
.SAXIHP1BREADY ('b0),
.SAXIHP1RDISSUECAP1EN ('b0),
.SAXIHP1RREADY ('b0),
.SAXIHP1WDATA ('b0),
.SAXIHP1WID ('b0),
.SAXIHP1WLAST ('b0),
.SAXIHP1WRISSUECAP1EN ('b0),
.SAXIHP1WSTRB ('b0),
.SAXIHP1WVALID ('b0),
.SAXIHP2ACLK ('b0),
.SAXIHP2ARADDR ('b0),
.SAXIHP2ARBURST ('b0),
.SAXIHP2ARCACHE ('b0),
.SAXIHP2ARID ('b0),
.SAXIHP2ARLEN ('b0),
.SAXIHP2ARLOCK ('b0),
.SAXIHP2ARPROT ('b0),
.SAXIHP2ARQOS ('b0),
.SAXIHP2ARSIZE ('b0),
.SAXIHP2ARVALID ('b0),
.SAXIHP2AWADDR ('b0),
.SAXIHP2AWBURST ('b0),
.SAXIHP2AWCACHE ('b0),
.SAXIHP2AWID ('b0),
.SAXIHP2AWLEN ('b0),
.SAXIHP2AWLOCK ('b0),
.SAXIHP2AWPROT ('b0),
.SAXIHP2AWQOS ('b0),
.SAXIHP2AWSIZE ('b0),
.SAXIHP2AWVALID ('b0),
.SAXIHP2BREADY ('b0),
.SAXIHP2RDISSUECAP1EN ('b0),
.SAXIHP2RREADY ('b0),
.SAXIHP2WDATA ('b0),
.SAXIHP2WID ('b0),
.SAXIHP2WLAST ('b0),
.SAXIHP2WRISSUECAP1EN ('b0),
.SAXIHP2WSTRB ('b0),
.SAXIHP2WVALID ('b0),
.SAXIHP3ACLK ('b0),
.SAXIHP3ARADDR ('b0),
.SAXIHP3ARBURST ('b0),
.SAXIHP3ARCACHE ('b0),
.SAXIHP3ARID ('b0),
.SAXIHP3ARLEN ('b0),
.SAXIHP3ARLOCK ('b0),
.SAXIHP3ARPROT ('b0),
.SAXIHP3ARQOS ('b0),
.SAXIHP3ARSIZE ('b0),
.SAXIHP3ARVALID ('b0),
.SAXIHP3AWADDR ('b0),
.SAXIHP3AWBURST ('b0),
.SAXIHP3AWCACHE ('b0),
.SAXIHP3AWID ('b0),
.SAXIHP3AWLEN ('b0),
.SAXIHP3AWLOCK ('b0),
.SAXIHP3AWPROT ('b0),
.SAXIHP3AWQOS ('b0),
.SAXIHP3AWSIZE ('b0),
.SAXIHP3AWVALID ('b0),
.SAXIHP3BREADY ('b0),
.SAXIHP3RDISSUECAP1EN ('b0),
.SAXIHP3RREADY ('b0),
.SAXIHP3WDATA ('b0),
.SAXIHP3WID ('b0),
.SAXIHP3WLAST ('b0),
.SAXIHP3WRISSUECAP1EN ('b0),
.SAXIHP3WSTRB ('b0),
.SAXIHP3WVALID ('b0)
);

6
xc7/resource/chipdb.rc
View File

@ -1,6 +0,0 @@
#include "resource.h"
IDR_CHIPDB_384 BINARYFILE "..\chipdbs\chipdb-384.bin"
IDR_CHIPDB_1K BINARYFILE "..\chipdbs\chipdb-1k.bin"
IDR_CHIPDB_5K BINARYFILE "..\chipdbs\chipdb-5k.bin"
IDR_CHIPDB_8K BINARYFILE "..\chipdbs\chipdb-8k.bin"

30
xc7/resource/embed.cc
View File

@ -1,30 +0,0 @@
#include <cstdio>
#include <windows.h>
#include "nextpnr.h"
#include "resource.h"
NEXTPNR_NAMESPACE_BEGIN
const char *chipdb_blob_384;
const char *chipdb_blob_1k;
const char *chipdb_blob_5k;
const char *chipdb_blob_8k;
const char *LoadFileInResource(int name, int type, DWORD &size)
{
HMODULE handle = ::GetModuleHandle(NULL);
HRSRC rc = ::FindResource(handle, MAKEINTRESOURCE(name), MAKEINTRESOURCE(type));
HGLOBAL rcData = ::LoadResource(handle, rc);
size = ::SizeofResource(handle, rc);
return static_cast<const char *>(::LockResource(rcData));
}
void load_chipdb()
{
DWORD size = 0;
chipdb_blob_384 = LoadFileInResource(IDR_CHIPDB_384, BINARYFILE, size);
chipdb_blob_1k = LoadFileInResource(IDR_CHIPDB_1K, BINARYFILE, size);
chipdb_blob_5k = LoadFileInResource(IDR_CHIPDB_5K, BINARYFILE, size);
chipdb_blob_8k = LoadFileInResource(IDR_CHIPDB_8K, BINARYFILE, size);
}
NEXTPNR_NAMESPACE_END

5
xc7/resource/resource.h
View File

@ -1,5 +0,0 @@
#define BINARYFILE 256
#define IDR_CHIPDB_384 101
#define IDR_CHIPDB_1K 102
#define IDR_CHIPDB_5K 103
#define IDR_CHIPDB_8K 104

2
xc7/xdl.cc
View File

@ -182,9 +182,9 @@ DesignSharedPtr create_torc_design(const Context *ctx)
if (get_net_or_empty(cell.second.get(), id_SR)) {
instPtr->setConfig(setting + "SR", "", cell.second->params.at(id_SR));
instPtr->setConfig("SYNC_ATTR", "", cell.second->params.at(ctx->id("SYNC_ATTR")));
instPtr->setConfig("SRUSEDMUX", "", "IN");
}
instPtr->setConfig("SYNC_ATTR", "", cell.second->params.at(ctx->id("SYNC_ATTR")));
if (get_net_or_empty(cell.second.get(), ctx->id("CE")))
instPtr->setConfig("CEUSEDMUX", "", "IN");