Merge branch 'master' into shadowram
This commit is contained in:
Pepijn de Vos
commit
0641ff47d9
@ -145,7 +145,8 @@ An example of how to use the generic flow is in [generic/examples](generic/examp
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The nextpnr GUI is not built by default, to reduce the number of dependencies for a standard headless build. To enable it, add `-DBUILD_GUI=ON` to the CMake command line and ensure that Qt5 and OpenGL are available:
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- On Ubuntu, install `qt5-default`
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- On Ubuntu 22.04 LTS, install `qtcreator qtbase5-dev qt5-qmake`
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- On other Ubuntu versions, install `qt5-default`
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- For MSVC vcpkg, install `qt5-base` (32-bit) or `qt5-base:x64-windows` (64-bit)
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- For Homebrew, install `qt5` and add qt5 in path: `echo 'export PATH="/usr/local/opt/qt/bin:$PATH"' >> ~/.bash_profile`
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` - this change is effective in next terminal session, so please re-open terminal window before building
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@ -21,6 +21,7 @@
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#ifndef NO_PYTHON
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#include "arch_pybindings.h"
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#include "bitstream.h"
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#include "nextpnr.h"
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#include "pybindings.h"
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@ -69,6 +70,8 @@ void arch_wrap_python(py::module &m)
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WRAP_MAP_UPTR(m, CellMap, "IdCellMap");
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WRAP_MAP_UPTR(m, NetMap, "IdNetMap");
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WRAP_MAP(m, HierarchyMap, wrap_context<HierarchicalCell &>, "HierarchyMap");
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m.def("write_bitstream", &write_bitstream);
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}
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NEXTPNR_NAMESPACE_END
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224
gowin/arch.cc
224
gowin/arch.cc
@ -19,6 +19,7 @@
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*/
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#include <boost/algorithm/string.hpp>
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#include <cells.h>
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#include <iostream>
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#include <math.h>
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#include <regex>
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@ -33,6 +34,8 @@
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NEXTPNR_NAMESPACE_BEGIN
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const PairPOD *pairLookup(const PairPOD *list, const size_t len, const int dest);
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// GUI
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void Arch::fixClockSpineDecals(void)
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{
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@ -175,6 +178,145 @@ DecalXY Arch::getWireDecal(WireId wire) const
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return wires.at(wire).decalxy_active;
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}
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bool Arch::allocate_longwire(NetInfo *ni, int lw_idx)
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{
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NPNR_ASSERT(ni != nullptr);
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if (ni->driver.cell == nullptr) {
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return false;
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}
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if (ni->name == id("$PACKER_VCC_NET") || ni->name == id("$PACKER_GND_NET")) {
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return false;
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}
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// So far only for OBUF
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switch (ni->driver.cell->type.index) {
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case ID_ODDR: /* fall-through*/
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case ID_ODDRC: /* fall-through*/
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case ID_IOBUF: /* fall-through*/
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case ID_TBUF:
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return false;
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case ID_OBUF:
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if (getCtx()->debug) {
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log_info("Long wire for IO %s\n", nameOf(ni));
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}
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ni = ni->driver.cell->ports.at(id_I).net;
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return allocate_longwire(ni, lw_idx);
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break;
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default:
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break;
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}
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if (getCtx()->debug) {
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log_info("Requested index:%d\n", lw_idx);
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}
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if (avail_longwires == 0 || (lw_idx != -1 && (avail_longwires & (1 << lw_idx)) == 0)) {
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return false;
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}
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int longwire = lw_idx;
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if (lw_idx == -1) {
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for (longwire = 7; longwire >= 0; --longwire) {
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if (avail_longwires & (1 << longwire)) {
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break;
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}
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}
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}
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avail_longwires &= ~(1 << longwire);
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// BUFS cell
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CellInfo *bufs;
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char buf[40];
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snprintf(buf, sizeof(buf), "$PACKER_BUFS%d", longwire);
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std::unique_ptr<CellInfo> new_cell = create_generic_cell(getCtx(), id_BUFS, buf);
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bufs = new_cell.get();
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cells[bufs->name] = std::move(new_cell);
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if (lw_idx != -1) {
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bufs->cluster = bufs->name;
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bufs->constr_z = lw_idx + BelZ::bufs_0_z;
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bufs->constr_abs_z = true;
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bufs->constr_children.clear();
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}
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// old driver -> bufs LW input net
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snprintf(buf, sizeof(buf), "$PACKER_BUFS_%c", longwire + 'A');
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auto net = std::make_unique<NetInfo>(id(buf));
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NetInfo *bufs_net = net.get();
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nets[net->name] = std::move(net);
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// split the net
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CellInfo *driver_cell = ni->driver.cell;
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IdString driver_port = ni->driver.port;
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driver_cell->disconnectPort(driver_port);
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bufs->connectPort(id_O, ni);
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bufs->connectPort(id_I, bufs_net);
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driver_cell->connectPort(driver_port, bufs_net);
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if (getCtx()->debug) {
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log_info("Long wire %d was allocated\n", longwire);
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}
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return true;
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}
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void Arch::fix_longwire_bels()
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{
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// After routing, it is clear which wires and in which bus SS00 and SS40 are used and
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// in which quadrant they are routed. Here we write it in the attributes.
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for (auto &cell : cells) {
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CellInfo *ci = cell.second.get();
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if (ci->type != id_BUFS) {
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continue;
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}
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const NetInfo *ni = ci->getPort(id_O);
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if (ni == nullptr) {
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continue;
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}
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// bus wire is one of the wires
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// value does not matter, but the L/R parameter itself
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for (auto &wire : ni->wires) {
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WireId w = wires[wire.first].type;
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switch (w.hash()) {
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case ID_LWSPINETL0:
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case ID_LWSPINETL1:
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case ID_LWSPINETL2:
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case ID_LWSPINETL3:
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case ID_LWSPINETL4:
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case ID_LWSPINETL5:
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case ID_LWSPINETL6:
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case ID_LWSPINETL7:
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case ID_LWSPINEBL0:
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case ID_LWSPINEBL1:
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case ID_LWSPINEBL2:
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case ID_LWSPINEBL3:
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case ID_LWSPINEBL4:
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case ID_LWSPINEBL5:
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case ID_LWSPINEBL6:
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case ID_LWSPINEBL7:
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ci->setParam(id("L"), Property(w.str(this)));
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break;
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case ID_LWSPINETR0:
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case ID_LWSPINETR1:
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case ID_LWSPINETR2:
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case ID_LWSPINETR3:
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case ID_LWSPINETR4:
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case ID_LWSPINETR5:
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case ID_LWSPINETR6:
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case ID_LWSPINETR7:
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case ID_LWSPINEBR0:
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case ID_LWSPINEBR1:
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case ID_LWSPINEBR2:
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case ID_LWSPINEBR3:
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case ID_LWSPINEBR4:
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case ID_LWSPINEBR5:
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case ID_LWSPINEBR6:
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case ID_LWSPINEBR7:
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ci->setParam(id("R"), Property(w.str(this)));
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break;
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default:
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break;
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}
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}
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}
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}
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WireInfo &Arch::wire_info(IdString wire)
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{
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auto w = wires.find(wire);
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@ -487,7 +629,15 @@ IdString Arch::wireToGlobal(int &row, int &col, const DatabasePOD *db, IdString
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}
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snprintf(buf, 32, "%c%d0", direction, num);
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wire = id(buf);
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snprintf(buf, 32, "R%dC%d_%c%d", row + 1, col + 1, direction, num);
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// local aliases
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const TilePOD *tile = db->grid[row * db->cols + col].get();
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auto local_alias = pairLookup(tile->aliases.get(), tile->num_aliases, wire.index);
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if (local_alias != nullptr) {
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wire = IdString(local_alias->src_id);
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snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, wire.c_str(this));
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} else {
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snprintf(buf, 32, "R%dC%d_%c%d", row + 1, col + 1, direction, num);
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}
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return id(buf);
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}
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@ -628,6 +778,28 @@ DelayQuad Arch::getWireTypeDelay(IdString wire)
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case ID_W830:
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len = id_X8;
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break;
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case ID_LT02:
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case ID_LT13:
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glbsrc = id_SPINE_TAP_SCLK_0;
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break;
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case ID_LT01:
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case ID_LT04:
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glbsrc = id_SPINE_TAP_SCLK_1;
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break;
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case ID_LBO0:
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case ID_LBO1:
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glbsrc = id_TAP_BRANCH_SCLK;
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break;
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case ID_LB01:
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case ID_LB11:
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case ID_LB21:
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case ID_LB31:
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case ID_LB41:
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case ID_LB51:
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case ID_LB61:
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case ID_LB71:
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glbsrc = id_BRANCH_SCLK;
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break;
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case ID_GT00:
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case ID_GT10:
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glbsrc = id_SPINE_TAP_PCLK;
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@ -647,7 +819,9 @@ DelayQuad Arch::getWireTypeDelay(IdString wire)
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glbsrc = id_BRANCH_PCLK;
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break;
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default:
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if (wire.str(this).rfind("SPINE", 0) == 0) {
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if (wire.str(this).rfind("LWSPINE", 0) == 0) {
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glbsrc = IdString(ID_CENT_SPINE_SCLK);
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} else if (wire.str(this).rfind("SPINE", 0) == 0) {
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glbsrc = IdString(ID_CENT_SPINE_PCLK);
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} else if (wire.str(this).rfind("UNK", 0) == 0) {
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glbsrc = IdString(ID_PIO_CENT_PCLK);
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@ -691,7 +865,7 @@ void Arch::read_cst(std::istream &in)
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std::regex port_attrre = std::regex("([^ =;]+=[^ =;]+) *([^;]*;)");
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std::regex iobelre = std::regex("IO([TRBL])([0-9]+)\\[?([A-Z])\\]?");
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std::regex inslocre = std::regex("INS_LOC +\"([^\"]+)\" +R([0-9]+)C([0-9]+)\\[([0-9])\\]\\[([AB])\\] *;.*");
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std::regex clockre = std::regex("CLOCK_LOC +\"([^\"]+)\" +BUF([GS])[^;]*;");
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std::regex clockre = std::regex("CLOCK_LOC +\"([^\"]+)\" +BUF([GS])(\\[([0-7])\\])?[^;]*;.*");
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std::smatch match, match_attr, match_pinloc;
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std::string line, pinline;
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enum
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@ -732,15 +906,23 @@ void Arch::read_cst(std::istream &in)
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continue;
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}
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switch (cst_type) {
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case clock: { // CLOCK name BUFG|S
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case clock: { // CLOCK name BUFG|S=#
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std::string which_clock = match[2];
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std::string lw = match[4];
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int lw_idx = -1;
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if (lw.length() > 0) {
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lw_idx = atoi(lw.c_str());
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log_info("lw_idx:%d\n", lw_idx);
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}
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if (which_clock.at(0) == 'S') {
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auto ni = nets.find(net);
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if (ni == nets.end()) {
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log_info("Net %s not found\n", net.c_str(this));
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continue;
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}
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log_info("Long wires are not implemented. The %s network will use normal routing.\n", net.c_str(this));
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if (!allocate_longwire(ni->second.get(), lw_idx)) {
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log_info("Can't use the long wires. The %s network will use normal routing.\n", net.c_str(this));
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}
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} else {
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log_info("BUFG isn't supported\n");
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continue;
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@ -1021,6 +1203,31 @@ Arch::Arch(ArchArgs args) : args(args)
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bool dff = true;
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bool oddrc = false;
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switch (static_cast<ConstIds>(bel->type_id)) {
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case ID_BUFS7:
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z++; /* fall-through*/
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case ID_BUFS6:
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z++; /* fall-through*/
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case ID_BUFS5:
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z++; /* fall-through*/
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case ID_BUFS4:
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z++; /* fall-through*/
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case ID_BUFS3:
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z++; /* fall-through*/
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case ID_BUFS2:
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z++; /* fall-through*/
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case ID_BUFS1:
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z++; /* fall-through*/
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case ID_BUFS0:
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snprintf(buf, 32, "R%dC%d_BUFS%d", row + 1, col + 1, z);
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belname = id(buf);
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addBel(belname, id_BUFS, Loc(col, row, BelZ::bufs_0_z + z), false);
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portname = IdString(pairLookup(bel->ports.get(), bel->num_ports, ID_I)->src_id);
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snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
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addBelInput(belname, id_I, id(buf));
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portname = IdString(pairLookup(bel->ports.get(), bel->num_ports, ID_O)->src_id);
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snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
|
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addBelOutput(belname, id_O, id(buf));
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break;
|
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case ID_GSR0:
|
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snprintf(buf, 32, "R%dC%d_GSR0", row + 1, col + 1);
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belname = id(buf);
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@ -1324,12 +1531,6 @@ Arch::Arch(ArchArgs args) : args(args)
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snprintf(buf, 32, "R%dC%d_%s_%s", row + 1, col + 1, srcid.c_str(this), destid.c_str(this));
|
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IdString pipname = id(buf);
|
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DelayQuad delay = getWireTypeDelay(destid);
|
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// local alias
|
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auto local_alias = pairLookup(tile->aliases.get(), tile->num_aliases, srcid.index);
|
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if (local_alias != nullptr) {
|
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srcid = IdString(local_alias->src_id);
|
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gsrcname = wireToGlobal(srcrow, srccol, db, srcid);
|
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}
|
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// global alias
|
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srcid = IdString(pip.src_id);
|
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GlobalAliasPOD alias;
|
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@ -1705,6 +1906,7 @@ bool Arch::route()
|
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}
|
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getCtx()->settings[id_route] = 1;
|
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archInfoToAttributes();
|
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fix_longwire_bels();
|
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return result;
|
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}
|
||||
|
||||
|
||||
10
gowin/arch.h
10
gowin/arch.h
@ -459,6 +459,9 @@ struct Arch : BaseArch<ArchRanges>
|
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void assignArchInfo() override;
|
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bool cellsCompatible(const CellInfo **cells, int count) const;
|
||||
bool haveBelType(int x, int y, IdString bel_type);
|
||||
bool allocate_longwire(NetInfo *ni, int lw_idx = -1);
|
||||
void fix_longwire_bels();
|
||||
|
||||
// chip db version
|
||||
unsigned int const chipdb_version = 1;
|
||||
|
||||
@ -475,6 +478,9 @@ struct Arch : BaseArch<ArchRanges>
|
||||
// XXX GW1NR-9 iobuf quirk
|
||||
bool gw1n9_quirk = false;
|
||||
|
||||
// 8 Long wires
|
||||
uint8_t avail_longwires = 0xff;
|
||||
|
||||
// Permissible combinations of modes in a single slice
|
||||
std::map<const IdString, IdString> dff_comp_mode;
|
||||
};
|
||||
@ -488,7 +494,9 @@ enum
|
||||
lutram_0_z = 30, // start Z for the IOLOGIC bels
|
||||
vcc_0_z = 277, // virtual VCC bel Z
|
||||
gnd_0_z = 278, // virtual VSS bel Z
|
||||
osc_z = 280 // Z for the oscillator bels
|
||||
osc_z = 280, // Z for the oscillator bels
|
||||
bufs_0_z = 281, // Z for long wire buffer bel
|
||||
free_z = 289 // Must be the last, one can use z starting from this value, adjust accordingly.
|
||||
};
|
||||
}
|
||||
|
||||
|
||||
@ -77,6 +77,9 @@ std::unique_ptr<CellInfo> create_generic_cell(Context *ctx, IdString type, std::
|
||||
new_cell->addOutput(id_G);
|
||||
} else if (type == id_VCC) {
|
||||
new_cell->addOutput(id_V);
|
||||
} else if (type == id_BUFS) {
|
||||
new_cell->addInput(id_I);
|
||||
new_cell->addOutput(id_O);
|
||||
} else {
|
||||
log_error("unable to create generic cell of type %s\n", type.c_str(ctx));
|
||||
}
|
||||
|
||||
@ -679,6 +679,81 @@ X(IOBHS)
|
||||
X(IOBIS)
|
||||
X(IOBJS)
|
||||
|
||||
// long wires
|
||||
X(BUFS)
|
||||
X(BUFS0)
|
||||
X(BUFS1)
|
||||
X(BUFS2)
|
||||
X(BUFS3)
|
||||
X(BUFS4)
|
||||
X(BUFS5)
|
||||
X(BUFS6)
|
||||
X(BUFS7)
|
||||
X(LWT0)
|
||||
X(LWB0)
|
||||
X(LWT1)
|
||||
X(LWB1)
|
||||
X(LWT2)
|
||||
X(LWB2)
|
||||
X(LWT3)
|
||||
X(LWB3)
|
||||
X(LWT4)
|
||||
X(LWB4)
|
||||
X(LWT5)
|
||||
X(LWB5)
|
||||
X(LWT6)
|
||||
X(LWB6)
|
||||
X(LWT7)
|
||||
X(LWB7)
|
||||
X(LWSPINETL0)
|
||||
X(LWSPINETL1)
|
||||
X(LWSPINETL2)
|
||||
X(LWSPINETL3)
|
||||
X(LWSPINETL4)
|
||||
X(LWSPINETL5)
|
||||
X(LWSPINETL6)
|
||||
X(LWSPINETL7)
|
||||
X(LWSPINETR0)
|
||||
X(LWSPINETR1)
|
||||
X(LWSPINETR2)
|
||||
X(LWSPINETR3)
|
||||
X(LWSPINETR4)
|
||||
X(LWSPINETR5)
|
||||
X(LWSPINETR6)
|
||||
X(LWSPINETR7)
|
||||
X(LWSPINEBL0)
|
||||
X(LWSPINEBL1)
|
||||
X(LWSPINEBL2)
|
||||
X(LWSPINEBL3)
|
||||
X(LWSPINEBL4)
|
||||
X(LWSPINEBL5)
|
||||
X(LWSPINEBL6)
|
||||
X(LWSPINEBL7)
|
||||
X(LWSPINEBR0)
|
||||
X(LWSPINEBR1)
|
||||
X(LWSPINEBR2)
|
||||
X(LWSPINEBR3)
|
||||
X(LWSPINEBR4)
|
||||
X(LWSPINEBR5)
|
||||
X(LWSPINEBR6)
|
||||
X(LWSPINEBR7)
|
||||
X(LWI0)
|
||||
X(LWI1)
|
||||
X(LWI2)
|
||||
X(LWI3)
|
||||
X(LWI4)
|
||||
X(LWI5)
|
||||
X(LWI6)
|
||||
X(LWI7)
|
||||
X(LWO0)
|
||||
X(LWO1)
|
||||
X(LWO2)
|
||||
X(LWO3)
|
||||
X(LWO4)
|
||||
X(LWO5)
|
||||
X(LWO6)
|
||||
X(LWO7)
|
||||
|
||||
// IOLOGIC
|
||||
X(TX)
|
||||
X(XXX_VSS)
|
||||
@ -826,6 +901,11 @@ X(CENT_SPINE_PCLK)
|
||||
X(SPINE_TAP_PCLK)
|
||||
X(TAP_BRANCH_PCLK)
|
||||
X(BRANCH_PCLK)
|
||||
X(CENT_SPINE_SCLK)
|
||||
X(SPINE_TAP_SCLK_0)
|
||||
X(SPINE_TAP_SCLK_1)
|
||||
X(TAP_BRANCH_SCLK)
|
||||
X(BRANCH_SCLK)
|
||||
X(clksetpos)
|
||||
X(clkholdpos)
|
||||
X(clk_qpos)
|
||||
|
||||
@ -1033,9 +1033,11 @@ static void pack_io(Context *ctx)
|
||||
if (constr_bel != ci->attrs.end()) {
|
||||
constr_bel_name = constr_bel->second.as_string();
|
||||
}
|
||||
constr_bel = iob->attrs.find(id_BEL);
|
||||
if (constr_bel != iob->attrs.end()) {
|
||||
constr_bel_name = constr_bel->second.as_string();
|
||||
if (iob != nullptr) {
|
||||
constr_bel = iob->attrs.find(id_BEL);
|
||||
if (constr_bel != iob->attrs.end()) {
|
||||
constr_bel_name = constr_bel->second.as_string();
|
||||
}
|
||||
}
|
||||
if (!constr_bel_name.empty()) {
|
||||
BelId constr_bel = ctx->getBelByNameStr(constr_bel_name);
|
||||
|
||||
@ -95,7 +95,7 @@ bool Arch::isBelLocationValid(BelId bel) const
|
||||
}
|
||||
return logic_cells_compatible(bel_cells.data(), num_cells);
|
||||
} else {
|
||||
CellInfo *cell = getBoundBelCell(bel);
|
||||
const CellInfo *cell = getBoundBelCell(bel);
|
||||
if (cell == nullptr)
|
||||
return true;
|
||||
else if (cell->type == id_SB_IO) {
|
||||
@ -107,7 +107,7 @@ bool Arch::isBelLocationValid(BelId bel) const
|
||||
for (auto pin : getWireBelPins(wire)) {
|
||||
if (pin.pin == id_PLLOUT_A || pin.pin == id_PLLOUT_B) {
|
||||
// Is there a PLL there ?
|
||||
auto pll_cell = getBoundBelCell(pin.bel);
|
||||
const CellInfo *pll_cell = getBoundBelCell(pin.bel);
|
||||
if (pll_cell == nullptr)
|
||||
break;
|
||||
|
||||
@ -116,11 +116,11 @@ bool Arch::isBelLocationValid(BelId bel) const
|
||||
break;
|
||||
|
||||
// Is that SB_IO used at an input ?
|
||||
if ((cell->ports[id_D_IN_0].net == nullptr) && (cell->ports[id_D_IN_1].net == nullptr))
|
||||
if ((cell->getPort(id_D_IN_0) == nullptr) && (cell->getPort(id_D_IN_1) == nullptr))
|
||||
break;
|
||||
|
||||
// Are we perhaps a PAD INPUT Bel that can be placed here?
|
||||
if (pll_cell->attrs[id_BEL_PAD_INPUT] == getBelName(bel).str(getCtx()))
|
||||
if (str_or_default(pll_cell->attrs, id_BEL_PAD_INPUT, "") == getBelName(bel).str(getCtx()))
|
||||
return true;
|
||||
|
||||
// Conflict
|
||||
@ -144,7 +144,7 @@ bool Arch::isBelLocationValid(BelId bel) const
|
||||
} else {
|
||||
// Check LVDS IO is not placed at complement location
|
||||
BelId compBel = getBelByLocation(compLoc);
|
||||
CellInfo *compCell = getBoundBelCell(compBel);
|
||||
const CellInfo *compCell = getBoundBelCell(compBel);
|
||||
if (compCell && compCell->ioInfo.lvds)
|
||||
return false;
|
||||
|
||||
@ -161,10 +161,10 @@ bool Arch::isBelLocationValid(BelId bel) const
|
||||
_io_pintype_need_clk_en(cell->ioInfo.pintype),
|
||||
_io_pintype_need_clk_en(compCell->ioInfo.pintype),
|
||||
};
|
||||
NetInfo *nets[] = {
|
||||
cell->ports[id_INPUT_CLK].net, compCell->ports[id_INPUT_CLK].net,
|
||||
cell->ports[id_OUTPUT_CLK].net, compCell->ports[id_OUTPUT_CLK].net,
|
||||
cell->ports[id_CLOCK_ENABLE].net, compCell->ports[id_CLOCK_ENABLE].net,
|
||||
const NetInfo *nets[] = {
|
||||
cell->getPort(id_INPUT_CLK), compCell->getPort(id_INPUT_CLK),
|
||||
cell->getPort(id_OUTPUT_CLK), compCell->getPort(id_OUTPUT_CLK),
|
||||
cell->getPort(id_CLOCK_ENABLE), compCell->getPort(id_CLOCK_ENABLE),
|
||||
};
|
||||
|
||||
for (int i = 0; i < 6; i++)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user