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mistral: Carry fixes

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Signed-off-by: gatecat <gatecat@ds0.me>
This commit is contained in:
gatecat 2021-05-13 20:25:55 +01:00
parent 3d1bb4f1b2
commit 09a867310b
2 changed files with 16 additions and 3 deletions
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3
mistral/bitstream.cc
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@ -226,7 +226,8 @@ struct MistralBitgen
bool is_carry = (luts[0] && luts[0]->combInfo.is_carry) || (luts[1] && luts[1]->combInfo.is_carry);
if (is_carry)
cv->bmux_m_set(CycloneV::LAB, pos, CycloneV::ARITH_SEL, alm, CycloneV::ADDER);
if (is_carry && alm == 0 && luts[0]->combInfo.carry_start)
// The carry in/out enable bits
if (is_carry && alm == 0 && !luts[0]->combInfo.carry_start)
cv->bmux_b_set(CycloneV::LAB, pos, CycloneV::TTO_DIS, alm, true);
}

16
mistral/lab.cc
View File

@ -735,11 +735,23 @@ uint64_t Arch::compute_lut_mask(uint32_t lab, uint8_t alm)
int index = 0;
for (int k = 0; k < lut->combInfo.lut_input_count; k++) {
IdString log_pin = get_lut_pin(lut, k);
int init_idx = k;
if (arith) {
// D0 only affects lower half; D1 upper half
if (k == 3 && j >= 16)
continue;
if (k == 4) {
if (j < 16)
continue;
else
init_idx = 3;
}
}
CellPinState state = lut->get_pin_state(log_pin);
if (state == PIN_0)
continue;
else if (state == PIN_1)
index |= (1 << k);
index |= (1 << init_idx);
// Ignore if no associated physical pin
if (get_net_or_empty(lut, log_pin) == nullptr || lut->pin_data.at(log_pin).bel_pins.empty())
continue;
@ -749,7 +761,7 @@ uint64_t Arch::compute_lut_mask(uint32_t lab, uint8_t alm)
// Depermute physical pin
IdString phys_pin = lut->pin_data.at(log_pin).bel_pins.at(0);
if (get_phys_pin_val(alm_data.l6_mode, arith, j, phys_pin) != inverted)
index |= (1 << k);
index |= (1 << init_idx);
}
if ((init >> index) & 0x1) {
mask |= (1ULL << uint64_t(j + offset));