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[timing] More robust timing.dot

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This commit is contained in:
Eddie Hung 2019-01-29 10:41:36 -08:00
parent b01f012e86
commit 0c891bf90c
1 changed files with 11 additions and 5 deletions
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12
common/timing.cc
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@ -696,8 +696,11 @@ struct Timing
if (usr.cell != cell.second.get() || usr.port != port.first)
continue;
// And for each clock event, label node with event as well as max arrival time
for (const auto &i : net_data.at(port.second.net))
auto it = net_data.find(port.second.net);
if (it != net_data.end()) {
for (const auto &i : it->second)
f << "\\n" << (i.first.edge == RISING_EDGE ? "posedge" : "negedge") << " " << i.first.clock.str(ctx) << " @ " << i.second.max_arrival + ctx->getNetinfoRouteDelay(port.second.net, usr);
}
break;
}
f << "\"]" << std::endl;
@ -706,9 +709,12 @@ struct Timing
output_ports.push_back(port.first);
// Label port
f << "\t\t" << "\"" << cell.second->name.str(ctx) << "." << port.first.str(ctx) << "\" [label = \"" << port.first.str(ctx);
// A:d for each clock event, label node with event as well as max arrival time
for (const auto &i : net_data.at(port.second.net))
// And for each clock event, label node with event as well as max arrival time
auto it = net_data.find(port.second.net);
if (it != net_data.end()) {
for (const auto &i : it->second)
f << "\\n" << (i.first.edge == RISING_EDGE ? "posedge" : "negedge") << " " << i.first.clock.str(ctx) << " @ " << i.second.max_arrival;
}
f << "\"";
// IOB outputs are startpoints
if (ctx->getBelIOB(cell.second->bel))