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ice40: Add virtual padin wires for intoscs and GB_IOs

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Signed-off-by: David Shah <davey1576@gmail.com>
This commit is contained in:
David Shah 2018-07-19 12:04:35 +02:00
parent d221e90706
commit 0cb9ec0757
1 changed files with 14 additions and 1 deletions
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15
ice40/chipdb.py
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@ -159,7 +159,7 @@ def wire_type(name):
name = name.split('/')[-1] name = name.split('/')[-1]
wt = None wt = None
if name.startswith("glb_netwk_"): if name.startswith("glb_netwk_") or name.startswith("padin_"):
wt = "GLOBAL" wt = "GLOBAL"
elif name.startswith("D_IN_") or name.startswith("D_OUT_"): elif name.startswith("D_IN_") or name.startswith("D_OUT_"):
wt = "LOCAL" wt = "LOCAL"
@ -432,6 +432,19 @@ with open(args.filename, "r") as f:
extra_cells[mode[1]].append((line[0], (int(line[1]), int(line[2]), line[3]))) extra_cells[mode[1]].append((line[0], (int(line[1]), int(line[2]), line[3])))
continue continue
def add_wire(x, y, name):
global num_wires
wire_idx = num_wires
num_wires = num_wires + 1
wname = (x, y, name)
wire_names[wname] = wire_idx
wire_names_r[wire_idx] = wname
wire_segments[wire_idx] = dict()
# Add virtual padin wires
for i in range(8):
add_wire(0, 0, "padin_%d" % i)
def add_bel_input(bel, wire, port): def add_bel_input(bel, wire, port):
if wire not in wire_downhill_belports: if wire not in wire_downhill_belports:
wire_downhill_belports[wire] = set() wire_downhill_belports[wire] = set()