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Use RelSlice::ssize instead of cast-to-int throughout

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Signed-off-by: D. Shah <dave@ds0.me>
This commit is contained in:
D. Shah 2021-02-08 11:24:00 +00:00
parent 8b4163b77c
commit 0d444bfc6e
4 changed files with 23 additions and 23 deletions
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12
ecp5/arch.cc
View File

@ -223,7 +223,7 @@ BelId Arch::getBelByName(IdStringList name) const
loc.y = id_to_y.at(name[1]);
ret.location = loc;
const LocationTypePOD *loci = loc_info(ret);
for (int i = 0; i < int(loci->bel_data.size()); i++) {
for (int i = 0; i < loci->bel_data.ssize(); i++) {
if (std::strcmp(loci->bel_data[i].name.get(), name[2].c_str(this)) == 0) {
ret.index = i;
return ret;
@ -239,7 +239,7 @@ BelRange Arch::getBelsByTile(int x, int y) const
br.b.cursor_tile = y * chip_info->width + x;
br.e.cursor_tile = y * chip_info->width + x;
br.b.cursor_index = 0;
br.e.cursor_index = int(chip_info->locations[chip_info->location_type[br.b.cursor_tile]].bel_data.size()) - 1;
br.e.cursor_index = chip_info->locations[chip_info->location_type[br.b.cursor_tile]].bel_data.ssize() - 1;
br.b.chip = chip_info;
br.e.chip = chip_info;
if (br.e.cursor_index == -1)
@ -288,7 +288,7 @@ WireId Arch::getWireByName(IdStringList name) const
loc.y = id_to_y.at(name[1]);
ret.location = loc;
const LocationTypePOD *loci = loc_info(ret);
for (int i = 0; i < int(loci->wire_data.size()); i++) {
for (int i = 0; i < loci->wire_data.ssize(); i++) {
if (std::strcmp(loci->wire_data[i].name.get(), name[2].c_str(this)) == 0) {
ret.index = i;
return ret;
@ -314,7 +314,7 @@ PipId Arch::getPipByName(IdStringList name) const
loc.y = id_to_y.at(name[1]);
ret.location = loc;
const LocationTypePOD *loci = loc_info(ret);
for (int i = 0; i < int(loci->pip_data.size()); i++) {
for (int i = 0; i < loci->pip_data.ssize(); i++) {
PipId curr;
curr.location = loc;
curr.index = i;
@ -422,7 +422,7 @@ BelId Arch::getBelByLocation(Loc loc) const
if (loc.x >= chip_info->width || loc.y >= chip_info->height)
return BelId();
const LocationTypePOD &locI = chip_info->locations[chip_info->location_type[loc.y * chip_info->width + loc.x]];
for (int i = 0; i < int(locI.bel_data.size()); i++) {
for (int i = 0; i < locI.bel_data.ssize(); i++) {
if (locI.bel_data[i].z == loc.z) {
BelId bi;
bi.location.x = loc.x;
@ -1169,7 +1169,7 @@ BelId Arch::get_dqsbuf(bool dqsright, int dqsrow)
BelId bel;
bel.location.y = dqsrow;
bel.location.x = (dqsright ? (chip_info->width - 1) : 0);
for (int i = 0; i < int(loc_info(bel)->bel_data.size()); i++) {
for (int i = 0; i < loc_info(bel)->bel_data.ssize(); i++) {
auto &bd = loc_info(bel)->bel_data[i];
if (bd.type == id_DQSBUFM.index) {
bel.index = i;

8
ecp5/arch.h
View File

@ -188,7 +188,7 @@ struct BelIterator
{
cursor_index++;
while (cursor_tile < chip->num_tiles &&
cursor_index >= int(chip->locations[chip->location_type[cursor_tile]].bel_data.size())) {
cursor_index >= chip->locations[chip->location_type[cursor_tile]].bel_data.ssize()) {
cursor_index = 0;
cursor_tile++;
}
@ -266,7 +266,7 @@ struct WireIterator
{
cursor_index++;
while (cursor_tile < chip->num_tiles &&
cursor_index >= int(chip->locations[chip->location_type[cursor_tile]].wire_data.size())) {
cursor_index >= chip->locations[chip->location_type[cursor_tile]].wire_data.ssize()) {
cursor_index = 0;
cursor_tile++;
}
@ -318,7 +318,7 @@ struct AllPipIterator
{
cursor_index++;
while (cursor_tile < chip->num_tiles &&
cursor_index >= int(chip->locations[chip->location_type[cursor_tile]].pip_data.size())) {
cursor_index >= chip->locations[chip->location_type[cursor_tile]].pip_data.ssize()) {
cursor_index = 0;
cursor_tile++;
}
@ -703,7 +703,7 @@ struct Arch : BaseCtx
{
WireId wireId;
wireId.location = loc;
for (int i = 0; i < int(loc_info(wireId)->wire_data.size()); i++) {
for (int i = 0; i < loc_info(wireId)->wire_data.ssize(); i++) {
if (loc_info(wireId)->wire_data[i].name.get() == basename) {
wireId.index = i;
return wireId;

6
ice40/arch.cc
View File

@ -259,7 +259,7 @@ BelRange Arch::getBelsByTile(int x, int y) const
br.e.cursor = br.b.cursor;
if (br.e.cursor != -1) {
while (br.e.cursor < int(chip_info->bel_data.size()) && chip_info->bel_data[br.e.cursor].x == x &&
while (br.e.cursor < chip_info->bel_data.ssize() && chip_info->bel_data[br.e.cursor].x == x &&
chip_info->bel_data[br.e.cursor].y == y)
br.e.cursor++;
}
@ -376,7 +376,7 @@ WireId Arch::getWireByName(IdStringList name) const
WireId ret;
if (wire_by_name.empty()) {
for (int i = 0; i < int(chip_info->wire_data.size()); i++) {
for (int i = 0; i < chip_info->wire_data.ssize(); i++) {
WireId w;
w.index = i;
wire_by_name[getWireName(w)] = i;
@ -449,7 +449,7 @@ PipId Arch::getPipByName(IdStringList name) const
PipId ret;
if (pip_by_name.empty()) {
for (int i = 0; i < int(chip_info->pip_data.size()); i++) {
for (int i = 0; i < chip_info->pip_data.ssize(); i++) {
PipId pip;
pip.index = i;
pip_by_name[getPipName(pip)] = i;

20
nexus/arch.h
View File

@ -485,8 +485,8 @@ struct BelIterator
BelIterator operator++()
{
cursor_index++;
while (cursor_tile < int(chip->grid.size()) &&
cursor_index >= int(db->loctypes[chip->grid[cursor_tile].loc_type].bels.size())) {
while (cursor_tile < chip->grid.ssize() &&
cursor_index >= db->loctypes[chip->grid[cursor_tile].loc_type].bels.ssize()) {
cursor_index = 0;
cursor_tile++;
}
@ -539,12 +539,12 @@ struct WireIterator
// Iterate over nodes first, then tile wires that aren't nodes
do {
cursor_index++;
while (cursor_tile < int(chip->grid.size()) &&
cursor_index >= int(db->loctypes[chip->grid[cursor_tile].loc_type].wires.size())) {
while (cursor_tile < chip->grid.ssize() &&
cursor_index >= db->loctypes[chip->grid[cursor_tile].loc_type].wires.ssize()) {
cursor_index = 0;
cursor_tile++;
}
} while (cursor_tile < int(chip->grid.size()) && !chip_wire_is_primary(db, chip, cursor_tile, cursor_index));
} while (cursor_tile < chip->grid.ssize() && !chip_wire_is_primary(db, chip, cursor_tile, cursor_index));
return *this;
}
@ -595,7 +595,7 @@ struct NeighWireIterator
int32_t tile;
do
cursor++;
while (cursor < int(wn.neigh_wires.size()) &&
while (cursor < wn.neigh_wires.ssize() &&
((wn.neigh_wires[cursor].arc_flags & LOGICAL_TO_PRIMARY) ||
!chip_rel_tile(chip, baseWire.tile, wn.neigh_wires[cursor].rel_x, wn.neigh_wires[cursor].rel_y, tile)));
}
@ -637,8 +637,8 @@ struct AllPipIterator
AllPipIterator operator++()
{
cursor_index++;
while (cursor_tile < int(chip->grid.size()) &&
cursor_index >= int(db->loctypes[chip->grid[cursor_tile].loc_type].pips.size())) {
while (cursor_tile < chip->grid.ssize() &&
cursor_index >= db->loctypes[chip->grid[cursor_tile].loc_type].pips.ssize()) {
cursor_index = 0;
cursor_tile++;
}
@ -695,7 +695,7 @@ struct UpDownhillPipIterator
break;
WireId w = *twi;
auto &tile = db->loctypes[chip->grid[w.tile].loc_type];
if (cursor < int(uphill ? tile.wires[w.index].pips_uh.size() : tile.wires[w.index].pips_dh.size()))
if (cursor < (uphill ? tile.wires[w.index].pips_uh.ssize() : tile.wires[w.index].pips_dh.ssize()))
break;
++twi;
cursor = 0;
@ -734,7 +734,7 @@ struct WireBelPinIterator
while (true) {
if (!(twi != twi_end))
break;
if (cursor < int(chip_wire_data(db, chip, *twi).bel_pins.size()))
if (cursor < chip_wire_data(db, chip, *twi).bel_pins.ssize())
break;
++twi;
cursor = 0;