Add missing dependencies to CMake targets.
- Add additional targets useful for various situations. - Have counter test use common remap.v file. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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@ -314,6 +314,42 @@ function(generate_chipdb)
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chipdb-${device}-bin
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chipdb-${device}-bin
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)
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)
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add_custom_target(
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chipdb-${device}-bin-check-verbose
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COMMAND
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nextpnr-fpga_interchange
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--chipdb ${chipdb_bin}
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--package ${test_package}
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--test --verbose
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DEPENDS
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${chipdb_bin}
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chipdb-${device}-bin
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)
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add_custom_target(
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chipdb-${device}-bin-check-verbose2
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COMMAND
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nextpnr-fpga_interchange
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--chipdb ${chipdb_bin}
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--package ${test_package}
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--test --debug
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DEPENDS
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${chipdb_bin}
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chipdb-${device}-bin
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)
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add_custom_target(
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chipdb-${device}-bin-check-debug
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COMMAND gdb --args
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$<TARGET_FILE:nextpnr-fpga_interchange>
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--chipdb ${chipdb_bin}
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--package ${test_package}
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--test
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DEPENDS
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${chipdb_bin}
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chipdb-${device}-bin
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)
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add_custom_target(
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add_custom_target(
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chipdb-${device}-bin-check-test-data
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chipdb-${device}-bin-check-test-data
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COMMAND
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COMMAND
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@ -69,12 +69,12 @@ function(add_interchange_test)
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set(synth_json ${CMAKE_CURRENT_BINARY_DIR}/${name}.json)
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set(synth_json ${CMAKE_CURRENT_BINARY_DIR}/${name}.json)
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add_custom_command(
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add_custom_command(
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OUTPUT ${synth_json}
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OUTPUT ${synth_json}
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COMMAND
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COMMAND ${CMAKE_COMMAND} -E env
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SOURCES=${sources}
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SOURCES="${sources}"
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OUT_JSON=${synth_json}
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OUT_JSON=${synth_json}
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TECHMAP=${techmap}
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TECHMAP=${techmap}
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yosys -c ${tcl}
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yosys -c ${tcl}
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DEPENDS ${sources}
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DEPENDS ${sources} ${techmap} ${tcl}
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)
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)
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add_custom_target(test-${family}-${name}-json DEPENDS ${synth_json})
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add_custom_target(test-${family}-${name}-json DEPENDS ${synth_json})
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@ -134,12 +134,98 @@ function(add_interchange_test)
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--phys ${phys}
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--phys ${phys}
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--package ${package}
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--package ${package}
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DEPENDS
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DEPENDS
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nextpnr-fpga_interchange
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${netlist}
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${netlist}
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${xdc}
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${xdc}
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${chipdb_bin_target}
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${chipdb_bin_target}
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${chipdb_bin_loc}
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${chipdb_bin_loc}
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)
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)
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add_custom_target(
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test-${family}-${name}-phys-verbose
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COMMAND
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nextpnr-fpga_interchange
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--chipdb ${chipdb_bin_loc}
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--xdc ${xdc}
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--netlist ${netlist}
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--phys ${phys}
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--package ${package}
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--verbose
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DEPENDS
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${netlist}
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${xdc}
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${chipdb_bin_target}
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${chipdb_bin_loc}
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)
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add_custom_target(
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test-${family}-${name}-phys-verbose2
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COMMAND
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nextpnr-fpga_interchange
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--chipdb ${chipdb_bin_loc}
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--xdc ${xdc}
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--netlist ${netlist}
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--phys ${phys}
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--package ${package}
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--debug
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DEPENDS
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${netlist}
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${xdc}
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${chipdb_bin_target}
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${chipdb_bin_loc}
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)
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add_custom_target(
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test-${family}-${name}-phys-debug
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COMMAND gdb --args
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$<TARGET_FILE:nextpnr-fpga_interchange>
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--chipdb ${chipdb_bin_loc}
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--xdc ${xdc}
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--netlist ${netlist}
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--phys ${phys}
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--package ${package}
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DEPENDS
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${netlist}
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${xdc}
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${chipdb_bin_target}
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${chipdb_bin_loc}
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)
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add_custom_target(
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test-${family}-${name}-phys-valgrind
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COMMAND
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PYTHONMALLOC=malloc valgrind
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$<TARGET_FILE:nextpnr-fpga_interchange>
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--chipdb ${chipdb_bin_loc}
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--xdc ${xdc}
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--netlist ${netlist}
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--phys ${phys}
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--package ${package}
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DEPENDS
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${netlist}
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${xdc}
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${chipdb_bin_target}
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${chipdb_bin_loc}
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)
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if(PROFILER)
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add_custom_target(
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test-${family}-${name}-phys-profile
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COMMAND CPUPROFILE=${name}.prof
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$<TARGET_FILE:nextpnr-fpga_interchange>
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--chipdb ${chipdb_bin_loc}
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--xdc ${xdc}
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--netlist ${netlist}
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--phys ${phys}
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--package ${package}
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DEPENDS
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${netlist}
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${xdc}
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${chipdb_bin_target}
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${chipdb_bin_loc}
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)
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endif()
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add_custom_target(test-${family}-${name}-phys DEPENDS ${phys})
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add_custom_target(test-${family}-${name}-phys DEPENDS ${phys})
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# Physical Netlist YAML
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# Physical Netlist YAML
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@ -6,7 +6,7 @@ add_interchange_test(
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tcl run.tcl
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tcl run.tcl
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xdc counter_basys3.xdc
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xdc counter_basys3.xdc
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sources counter.v
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sources counter.v
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techmap remap.v
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techmap ../../remap.v
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)
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)
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add_interchange_test(
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add_interchange_test(
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@ -17,5 +17,5 @@ add_interchange_test(
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tcl run.tcl
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tcl run.tcl
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xdc counter_arty.xdc
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xdc counter_arty.xdc
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sources counter.v
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sources counter.v
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techmap remap.v
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techmap ../../remap.v
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)
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)
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@ -1,11 +0,0 @@
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module INV(input I, output O);
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LUT1 #(.INIT(2'b01)) _TECHMAP_REPLACE_ (.I0(I), .O(O));
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endmodule
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module BUF(input I, output O);
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LUT1 #(.INIT(2'b10)) _TECHMAP_REPLACE_ (.I0(I), .O(O));
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endmodule
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@ -9,7 +9,7 @@ set(RAPIDWRIGHT_PATH $ENV{HOME}/RapidWright CACHE PATH "Path to RapidWright")
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set(INVOKE_RAPIDWRIGHT ${RAPIDWRIGHT_PATH}/scripts/invoke_rapidwright.sh CACHE PATH "Path to RapidWright invocation script")
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set(INVOKE_RAPIDWRIGHT ${RAPIDWRIGHT_PATH}/scripts/invoke_rapidwright.sh CACHE PATH "Path to RapidWright invocation script")
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# FIXME: Make patch data available in the python package and remove this cached var
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# FIXME: Make patch data available in the python package and remove this cached var
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set(PYTHON_INTERCHANGE_PATH $ENV{HOME}/python-fpga-interchange CACHE PATH "Path to the FPGA interchange python library")
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set(PYTHON_INTERCHANGE_PATH $ENV{HOME}/python-fpga-interchange CACHE PATH "Path to the FPGA interchange python library")
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set(INTERCHANGE_SCHEMA_PATH $ENV{HOME}/fpga_interchange_schema CACHE PATH "Path to the FPGA interchange schema dir")
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set(INTERCHANGE_SCHEMA_PATH ${PROJECT_SOURCE_DIR}/3rdparty/fpga-interchange-schema/interchange CACHE PATH "Path to the FPGA interchange schema dir")
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add_subdirectory(3rdparty/fpga-interchange-schema/cmake/cxx_static)
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add_subdirectory(3rdparty/fpga-interchange-schema/cmake/cxx_static)
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