commit
0f4166fedb
@ -205,9 +205,9 @@ struct RegionPlug : PseudoCell
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WireId getPortWire(IdString port) const override { return port_wires.at(port); }
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// TODO: partial reconfiguration region timing
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bool getDelay(IdString fromPort, IdString toPort, DelayQuad &delay) const { return false; }
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TimingPortClass getPortTimingClass(IdString port, int &clockInfoCount) const { return TMG_IGNORE; }
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virtual TimingClockingInfo getPortClockingInfo(IdString port, int index) const { return TimingClockingInfo{}; }
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bool getDelay(IdString fromPort, IdString toPort, DelayQuad &delay) const override { return false; }
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TimingPortClass getPortTimingClass(IdString port, int &clockInfoCount) const override { return TMG_IGNORE; }
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TimingClockingInfo getPortClockingInfo(IdString port, int index) const override { return TimingClockingInfo{}; }
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dict<IdString, WireId> port_wires;
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Loc loc;
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@ -373,8 +373,7 @@ struct Router2
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return base_cost * hist_cost * present_cost / (1 + (source_uses * crit_weight)) + bias_cost;
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}
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float get_togo_cost(NetInfo *net, store_index<PortRef> user, int wire, WireId src_sink, float crit_weight,
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bool bwd = false)
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float get_togo_cost(NetInfo *net, store_index<PortRef> user, int wire, WireId src_sink, bool bwd, float crit_weight)
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{
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auto &nd = nets.at(net->udata);
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auto &wd = flat_wires[wire];
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