Merge pull request #59 from daveshah1/ecp5_timing
Simple timing model for ECP5
This commit is contained in:
David Shah
GitHub
commit
0f86d082e5
146
ecp5/arch.cc
146
ecp5/arch.cc
@ -46,13 +46,16 @@ static std::tuple<int, int, std::string> split_identifier_name(const std::string
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void IdString::initialize_arch(const BaseCtx *ctx)
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{
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#define X(t) initialize_add(ctx, #t, ID_##t);
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#include "constids.inc"
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#undef X
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}
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// -----------------------------------------------------------------------
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static const ChipInfoPOD *get_chip_info(const RelPtr<ChipInfoPOD> *ptr) { return ptr->get(); }
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static const ChipInfoPOD *get_chip_info(const RelPtr<ChipInfoPOD> *ptr)
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{ return ptr->get(); }
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#if defined(_MSC_VER)
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void load_chipdb();
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@ -369,7 +372,7 @@ BelId Arch::getBelByLocation(Loc loc) const
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delay_t Arch::estimateDelay(WireId src, WireId dst) const
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{
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return 50 * (abs(src.location.x - dst.location.x) + abs(src.location.y - dst.location.y));
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return 100 * (abs(src.location.x - dst.location.x) + abs(src.location.y - dst.location.y));
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}
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delay_t Arch::predictDelay(const NetInfo *net_info, const PortRef &sink) const
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@ -378,16 +381,19 @@ delay_t Arch::predictDelay(const NetInfo *net_info, const PortRef &sink) const
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auto driver_loc = getBelLocation(driver.cell->bel);
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auto sink_loc = getBelLocation(sink.cell->bel);
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return 50 * (abs(driver_loc.x - sink_loc.x) + abs(driver_loc.y - sink_loc.y));
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return 100 * (abs(driver_loc.x - sink_loc.x) + abs(driver_loc.y - sink_loc.y));
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}
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bool Arch::getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t &budget) const { return false; }
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bool Arch::getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t &budget) const
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{ return false; }
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// -----------------------------------------------------------------------
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bool Arch::place() { return placer1(getCtx(), Placer1Cfg(getCtx())); }
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bool Arch::place()
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{ return placer1(getCtx(), Placer1Cfg(getCtx())); }
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bool Arch::route() { return router1(getCtx(), Router1Cfg(getCtx())); }
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bool Arch::route()
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{ return router1(getCtx(), Router1Cfg(getCtx())); }
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// -----------------------------------------------------------------------
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@ -408,8 +414,8 @@ std::vector<GraphicElement> Arch::getDecalGraphics(DecalId decal) const
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el.style = decal.active ? GraphicElement::STYLE_ACTIVE : GraphicElement::STYLE_INACTIVE;
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el.x1 = bel.location.x + logic_cell_x1;
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el.x2 = bel.location.x + logic_cell_x2;
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el.y1 = bel.location.y + logic_cell_y1 + (z)*logic_cell_pitch;
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el.y2 = bel.location.y + logic_cell_y2 + (z)*logic_cell_pitch;
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el.y1 = bel.location.y + logic_cell_y1 + (z) * logic_cell_pitch;
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el.y2 = bel.location.y + logic_cell_y2 + (z) * logic_cell_pitch;
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ret.push_back(el);
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}
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@ -438,22 +444,136 @@ DecalXY Arch::getBelDecal(BelId bel) const
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return decalxy;
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}
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DecalXY Arch::getWireDecal(WireId wire) const { return {}; }
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DecalXY Arch::getWireDecal(WireId wire) const
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{ return {}; }
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DecalXY Arch::getPipDecal(PipId pip) const { return {}; };
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DecalXY Arch::getPipDecal(PipId pip) const
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{ return {}; };
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DecalXY Arch::getGroupDecal(GroupId pip) const { return {}; };
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DecalXY Arch::getGroupDecal(GroupId pip) const
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{ return {}; };
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// -----------------------------------------------------------------------
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bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayInfo &delay) const
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{
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return false;
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// Data for -8 grade
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if (cell->type == id_TRELLIS_SLICE) {
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bool has_carry = str_or_default(cell->params, id("MODE"), "LOGIC") == "CCU2";
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if (fromPort == id_A0 || fromPort == id_B0 || fromPort == id_C0 || fromPort == id_D0) {
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if (toPort == id_F0) {
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delay.delay = 180;
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return true;
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} else if (has_carry && toPort == id_F1) {
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delay.delay = 500;
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return true;
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} else if (has_carry && toPort == id_FCO) {
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delay.delay = 355;
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return true;
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} else if (toPort == id_OFX0) {
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delay.delay = 306;
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return true;
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}
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}
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if (fromPort == id_A1 || fromPort == id_B1 || fromPort == id_C1 || fromPort == id_D1) {
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if (toPort == id_F1) {
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delay.delay = 180;
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return true;
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} else if (has_carry && toPort == id_FCO) {
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delay.delay = 355;
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return true;
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} else if (toPort == id_OFX0) {
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delay.delay = 306;
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return true;
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}
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}
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if (has_carry && fromPort == id_FCI) {
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if (toPort == id_F0) {
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delay.delay = 328;
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return true;
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} else if (toPort == id_F1) {
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delay.delay = 349;
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return true;
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} else if (toPort == id_FCO) {
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delay.delay = 56;
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return true;
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}
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}
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if (fromPort == id_CLK && (toPort == id_Q0 || toPort == id_Q1)) {
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delay.delay = 395;
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return true;
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}
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if (fromPort == id_M0 && toPort == id_OFX0) {
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delay.delay = 193;
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return true;
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}
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if (fromPort == id_WCK && (toPort == id_F0 || toPort == id_F1)) {
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delay.delay = 717;
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return true;
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}
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if ((fromPort == id_A0 && toPort == id_WADO3) ||
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(fromPort == id_A1 && toPort == id_WDO1) ||
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(fromPort == id_B0 && toPort == id_WADO1) ||
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(fromPort == id_B1 && toPort == id_WDO3) ||
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(fromPort == id_C0 && toPort == id_WADO2) ||
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(fromPort == id_C1 && toPort == id_WDO0) ||
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(fromPort == id_D0 && toPort == id_WADO0) ||
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(fromPort == id_D1 && toPort == id_WDO2)) {
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delay.delay = 0;
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return true;
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}
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return false;
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} else {
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return false;
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}
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}
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TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, IdString &clockPort) const
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{
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return TMG_IGNORE;
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if (cell->type == id_TRELLIS_SLICE) {
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int sd0 = int_or_default(cell->params, id("REG0_SD"), 0), sd1 = int_or_default(cell->params, id("REG1_SD"), 0);
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if (port == id_CLK || port == id_WCK)
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return TMG_CLOCK_INPUT;
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if (port == id_A0 || port == id_A1 || port == id_B0 || port == id_B1 || port == id_C0 || port == id_C1 ||
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port == id_D0 || port == id_D1 || port == id_FCI || port == id_FXA || port == id_FXB)
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return TMG_COMB_INPUT;
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if (port == id_F0 || port == id_F1 || port == id_FCO || port == id_OFX0 || port == id_OFX1)
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return TMG_COMB_OUTPUT;
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if (port == id_DI0 || port == id_DI1 || port == id_CE || port == id_LSR || (sd0 == 1 && port == id_M0) || (sd1 == 1 && port == id_M1)) {
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clockPort = id_CLK;
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return TMG_REGISTER_INPUT;
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}
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if (port == id_M0 || port == id_M1)
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return TMG_COMB_INPUT;
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if (port == id_Q0 || port == id_Q1) {
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clockPort = id_CLK;
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return TMG_REGISTER_OUTPUT;
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}
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if (port == id_WDO0 || port == id_WDO1 || port == id_WDO2 || port == id_WDO3 || port == id_WADO0 || port == id_WADO1 || port == id_WADO2 || port == id_WADO3)
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return TMG_COMB_OUTPUT;
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if (port == id_WD0 || port == id_WD1 || port == id_WAD0 || port == id_WAD1 || port == id_WAD2 || port == id_WAD3 || port == id_WRE) {
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clockPort = id_WCK;
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return TMG_REGISTER_INPUT;
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}
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NPNR_ASSERT_FALSE_STR("no timing type for slice port '" + port.str(this) + "'");
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} else if (cell->type == id_TRELLIS_IO) {
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if (port == id_T || port == id_I)
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return TMG_ENDPOINT;
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if (port == id_O)
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return TMG_STARTPOINT;
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return TMG_IGNORE;
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} else {
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NPNR_ASSERT_FALSE_STR("no timing data for cell type '" + cell->type.str(this) + "'");
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}
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}
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std::vector<std::pair<std::string, std::string>> Arch::getTilesAtLocation(int row, int col)
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@ -745,7 +745,7 @@ struct Arch : BaseCtx
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{
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DelayInfo delay;
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NPNR_ASSERT(pip != PipId());
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delay.delay = locInfo(pip)->pip_data[pip.index].delay * 100;
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delay.delay = locInfo(pip)->pip_data[pip.index].delay;
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return delay;
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}
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@ -130,11 +130,54 @@ def process_loc_globals(chip):
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tapdrv = chip.global_data.get_tap_driver(y, x)
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global_data[x, y] = (quadrants.index(quad), int(tapdrv.dir), tapdrv.col)
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def get_wire_type(name):
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if "H00" in name or "V00" in name:
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return "X0"
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if "H01" in name or "V01" in name:
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return "X1"
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if "H02" in name or "V02" in name:
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return "X2"
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if "H06" in name or "V06" in name:
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return "X6"
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if "_SLICE" in name or "_EBR" in name:
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return "SLICE"
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return "LOCAL"
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def get_pip_delay(wire_from, wire_to):
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# ECP5 timings WIP!!!
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type_from = get_wire_type(wire_from)
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type_to = get_wire_type(wire_to)
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if type_from == "X2" and type_to == "X2":
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return 170
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if type_from == "SLICE" or type_to == "SLICE":
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return 205
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if type_from in ("LOCAL", "X0") and type_to in ("X1", "X2", "X6"):
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return 90
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if type_from == "X6" or type_to == "X6":
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return 200
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if type_from in ("X1", "X2", "X6") and type_to in ("LOCAL", "X0"):
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return 90
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return 100
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def write_database(dev_name, chip, ddrg, endianness):
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def write_loc(loc, sym_name):
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bba.u16(loc.x, "%s.x" % sym_name)
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bba.u16(loc.y, "%s.y" % sym_name)
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loctypes = list([_.key() for _ in ddrg.locationTypes])
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loc_with_type = {}
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for y in range(0, max_row+1):
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for x in range(0, max_col+1):
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loc_with_type[loctypes.index(ddrg.typeAtLocation[pytrellis.Location(x, y)])] = (x, y)
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def get_wire_name(arc_loctype, rel, idx):
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loc = loc_with_type[arc_loctype]
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lt = ddrg.typeAtLocation[pytrellis.Location(loc[0] + rel.x, loc[1] + rel.y)]
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wire = ddrg.locationTypes[lt].wires[idx]
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return ddrg.to_str(wire.name)
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bba = BinaryBlobAssembler()
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bba.pre('#include "nextpnr.h"')
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bba.pre('NEXTPNR_NAMESPACE_BEGIN')
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@ -142,7 +185,6 @@ def write_database(dev_name, chip, ddrg, endianness):
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bba.push("chipdb_blob_%s" % dev_name)
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bba.r("chip_info", "chip_info")
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loctypes = list([_.key() for _ in ddrg.locationTypes])
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for idx in range(len(loctypes)):
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loctype = ddrg.locationTypes[loctypes[idx]]
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@ -153,7 +195,7 @@ def write_database(dev_name, chip, ddrg, endianness):
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write_loc(arc.sinkWire.rel, "dst")
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bba.u32(arc.srcWire.id, "src_idx")
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bba.u32(arc.sinkWire.id, "dst_idx")
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bba.u32(arc.delay, "delay") # TODO:delay
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bba.u32(get_pip_delay(get_wire_name(idx, arc.srcWire.rel, arc.srcWire.id), get_wire_name(idx, arc.sinkWire.rel, arc.sinkWire.id)), "delay") # TODO:delay
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bba.u16(get_tiletype_index(ddrg.to_str(arc.tiletype)), "tile_type")
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bba.u8(int(arc.cls), "pip_type")
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bba.u8(0, "padding")
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