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Timing: Fix combinational paths through all ports (#1175)

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Fixes https://github.com/YosysHQ/nextpnr/issues/1174
This commit is contained in:
Rowan Goemans 2023-06-12 10:25:01 +02:00 committed by GitHub
parent 5b958c4d80
commit 0f947ee693
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GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 22 additions and 26 deletions
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48
common/kernel/timing.cc
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@ -113,23 +113,21 @@ void TimingAnalyser::get_cell_delays()
info.edge); info.edge);
} }
} }
// Combinational delays through cell
else if (cls == TMG_COMB_INPUT) {
for (auto &other_port : ci->ports) {
auto &op = other_port.second;
// ignore dangling ports and non-outputs
if (op.net == nullptr || op.type != PORT_OUT)
continue;
DelayQuad delay;
bool is_path = ctx->getCellDelay(ci, name, other_port.first, delay);
if (is_path)
pd.cell_arcs.emplace_back(CellArc::COMBINATIONAL, other_port.first, delay);
}
}
// asynchronous endpoint // asynchronous endpoint
else if (cls == TMG_ENDPOINT) { else if (cls == TMG_ENDPOINT) {
pd.cell_arcs.emplace_back(CellArc::ENDPOINT, async_clk_key.key.clock, DelayQuad {}); pd.cell_arcs.emplace_back(CellArc::ENDPOINT, async_clk_key.key.clock, DelayQuad {});
} }
// Combinational delays through cell
for (auto &other_port : ci->ports) {
auto &op = other_port.second;
// ignore dangling ports and non-outputs
if (op.net == nullptr || op.type != PORT_OUT)
continue;
DelayQuad delay;
bool is_path = ctx->getCellDelay(ci, name, other_port.first, delay);
if (is_path)
pd.cell_arcs.emplace_back(CellArc::COMBINATIONAL, other_port.first, delay);
}
} else if (pi.type == PORT_OUT) { } else if (pi.type == PORT_OUT) {
// Output ports might have clk-to-q relationships // Output ports might have clk-to-q relationships
if (cls == TMG_REGISTER_OUTPUT) { if (cls == TMG_REGISTER_OUTPUT) {
@ -140,23 +138,21 @@ void TimingAnalyser::get_cell_delays()
pd.cell_arcs.emplace_back(CellArc::CLK_TO_Q, info.clock_port, info.clockToQ, info.edge); pd.cell_arcs.emplace_back(CellArc::CLK_TO_Q, info.clock_port, info.clockToQ, info.edge);
} }
} }
// Combinational delays through cell
else if (cls == TMG_COMB_OUTPUT) {
for (auto &other_port : ci->ports) {
auto &op = other_port.second;
// ignore dangling ports and non-inputs
if (op.net == nullptr || op.type != PORT_IN)
continue;
DelayQuad delay;
bool is_path = ctx->getCellDelay(ci, other_port.first, name, delay);
if (is_path)
pd.cell_arcs.emplace_back(CellArc::COMBINATIONAL, other_port.first, delay);
}
}
// Asynchronous startpoint // Asynchronous startpoint
else if (cls == TMG_STARTPOINT) { else if (cls == TMG_STARTPOINT) {
pd.cell_arcs.emplace_back(CellArc::STARTPOINT, async_clk_key.key.clock, DelayQuad {}); pd.cell_arcs.emplace_back(CellArc::STARTPOINT, async_clk_key.key.clock, DelayQuad {});
} }
// Combinational delays through cell
for (auto &other_port : ci->ports) {
auto &op = other_port.second;
// ignore dangling ports and non-inputs
if (op.net == nullptr || op.type != PORT_IN)
continue;
DelayQuad delay;
bool is_path = ctx->getCellDelay(ci, other_port.first, name, delay);
if (is_path)
pd.cell_arcs.emplace_back(CellArc::COMBINATIONAL, other_port.first, delay);
}
} }
} }
} }