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Assign proper pips

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This commit is contained in:
Miodrag Milanovic 2018-07-21 15:08:49 +02:00
parent 3afcd812c9
commit 13339c0355
1 changed files with 27 additions and 9 deletions
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24
ice40/bitstream.cc
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@ -467,9 +467,8 @@ void write_asc(const Context *ctx, std::ostream &out)
set_config(ti, config.at(y).at(x), set_config(ti, config.at(y).at(x),
"Cascade.IPCON_LC0" + std::to_string(lc_idx) + "_inmux02_5", true); "Cascade.IPCON_LC0" + std::to_string(lc_idx) + "_inmux02_5", true);
else else
set_config(ti, config.at(y).at(x), set_config(ti, config.at(y).at(x), "Cascade.MULT" + std::to_string(int(tile - TILE_DSP0)) +
"Cascade.MULT" + std::to_string(int(tile - TILE_DSP0)) + "_LC0" + "_LC0" + std::to_string(lc_idx) + "_inmux02_5",
std::to_string(lc_idx) + "_inmux02_5",
true); true);
} }
} }
@ -634,6 +633,25 @@ bool read_asc(Context *ctx, std::istream &in)
} }
} }
read_config(ctx, in, config); read_config(ctx, in, config);
// Set pips
for (auto pip : ctx->getPips()) {
const PipInfoPOD &pi = ci.pip_data[pip.index];
const SwitchInfoPOD &swi = bi.switches[pi.switch_index];
bool isUsed = true;
for (int i = 0; i < swi.num_bits; i++) {
bool val = (pi.switch_mask & (1 << ((swi.num_bits - 1) - i))) != 0;
int8_t cbit = config.at(swi.y).at(swi.x).at(swi.cbits[i].row).at(swi.cbits[i].col);
isUsed &= !(bool(cbit) ^ val);
}
if (isUsed) {
IdString net = ctx->wire_to_net[pi.dst];
WireId wire;
wire.index = pi.dst;
ctx->unbindWire(wire);
ctx->bindPip(pip, net, STRENGTH_WEAK);
}
}
return true; return true;
} catch (log_execution_error_exception) { } catch (log_execution_error_exception) {
return false; return false;