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Merge pull request #1028 from YosysHQ/gatecat/router2-reserve-src

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router2: Reserve source wire, too; ice40 fixes
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myrtle 2022-09-20 14:37:55 +02:00 committed by GitHub
commit 136ab81cbd
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2 changed files with 17 additions and 0 deletions
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7
common/route/router2.cc
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@ -453,6 +453,13 @@ struct Router2
{ {
bool did_something = false; bool did_something = false;
WireId src = ctx->getNetinfoSourceWire(net); WireId src = ctx->getNetinfoSourceWire(net);
{
auto &src_wd = wire_data(src);
if (src_wd.reserved_net != -1 && src_wd.reserved_net != net->udata)
log_error("attempting to reserve src wire '%s' for nets '%s' and '%s'\n", ctx->nameOfWire(src),
ctx->nameOf(nets_by_udata.at(src_wd.reserved_net)), ctx->nameOf(net));
src_wd.reserved_net = net->udata;
}
auto &usr = net->users.at(i); auto &usr = net->users.at(i);
for (auto sink : ctx->getNetinfoSinkWires(net, usr)) { for (auto sink : ctx->getNetinfoSinkWires(net, usr)) {
pool<WireId> rsv; pool<WireId> rsv;

10
ice40/arch.h
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@ -680,6 +680,16 @@ struct Arch : BaseArch<ArchRanges>
return switches_locked[pi.switch_index] == WireId(); return switches_locked[pi.switch_index] == WireId();
} }
bool checkPipAvailForNet(PipId pip, NetInfo *net) const override
{
if (ice40_pip_hard_unavail(pip))
return false;
auto &pi = chip_info->pip_data[pip.index];
auto swl = switches_locked[pi.switch_index];
return swl == WireId() || (swl == getPipDstWire(pip) && wire_to_net[swl.index] == net);
}
NetInfo *getBoundPipNet(PipId pip) const override NetInfo *getBoundPipNet(PipId pip) const override
{ {
NPNR_ASSERT(pip != PipId()); NPNR_ASSERT(pip != PipId());