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Adding stubs for delay annotation and cell timing lookup

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Signed-off-by: David Shah <davey1576@gmail.com>
This commit is contained in:
David Shah 2018-06-20 11:44:28 +02:00
parent 5d1b87b0a4
commit 1436ae21a2
8 changed files with 119 additions and 6 deletions
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2
common/nextpnr.h
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@ -17,13 +17,13 @@
*
*/
#include <algorithm>
#include <assert.h>
#include <stdint.h>
#include <string>
#include <unordered_map>
#include <unordered_set>
#include <vector>
#include <algorithm>
#ifndef NEXTPNR_H
#define NEXTPNR_H

29
common/timing.cc Normal file
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@ -0,0 +1,29 @@
/*
* nextpnr -- Next Generation Place and Route
*
* Copyright (C) 2018 David Shah <david@symbioticeda.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
#include "timing.h"
#include "log.h"
#include <unordered_map>
#include <utility>
#include <algorithm>
void assign_budget(Context *ctx, float default_clock = 12e6)
{
}

28
common/timing.h Normal file
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@ -0,0 +1,28 @@
/*
* nextpnr -- Next Generation Place and Route
*
* Copyright (C) 2018 David Shah <david@symbioticeda.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
#ifndef TIMING_H
#define TIMING_H
#include "nextpnr.h"
// Assign "budget" values for all user ports in the design
void assign_budget(Context *ctx, float default_clock = 12e6);
#endif TIMING_H

18
dummy/arch.cc
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@ -176,4 +176,22 @@ std::vector<GraphicElement> Arch::getPipGraphics(PipId pip) const
return ret;
}
// ---------------------------------------------------------------
delay_t Arch::getCellDelay(const CellInfo *cell, IdString fromPort,
IdString toPort) const
{
return 0;
}
IdString Arch::getPortClock(const CellInfo *cell, IdString port) const
{
return IdString();
}
bool Arch::isClockPort(const CellInfo *cell, IdString port) const
{
return false;
}
NEXTPNR_NAMESPACE_END

7
dummy/arch.h
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@ -32,7 +32,9 @@ struct DelayInfo
delay_t delay = 0;
delay_t raiseDelay() const { return delay; }
delay_t fallDelay() const { return delay; }
delay_t avgDelay() const { return delay; }
DelayInfo operator+(const DelayInfo &other) const
@ -131,6 +133,11 @@ struct Arch : BaseCtx
std::unordered_set<BelId> belGraphicsReload;
std::unordered_set<WireId> wireGraphicsReload;
std::unordered_set<PipId> pipGraphicsReload;
delay_t getCellDelay(const CellInfo *cell, IdString fromPort,
IdString toPort) const;
IdString getPortClock(const CellInfo *cell, IdString port) const;
bool isClockPort(const CellInfo *cell, IdString port) const;
};
NEXTPNR_NAMESPACE_END

2
frontend/json/jsonparse.cc
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@ -26,8 +26,8 @@
#include <fstream>
#include <iostream>
#include <log.h>
#include <string>
#include <map>
#include <string>
#include "nextpnr.h"
NEXTPNR_NAMESPACE_BEGIN

21
ice40/arch.cc
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@ -416,4 +416,25 @@ std::vector<GraphicElement> Arch::getPipGraphics(PipId pip) const
return ret;
}
// -----------------------------------------------------------------------
delay_t Arch::getCellDelay(const CellInfo *cell, IdString fromPort,
IdString toPort) const
{
// TODO
return 0;
}
IdString Arch::getPortClock(const CellInfo *cell, IdString port) const
{
// TODO
return IdString();
}
bool Arch::isClockPort(const CellInfo *cell, IdString port) const
{
// TODO
return false;
}
NEXTPNR_NAMESPACE_END

10
ice40/arch.h
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@ -755,6 +755,16 @@ struct Arch : BaseCtx
std::unordered_set<BelId> belGraphicsReload;
std::unordered_set<WireId> wireGraphicsReload;
std::unordered_set<PipId> pipGraphicsReload;
// -------------------------------------------------
// Get the delay through a cell from one port to another
delay_t getCellDelay(const CellInfo *cell, IdString fromPort,
IdString toPort) const;
// Get the associated clock to a port, or empty if the port is combinational
IdString getPortClock(const CellInfo *cell, IdString port) const;
// Return true if a port is a clock
bool isClockPort(const CellInfo *cell, IdString port) const;
};
NEXTPNR_NAMESPACE_END