diff --git a/common/nextpnr.h b/common/nextpnr.h
index 3ba4f3b3..4a1aaac1 100644
--- a/common/nextpnr.h
+++ b/common/nextpnr.h
@@ -273,6 +273,16 @@ struct CellInfo : ArchCellInfo
 
     // cell_port -> bel_pin
     std::unordered_map<IdString, IdString> pins;
+
+    // placement constraints
+    CellInfo *constr_parent;
+    std::vector<CellInfo*> constr_children;
+    const int UNCONSTR = INT_MIN;
+    int constr_x = UNCONSTR; // this.x - parent.x
+    int constr_y = UNCONSTR; // this.y - parent.y
+    int constr_z = UNCONSTR; // this.z - parent.z
+    bool constr_abs_z = false; // parent.z := 0
+    // parent.[xyz] := 0 when (constr_parent == nullptr)
 };
 
 struct DeterministicRNG
diff --git a/ecp5/arch_pybindings.cc b/ecp5/arch_pybindings.cc
index 8310c3a1..c261c3ec 100644
--- a/ecp5/arch_pybindings.cc
+++ b/ecp5/arch_pybindings.cc
@@ -2,7 +2,7 @@
  *  nextpnr -- Next Generation Place and Route
  *
  *  Copyright (C) 2018  Clifford Wolf <clifford@symbioticeda.com>
- *  Copyright (C) 2018  David Shah <dave@ds0.me>
+ *  Copyright (C) 2018  David Shah <david@symbioticeda.com>
  *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
@@ -20,13 +20,132 @@
 
 #ifndef NO_PYTHON
 
+#include "arch_pybindings.h"
 #include "nextpnr.h"
 #include "pybindings.h"
 
 NEXTPNR_NAMESPACE_BEGIN
 
-void arch_wrap_python() {}
+void arch_wrap_python()
+{
+    using namespace PythonConversion;
+    class_<ArchArgs>("ArchArgs").def_readwrite("type", &ArchArgs::type);
+
+    class_<BelId>("BelId").def_readwrite("index", &BelId::index);
+
+    class_<WireId>("WireId").def_readwrite("index", &WireId::index);
+
+    class_<PipId>("PipId").def_readwrite("index", &PipId::index);
+
+    class_<BelPin>("BelPin").def_readwrite("bel", &BelPin::bel).def_readwrite("pin", &BelPin::pin);
+
+    enum_<PortPin>("PortPin")
+#define X(t) .value("PIN_" #t, PIN_##t)
+
+#include "portpins.inc"
+            ;
+#undef X
+
+    auto arch_cls = class_<Arch, Arch *, bases<BaseCtx>, boost::noncopyable>("Arch", init<ArchArgs>());
+    auto ctx_cls = class_<Context, Context *, bases<Arch>, boost::noncopyable>("Context", no_init)
+                           .def("checksum", &Context::checksum)
+                           .def("pack", &Context::pack)
+                           .def("place", &Context::place)
+                           .def("route", &Context::route);
+
+    fn_wrapper_1a<Context, decltype(&Context::getBelType), &Context::getBelType, conv_to_str<BelType>,
+                  conv_from_str<BelId>>::def_wrap(ctx_cls, "getBelType");
+    fn_wrapper_1a<Context, decltype(&Context::checkBelAvail), &Context::checkBelAvail, pass_through<bool>,
+                  conv_from_str<BelId>>::def_wrap(ctx_cls, "checkBelAvail");
+    fn_wrapper_1a<Context, decltype(&Context::getBelChecksum), &Context::getBelChecksum, pass_through<uint32_t>,
+                  conv_from_str<BelId>>::def_wrap(ctx_cls, "getBelChecksum");
+    fn_wrapper_3a_v<Context, decltype(&Context::bindBel), &Context::bindBel, conv_from_str<BelId>,
+                    conv_from_str<IdString>, pass_through<PlaceStrength>>::def_wrap(ctx_cls, "bindBel");
+    fn_wrapper_1a_v<Context, decltype(&Context::unbindBel), &Context::unbindBel, conv_from_str<BelId>>::def_wrap(
+            ctx_cls, "unbindBel");
+    fn_wrapper_1a<Context, decltype(&Context::getBoundBelCell), &Context::getBoundBelCell, conv_to_str<IdString>,
+                  conv_from_str<BelId>>::def_wrap(ctx_cls, "getBoundBelCell");
+    fn_wrapper_1a<Context, decltype(&Context::getConflictingBelCell), &Context::getConflictingBelCell,
+                  conv_to_str<IdString>, conv_from_str<BelId>>::def_wrap(ctx_cls, "getConflictingBelCell");
+    fn_wrapper_0a<Context, decltype(&Context::getBels), &Context::getBels, wrap_context<BelRange>>::def_wrap(ctx_cls,
+                                                                                                             "getBels");
+
+    fn_wrapper_2a<Context, decltype(&Context::getBelPinWire), &Context::getBelPinWire, conv_to_str<WireId>,
+                  conv_from_str<BelId>, conv_from_str<PortPin>>::def_wrap(ctx_cls, "getBelPinWire");
+    fn_wrapper_1a<Context, decltype(&Context::getWireBelPins), &Context::getWireBelPins, wrap_context<BelPinRange>,
+                  conv_from_str<WireId>>::def_wrap(ctx_cls, "getWireBelPins");
+
+    fn_wrapper_1a<Context, decltype(&Context::getWireChecksum), &Context::getWireChecksum, pass_through<uint32_t>,
+                  conv_from_str<WireId>>::def_wrap(ctx_cls, "getWireChecksum");
+    fn_wrapper_3a_v<Context, decltype(&Context::bindWire), &Context::bindWire, conv_from_str<WireId>,
+                    conv_from_str<IdString>, pass_through<PlaceStrength>>::def_wrap(ctx_cls, "bindWire");
+    fn_wrapper_1a_v<Context, decltype(&Context::unbindWire), &Context::unbindWire, conv_from_str<WireId>>::def_wrap(
+            ctx_cls, "unbindWire");
+    fn_wrapper_1a<Context, decltype(&Context::checkWireAvail), &Context::checkWireAvail, pass_through<bool>,
+                  conv_from_str<WireId>>::def_wrap(ctx_cls, "checkWireAvail");
+    fn_wrapper_1a<Context, decltype(&Context::getBoundWireNet), &Context::getBoundWireNet, conv_to_str<IdString>,
+                  conv_from_str<WireId>>::def_wrap(ctx_cls, "getBoundWireNet");
+    fn_wrapper_1a<Context, decltype(&Context::getConflictingWireNet), &Context::getConflictingWireNet,
+                  conv_to_str<IdString>, conv_from_str<WireId>>::def_wrap(ctx_cls, "getConflictingWireNet");
+
+    fn_wrapper_0a<Context, decltype(&Context::getWires), &Context::getWires, wrap_context<WireRange>>::def_wrap(
+            ctx_cls, "getWires");
+
+    fn_wrapper_0a<Context, decltype(&Context::getPips), &Context::getPips, wrap_context<AllPipRange>>::def_wrap(
+            ctx_cls, "getPips");
+    fn_wrapper_1a<Context, decltype(&Context::getPipChecksum), &Context::getPipChecksum, pass_through<uint32_t>,
+                  conv_from_str<PipId>>::def_wrap(ctx_cls, "getPipChecksum");
+    fn_wrapper_3a_v<Context, decltype(&Context::bindPip), &Context::bindPip, conv_from_str<PipId>,
+                    conv_from_str<IdString>, pass_through<PlaceStrength>>::def_wrap(ctx_cls, "bindPip");
+    fn_wrapper_1a_v<Context, decltype(&Context::unbindPip), &Context::unbindPip, conv_from_str<PipId>>::def_wrap(
+            ctx_cls, "unbindPip");
+    fn_wrapper_1a<Context, decltype(&Context::checkPipAvail), &Context::checkPipAvail, pass_through<bool>,
+                  conv_from_str<PipId>>::def_wrap(ctx_cls, "checkPipAvail");
+    fn_wrapper_1a<Context, decltype(&Context::getBoundPipNet), &Context::getBoundPipNet, conv_to_str<IdString>,
+                  conv_from_str<PipId>>::def_wrap(ctx_cls, "getBoundPipNet");
+    fn_wrapper_1a<Context, decltype(&Context::getConflictingPipNet), &Context::getConflictingPipNet,
+                  conv_to_str<IdString>, conv_from_str<PipId>>::def_wrap(ctx_cls, "getConflictingPipNet");
+
+    fn_wrapper_1a<Context, decltype(&Context::getPipsDownhill), &Context::getPipsDownhill, wrap_context<PipRange>,
+                  conv_from_str<WireId>>::def_wrap(ctx_cls, "getPipsDownhill");
+    fn_wrapper_1a<Context, decltype(&Context::getPipsUphill), &Context::getPipsUphill, wrap_context<PipRange>,
+                  conv_from_str<WireId>>::def_wrap(ctx_cls, "getPipsUphill");
+    fn_wrapper_1a<Context, decltype(&Context::getWireAliases), &Context::getWireAliases, wrap_context<PipRange>,
+                  conv_from_str<WireId>>::def_wrap(ctx_cls, "getWireAliases");
+
+    fn_wrapper_1a<Context, decltype(&Context::getPipSrcWire), &Context::getPipSrcWire, conv_to_str<WireId>,
+                  conv_from_str<PipId>>::def_wrap(ctx_cls, "getPipSrcWire");
+    fn_wrapper_1a<Context, decltype(&Context::getPipDstWire), &Context::getPipDstWire, conv_to_str<WireId>,
+                  conv_from_str<PipId>>::def_wrap(ctx_cls, "getPipDstWire");
+    fn_wrapper_1a<Context, decltype(&Context::getPipDelay), &Context::getPipDelay, pass_through<DelayInfo>,
+                  conv_from_str<PipId>>::def_wrap(ctx_cls, "getPipDelay");
+
+    fn_wrapper_1a<Context, decltype(&Context::getPackagePinBel), &Context::getPackagePinBel, conv_to_str<BelId>,
+                  pass_through<std::string>>::def_wrap(ctx_cls, "getPackagePinBel");
+    fn_wrapper_1a<Context, decltype(&Context::getBelPackagePin), &Context::getBelPackagePin, pass_through<std::string>,
+                  conv_from_str<BelId>>::def_wrap(ctx_cls, "getBelPackagePin");
+
+    fn_wrapper_0a<Context, decltype(&Context::getChipName), &Context::getChipName, pass_through<std::string>>::def_wrap(
+            ctx_cls, "getChipName");
+    fn_wrapper_0a<Context, decltype(&Context::archId), &Context::archId, conv_to_str<IdString>>::def_wrap(ctx_cls,
+                                                                                                          "archId");
+
+    typedef std::unordered_map<IdString, std::unique_ptr<CellInfo>> CellMap;
+    typedef std::unordered_map<IdString, std::unique_ptr<NetInfo>> NetMap;
+
+    readonly_wrapper<Context, decltype(&Context::cells), &Context::cells, wrap_context<CellMap &>>::def_wrap(ctx_cls,
+                                                                                                             "cells");
+    readonly_wrapper<Context, decltype(&Context::nets), &Context::nets, wrap_context<NetMap &>>::def_wrap(ctx_cls,
+                                                                                                          "nets");
+    WRAP_RANGE(Bel, conv_to_str<BelId>);
+    WRAP_RANGE(Wire, conv_to_str<WireId>);
+    WRAP_RANGE(AllPip, conv_to_str<PipId>);
+    WRAP_RANGE(Pip, conv_to_str<PipId>);
+
+    WRAP_MAP_UPTR(CellMap, "IdCellMap");
+    WRAP_MAP_UPTR(NetMap, "IdNetMap");
+}
 
 NEXTPNR_NAMESPACE_END
 
-#endif
+#endif // NO_PYTHON
diff --git a/ecp5/bitstream.cc b/ecp5/bitstream.cc
index c2218762..f1feba24 100644
--- a/ecp5/bitstream.cc
+++ b/ecp5/bitstream.cc
@@ -185,22 +185,31 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
     }
     // Find bank voltages
     std::unordered_map<int, IOVoltage> bankVcc;
+    std::unordered_map<int, bool> bankLvds;
+
     for (auto &cell : ctx->cells) {
         CellInfo *ci = cell.second.get();
         if (ci->bel != BelId() && ci->type == ctx->id("TRELLIS_IO")) {
             int bank = ctx->getPioBelBank(ci->bel);
+            std::string dir = str_or_default(ci->params, ctx->id("DIR"), "INPUT");
             std::string iotype = str_or_default(ci->attrs, ctx->id("IO_TYPE"), "LVCMOS33");
-            IOVoltage vcc = get_vccio(ioType_from_str(iotype));
-            if (bankVcc.find(bank) != bankVcc.end()) {
-                // TODO: strong and weak constraints
-                if (bankVcc[bank] != vcc) {
-                    log_error("Error processing '%s': incompatible IO voltages %s and %s on bank %d.",
-                              cell.first.c_str(ctx), iovoltage_to_str(bankVcc[bank]).c_str(),
-                              iovoltage_to_str(vcc).c_str(), bank);
+
+            if (dir != "INPUT") {
+                IOVoltage vcc = get_vccio(ioType_from_str(iotype));
+                if (bankVcc.find(bank) != bankVcc.end()) {
+                    // TODO: strong and weak constraints
+                    if (bankVcc[bank] != vcc) {
+                        log_error("Error processing '%s': incompatible IO voltages %s and %s on bank %d.",
+                                  cell.first.c_str(ctx), iovoltage_to_str(bankVcc[bank]).c_str(),
+                                  iovoltage_to_str(vcc).c_str(), bank);
+                    }
+                } else {
+                    bankVcc[bank] = vcc;
                 }
-            } else {
-                bankVcc[bank] = vcc;
             }
+
+            if (iotype == "LVDS")
+                bankLvds[bank] = true;
         }
     }
 
@@ -211,6 +220,10 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
             int bank = std::stoi(type.substr(7));
             if (bankVcc.find(bank) != bankVcc.end())
                 cc.tiles[tile.first].add_enum("BANK.VCCIO", iovoltage_to_str(bankVcc[bank]));
+            if (bankLvds[bank]) {
+                cc.tiles[tile.first].add_enum("BANK.DIFF_REF", "ON");
+                cc.tiles[tile.first].add_enum("BANK.LVDSO", "ON");
+            }
         }
     }
 
@@ -267,8 +280,8 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
                     other = "PIOD";
                 else
                     log_error("cannot place differential IO at location %s\n", pio.c_str());
-                cc.tiles[pio_tile].add_enum(other + ".BASE_TYPE", "_NONE_");
-                cc.tiles[pic_tile].add_enum(other + ".BASE_TYPE", "_NONE_");
+                //cc.tiles[pio_tile].add_enum(other + ".BASE_TYPE", "_NONE_");
+                //cc.tiles[pic_tile].add_enum(other + ".BASE_TYPE", "_NONE_");
                 cc.tiles[pio_tile].add_enum(other + ".PULLMODE", "NONE");
                 cc.tiles[pio_tile].add_enum(pio + ".PULLMODE", "NONE");
             }
diff --git a/generic/arch_pybindings.cc b/generic/arch_pybindings.cc
index a99723f2..186b2c13 100644
--- a/generic/arch_pybindings.cc
+++ b/generic/arch_pybindings.cc
@@ -20,12 +20,22 @@
 
 #ifndef NO_PYTHON
 
+#include "arch_pybindings.h"
 #include "nextpnr.h"
 #include "pybindings.h"
 
 NEXTPNR_NAMESPACE_BEGIN
 
-void arch_wrap_python() { class_<ArchArgs>("ArchArgs"); }
+void arch_wrap_python()
+{
+    using namespace PythonConversion;
+    auto arch_cls = class_<Arch, Arch *, bases<BaseCtx>, boost::noncopyable>("Arch", init<ArchArgs>());
+    auto ctx_cls = class_<Context, Context *, bases<Arch>, boost::noncopyable>("Context", no_init)
+                           .def("checksum", &Context::checksum)
+                           .def("pack", &Context::pack)
+                           .def("place", &Context::place)
+                           .def("route", &Context::route);
+}
 
 NEXTPNR_NAMESPACE_END
 
diff --git a/gui/designwidget.cc b/gui/designwidget.cc
index e63ee937..7e8e2840 100644
--- a/gui/designwidget.cc
+++ b/gui/designwidget.cc
@@ -312,6 +312,7 @@ void DesignWidget::newContext(Context *ctx)
     QMap<QString, QTreeWidgetItem *> pip_items;
     pip_root->setText(0, "Pips");
     treeWidget->insertTopLevelItem(0, pip_root);
+#ifndef ARCH_ECP5    
     if (ctx) {
         for (auto pip : ctx->getPips()) {
             auto id = ctx->getPipName(pip);
@@ -338,6 +339,7 @@ void DesignWidget::newContext(Context *ctx)
     for (auto pip : nameToItem[2].toStdMap()) {
         pip_root->addChild(pip.second);
     }
+#endif    
 
     nets_root = new QTreeWidgetItem(treeWidget);
     nets_root->setText(0, "Nets");
diff --git a/ice40/picorv32_benchmark.py b/ice40/picorv32_benchmark.py
new file mode 100755
index 00000000..9544db50
--- /dev/null
+++ b/ice40/picorv32_benchmark.py
@@ -0,0 +1,43 @@
+#!/usr/bin/env python3
+import os, sys, threading
+from os import path
+import subprocess
+import re
+
+num_runs = 8
+
+if not path.exists("picorv32.json"):
+    os.remove("picorv32.json")
+    subprocess.run(["wget", "https://raw.githubusercontent.com/cliffordwolf/picorv32/master/picorv32.v"], check=True)
+    subprocess.run(["yosys", "-q", "-p", "synth_ice40 -json picorv32.json -top top", "picorv32.v", "picorv32_top.v"], check=True)
+
+fmax = {}
+
+if not path.exists("picorv32_work"):
+    os.mkdir("picorv32_work")
+
+threads = []
+
+for i in range(num_runs):
+    def runner(run):
+        ascfile = "picorv32_work/picorv32_s{}.asc".format(run)
+        if path.exists(ascfile):
+            os.remove(ascfile)
+        result = subprocess.run(["../nextpnr-ice40", "--hx8k", "--seed", str(run), "--json", "picorv32.json", "--asc", ascfile], stderr=subprocess.DEVNULL, stdout=subprocess.DEVNULL)
+        if result.returncode != 0:
+            print("Run {} failed!".format(run))
+        else:
+            icetime_res = subprocess.check_output(["icetime", "-d", "hx8k", ascfile])
+            fmax_m = re.search(r'\(([0-9.]+) MHz\)', icetime_res.decode('utf-8'))
+            fmax[run] = float(fmax_m.group(1))
+    threads.append(threading.Thread(target=runner, args=[i+1]))
+
+for t in threads: t.start()
+for t in threads: t.join()
+
+fmax_min = min(fmax.values())
+fmax_max = max(fmax.values())
+fmax_avg = sum(fmax.values()) / len(fmax)
+
+print("{}/{} runs passed".format(len(fmax), num_runs))
+print("icetime: min = {} MHz, avg = {} MHz, max = {} MHz".format(fmax_min, fmax_avg, fmax_max))