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timing: Allow overriding of route delays

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Signed-off-by: gatecat <gatecat@ds0.me>
This commit is contained in:
gatecat 2021-07-28 11:20:28 +01:00
parent eb6817c259
commit 14c676ab49
2 changed files with 10 additions and 3 deletions
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7
common/timing.cc
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@ -38,10 +38,11 @@ void TimingAnalyser::setup()
run(); run();
} }
void TimingAnalyser::run() void TimingAnalyser::run(bool update_route_delays)
{ {
reset_times(); reset_times();
get_route_delays(); if (update_route_delays)
get_route_delays();
walk_forward(); walk_forward();
walk_backward(); walk_backward();
compute_slack(); compute_slack();
@ -149,6 +150,8 @@ void TimingAnalyser::get_route_delays()
} }
} }
void TimingAnalyser::set_route_delay(CellPortKey port, DelayPair value) { ports.at(port).route_delay = value; }
void TimingAnalyser::topo_sort() void TimingAnalyser::topo_sort()
{ {
TopoSort<CellPortKey> topo; TopoSort<CellPortKey> topo;

6
common/timing.h
View File

@ -97,9 +97,13 @@ struct TimingAnalyser
public: public:
TimingAnalyser(Context *ctx) : ctx(ctx){}; TimingAnalyser(Context *ctx) : ctx(ctx){};
void setup(); void setup();
void run(); void run(bool update_route_delays = true);
void print_report(); void print_report();
// This is used when routers etc are not actually binding detailed routing (due to congestion or an abstracted
// model), but want to re-run STA with their own calculated delays
void set_route_delay(CellPortKey port, DelayPair value);
float get_criticality(CellPortKey port) const { return ports.at(port).worst_crit; } float get_criticality(CellPortKey port) const { return ports.at(port).worst_crit; }
float get_setup_slack(CellPortKey port) const { return ports.at(port).worst_setup_slack; } float get_setup_slack(CellPortKey port) const { return ports.at(port).worst_setup_slack; }
float get_domain_setup_slack(CellPortKey port) const float get_domain_setup_slack(CellPortKey port) const