load wires
This commit is contained in:
Pepijn de Vos
parent
93faa752f5
commit
15d0533474
@ -66,7 +66,7 @@ endif()
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set(PROGRAM_PREFIX "" CACHE STRING "Name prefix for executables")
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# List of families to build
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set(FAMILIES generic ice40 ecp5)
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set(FAMILIES generic ice40 ecp5 gowin)
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set(ARCH "" CACHE STRING "Architecture family for nextpnr build")
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set_property(CACHE ARCH PROPERTY STRINGS ${FAMILIES})
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@ -99,9 +99,9 @@ if (MSVC)
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else()
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set(CMAKE_CXX_FLAGS_DEBUG "-Wall -fPIC -ggdb -pipe")
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if (USE_OPENMP)
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set(CMAKE_CXX_FLAGS_RELEASE "-Wall -fPIC -O3 -g -pipe -fopenmp")
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set(CMAKE_CXX_FLAGS_RELEASE "-Wall -fPIC -O0 -g -pipe -fopenmp")
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else()
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set(CMAKE_CXX_FLAGS_RELEASE "-Wall -fPIC -O3 -g -pipe")
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set(CMAKE_CXX_FLAGS_RELEASE "-Wall -fPIC -O0 -g -pipe")
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endif()
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endif()
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@ -59,7 +59,7 @@ template <> struct hash<std::pair<int, NEXTPNR_NAMESPACE_PREFIX BelId>>
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return seed;
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}
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};
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#ifndef ARCH_GENERIC
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#if !defined(ARCH_GENERIC) && !defined(ARCH_GOWIN)
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template <> struct hash<std::pair<NEXTPNR_NAMESPACE_PREFIX IdString, NEXTPNR_NAMESPACE_PREFIX BelId>>
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{
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std::size_t
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54
gowin/CMakeLists.txt
Normal file
54
gowin/CMakeLists.txt
Normal file
@ -0,0 +1,54 @@
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cmake_minimum_required(VERSION 3.5)
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project(chipdb-gowin NONE)
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set(ALL_GOWIN_DEVICES GW1N-1 GW1N-9)
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set(GOWIN_DEVICES ${ALL_GOWIN_DEVICES} CACHE STRING
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"Include support for these Gowin devices (available: ${ALL_GOWIN_DEVICES})")
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message(STATUS "Enabled Gowin devices: ${GOWIN_DEVICES}")
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find_program (GOWIN_BBA_EXECUTABLE gowin_bba)
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message(STATUS "gowin_bba executable: ${GOWIN_BBA_EXECUTABLE}")
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if(DEFINED GOWIN_CHIPDB)
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add_custom_target(chipdb-gowin-bbas ALL)
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else()
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find_package(PythonInterp 3.6 REQUIRED)
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# shared among all families
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set(SERIALIZE_CHIPDBS TRUE CACHE BOOL
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"Serialize device data preprocessing to minimize memory use")
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set(all_device_bbas)
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file(MAKE_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR}/chipdb)
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foreach(device ${GOWIN_DEVICES})
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if(NOT device IN_LIST ALL_GOWIN_DEVICES)
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message(FATAL_ERROR "Device ${device} is not a supported Gowin device")
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endif()
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set(device_bba chipdb/chipdb-${device}.bba)
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add_custom_command(
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OUTPUT ${device_bba}
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COMMAND ${GOWIN_BBA_EXECUTABLE} -d ${device} -o ${device_bba}.new
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# atomically update
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COMMAND ${CMAKE_COMMAND} -E rename ${device_bba}.new ${device_bba}
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DEPENDS
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${GOWIN_BBA_EXECUTABLE}
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${PREVIOUS_CHIPDB_TARGET}
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VERBATIM)
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list(APPEND all_device_bbas ${device_bba})
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if(SERIALIZE_CHIPDBS)
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set(PREVIOUS_CHIPDB_TARGET ${CMAKE_CURRENT_BINARY_DIR}/${device_bba})
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endif()
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endforeach()
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add_custom_target(chipdb-gowin-bbas ALL DEPENDS ${all_device_bbas})
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get_directory_property(has_parent PARENT_DIRECTORY)
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if(has_parent)
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set(GOWIN_CHIPDB ${CMAKE_CURRENT_BINARY_DIR}/chipdb PARENT_SCOPE)
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# serialize chipdb build across multiple architectures
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set(PREVIOUS_CHIPDB_TARGET chipdb-gowin-bbas PARENT_SCOPE)
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else()
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message(STATUS "Build nextpnr with -DGOWIN_CHIPDB=${CMAKE_CURRENT_BINARY_DIR}/chipdb")
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endif()
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endif()
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810
gowin/arch.cc
Normal file
810
gowin/arch.cc
Normal file
@ -0,0 +1,810 @@
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/*
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* nextpnr -- Next Generation Place and Route
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*
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* Copyright (C) 2018 Clifford Wolf <clifford@symbioticeda.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include <iostream>
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#include <math.h>
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#include "nextpnr.h"
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#include "embed.h"
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#include "placer1.h"
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#include "placer_heap.h"
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#include "router1.h"
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#include "router2.h"
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#include "util.h"
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NEXTPNR_NAMESPACE_BEGIN
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WireInfo &Arch::wire_info(IdString wire)
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{
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auto w = wires.find(wire);
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if (w == wires.end())
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NPNR_ASSERT_FALSE_STR("no wire named " + wire.str(this));
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return w->second;
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}
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PipInfo &Arch::pip_info(IdString pip)
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{
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auto p = pips.find(pip);
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if (p == pips.end())
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NPNR_ASSERT_FALSE_STR("no pip named " + pip.str(this));
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return p->second;
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}
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BelInfo &Arch::bel_info(IdString bel)
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{
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auto b = bels.find(bel);
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if (b == bels.end())
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NPNR_ASSERT_FALSE_STR("no bel named " + bel.str(this));
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return b->second;
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}
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void Arch::addWire(IdString name, IdString type, int x, int y)
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{
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NPNR_ASSERT(wires.count(name) == 0);
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WireInfo &wi = wires[name];
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wi.name = name;
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wi.type = type;
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wi.x = x;
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wi.y = y;
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wire_ids.push_back(name);
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}
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void Arch::addPip(IdString name, IdString type, IdString srcWire, IdString dstWire, DelayInfo delay, Loc loc)
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{
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NPNR_ASSERT(pips.count(name) == 0);
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PipInfo &pi = pips[name];
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pi.name = name;
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pi.type = type;
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pi.srcWire = srcWire;
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pi.dstWire = dstWire;
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pi.delay = delay;
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pi.loc = loc;
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wire_info(srcWire).downhill.push_back(name);
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wire_info(dstWire).uphill.push_back(name);
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pip_ids.push_back(name);
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if (int(tilePipDimZ.size()) <= loc.x)
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tilePipDimZ.resize(loc.x + 1);
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if (int(tilePipDimZ[loc.x].size()) <= loc.y)
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tilePipDimZ[loc.x].resize(loc.y + 1);
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gridDimX = std::max(gridDimX, loc.x + 1);
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gridDimY = std::max(gridDimY, loc.x + 1);
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tilePipDimZ[loc.x][loc.y] = std::max(tilePipDimZ[loc.x][loc.y], loc.z + 1);
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}
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void Arch::addBel(IdString name, IdString type, Loc loc, bool gb)
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{
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NPNR_ASSERT(bels.count(name) == 0);
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NPNR_ASSERT(bel_by_loc.count(loc) == 0);
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BelInfo &bi = bels[name];
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bi.name = name;
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bi.type = type;
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bi.x = loc.x;
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bi.y = loc.y;
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bi.z = loc.z;
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bi.gb = gb;
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bel_ids.push_back(name);
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bel_by_loc[loc] = name;
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if (int(bels_by_tile.size()) <= loc.x)
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bels_by_tile.resize(loc.x + 1);
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if (int(bels_by_tile[loc.x].size()) <= loc.y)
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bels_by_tile[loc.x].resize(loc.y + 1);
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bels_by_tile[loc.x][loc.y].push_back(name);
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if (int(tileBelDimZ.size()) <= loc.x)
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tileBelDimZ.resize(loc.x + 1);
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if (int(tileBelDimZ[loc.x].size()) <= loc.y)
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tileBelDimZ[loc.x].resize(loc.y + 1);
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gridDimX = std::max(gridDimX, loc.x + 1);
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gridDimY = std::max(gridDimY, loc.x + 1);
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tileBelDimZ[loc.x][loc.y] = std::max(tileBelDimZ[loc.x][loc.y], loc.z + 1);
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}
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void Arch::addBelInput(IdString bel, IdString name, IdString wire)
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{
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NPNR_ASSERT(bel_info(bel).pins.count(name) == 0);
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PinInfo &pi = bel_info(bel).pins[name];
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pi.name = name;
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pi.wire = wire;
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pi.type = PORT_IN;
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wire_info(wire).downhill_bel_pins.push_back(BelPin{bel, name});
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wire_info(wire).bel_pins.push_back(BelPin{bel, name});
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}
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void Arch::addBelOutput(IdString bel, IdString name, IdString wire)
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{
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NPNR_ASSERT(bel_info(bel).pins.count(name) == 0);
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PinInfo &pi = bel_info(bel).pins[name];
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pi.name = name;
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pi.wire = wire;
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pi.type = PORT_OUT;
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wire_info(wire).uphill_bel_pin = BelPin{bel, name};
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wire_info(wire).bel_pins.push_back(BelPin{bel, name});
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}
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void Arch::addBelInout(IdString bel, IdString name, IdString wire)
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{
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NPNR_ASSERT(bel_info(bel).pins.count(name) == 0);
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PinInfo &pi = bel_info(bel).pins[name];
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pi.name = name;
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pi.wire = wire;
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pi.type = PORT_INOUT;
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wire_info(wire).downhill_bel_pins.push_back(BelPin{bel, name});
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wire_info(wire).bel_pins.push_back(BelPin{bel, name});
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}
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void Arch::addGroupBel(IdString group, IdString bel) { groups[group].bels.push_back(bel); }
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void Arch::addGroupWire(IdString group, IdString wire) { groups[group].wires.push_back(wire); }
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void Arch::addGroupPip(IdString group, IdString pip) { groups[group].pips.push_back(pip); }
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void Arch::addGroupGroup(IdString group, IdString grp) { groups[group].groups.push_back(grp); }
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void Arch::addDecalGraphic(DecalId decal, const GraphicElement &graphic)
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{
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decal_graphics[decal].push_back(graphic);
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refreshUi();
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}
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void Arch::setWireDecal(WireId wire, DecalXY decalxy)
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{
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wire_info(wire).decalxy = decalxy;
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refreshUiWire(wire);
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}
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void Arch::setPipDecal(PipId pip, DecalXY decalxy)
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{
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pip_info(pip).decalxy = decalxy;
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refreshUiPip(pip);
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}
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void Arch::setBelDecal(BelId bel, DecalXY decalxy)
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{
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bel_info(bel).decalxy = decalxy;
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refreshUiBel(bel);
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}
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void Arch::setGroupDecal(GroupId group, DecalXY decalxy)
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{
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groups[group].decalxy = decalxy;
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refreshUiGroup(group);
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}
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void Arch::setWireAttr(IdString wire, IdString key, const std::string &value) { wire_info(wire).attrs[key] = value; }
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void Arch::setPipAttr(IdString pip, IdString key, const std::string &value) { pip_info(pip).attrs[key] = value; }
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void Arch::setBelAttr(IdString bel, IdString key, const std::string &value) { bel_info(bel).attrs[key] = value; }
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void Arch::setLutK(int K) { args.K = K; }
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void Arch::setDelayScaling(double scale, double offset)
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{
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args.delayScale = scale;
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args.delayOffset = offset;
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}
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void Arch::addCellTimingClock(IdString cell, IdString port) { cellTiming[cell].portClasses[port] = TMG_CLOCK_INPUT; }
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void Arch::addCellTimingDelay(IdString cell, IdString fromPort, IdString toPort, DelayInfo delay)
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{
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if (get_or_default(cellTiming[cell].portClasses, fromPort, TMG_IGNORE) == TMG_IGNORE)
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cellTiming[cell].portClasses[fromPort] = TMG_COMB_INPUT;
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if (get_or_default(cellTiming[cell].portClasses, toPort, TMG_IGNORE) == TMG_IGNORE)
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cellTiming[cell].portClasses[toPort] = TMG_COMB_OUTPUT;
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cellTiming[cell].combDelays[CellDelayKey{fromPort, toPort}] = delay;
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}
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void Arch::addCellTimingSetupHold(IdString cell, IdString port, IdString clock, DelayInfo setup, DelayInfo hold)
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{
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TimingClockingInfo ci;
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ci.clock_port = clock;
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ci.edge = RISING_EDGE;
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ci.setup = setup;
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ci.hold = hold;
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cellTiming[cell].clockingInfo[port].push_back(ci);
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cellTiming[cell].portClasses[port] = TMG_REGISTER_INPUT;
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}
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void Arch::addCellTimingClockToOut(IdString cell, IdString port, IdString clock, DelayInfo clktoq)
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{
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TimingClockingInfo ci;
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ci.clock_port = clock;
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ci.edge = RISING_EDGE;
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ci.clockToQ = clktoq;
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cellTiming[cell].clockingInfo[port].push_back(ci);
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cellTiming[cell].portClasses[port] = TMG_REGISTER_OUTPUT;
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}
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// ---------------------------------------------------------------
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//TODO represent wires more intelligently.
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IdString Arch::wireToGlobal(int row, int col, const DatabasePOD* db, IdString wire) {
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std::string wirename = wire.str(this);
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char buf[32];
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if( wirename == "VCC" || wirename == "GND" ) {
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return wire;
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}
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if(!isdigit(wirename[1]) || !isdigit(wirename[2]) || !isdigit(wirename[3])) {
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snprintf(buf, 32, "R%dC%d_%s", row+1, col+1, wirename.c_str());
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return id(buf);
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}
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char direction = wirename[0];
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int num = std::stoi(wirename.substr(1, 2));
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int segment = std::stoi(wirename.substr(3, 1));
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int rootrow, rootcol;
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switch (direction)
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{
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case 'N':
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rootrow = row + segment;
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rootcol = col;
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break;
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case 'S':
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rootrow = row - segment;
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rootcol = col;
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break;
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case 'E':
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rootrow = row;
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rootcol = col - segment;
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break;
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case 'W':
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rootrow = row;
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rootcol = col + segment;
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break;
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default:
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snprintf(buf, 32, "R%dC%d_%s", row+1, col+1, wirename.c_str());
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return id(buf);
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break;
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}
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// wires wrap around the edges
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// assumes 0-based indexes
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if(rootrow < 0) {
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rootrow = -1-rootrow;
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direction = 'N';
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} else if(rootcol < 0) {
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rootcol = -1-rootcol;
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direction = 'W';
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} else if(rootrow >= db->rows) {
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rootrow = 2*db->rows-1-rootrow;
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direction = 'S';
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} else if(rootcol >= db->cols) {
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rootcol = 2*db->cols-1-rootcol;
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direction = 'E';
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}
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snprintf(buf, 32, "R%dC%d_%c%d", rootrow+1, rootcol+1, direction, num);
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return id(buf);
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}
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Arch::Arch(ArchArgs args) : args(args)
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{
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family = "GW1N-9";
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device = "GW1NR-9";
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speed = "C6/E5"; // or whatever
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package = "QFN48"; // or something
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// Load database
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std::string chipdb = stringf("gowin/chipdb-%s.bin", family.c_str());
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auto db = reinterpret_cast<const DatabasePOD*>(get_chipdb(chipdb));
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if (db == nullptr)
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log_error("Failed to load chipdb '%s'\n", chipdb.c_str());
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if (db->family.get() != family) {
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log_error("Database is for family '%s' but provided device is family '%s'.\n", db->family.get(),
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family.c_str());
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}
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// setup id strings
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for (size_t i = 0; i < db->num_ids; i++) {
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IdString::initialize_add(this, db->id_strs[i].get(), uint32_t(i)+db->num_constids);
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}
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// setup db
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for (int i=0; i < db->rows*db->cols; i++) {
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int row = i/db->cols;
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int col = i%db->cols;
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const TilePOD* tile = db->grid[i].get();
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for(unsigned int j=0; j < tile->num_pips; j++) {
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const PairPOD pip = tile->pips[j];
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IdString gdestname = wireToGlobal(row, col, db, pip.dest_id);
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if(wires.count(gdestname) == 0) addWire(gdestname, pip.dest_id, col, row);
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IdString gsrcname = wireToGlobal(row, col, db, pip.src_id);
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if(wires.count(gsrcname) == 0) addWire(gsrcname, pip.src_id, col, row);
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}
|
||||
for(unsigned int j=0; j < tile->num_clock_pips; j++) {
|
||||
const PairPOD pip = tile->clock_pips[j];
|
||||
IdString gdestname = wireToGlobal(row, col, db, pip.dest_id);
|
||||
if(wires.count(gdestname) == 0) addWire(gdestname, pip.dest_id, col, row);
|
||||
IdString gsrcname = wireToGlobal(row, col, db, pip.src_id);
|
||||
if(wires.count(gsrcname) == 0) addWire(gsrcname, pip.src_id, col, row);
|
||||
}
|
||||
}
|
||||
// Dummy for empty decals
|
||||
decal_graphics[IdString()];
|
||||
}
|
||||
|
||||
void IdString::initialize_arch(const BaseCtx *ctx) {}
|
||||
|
||||
// ---------------------------------------------------------------
|
||||
|
||||
BelId Arch::getBelByName(IdString name) const
|
||||
{
|
||||
if (bels.count(name))
|
||||
return name;
|
||||
return BelId();
|
||||
}
|
||||
|
||||
IdString Arch::getBelName(BelId bel) const { return bel; }
|
||||
|
||||
Loc Arch::getBelLocation(BelId bel) const
|
||||
{
|
||||
auto &info = bels.at(bel);
|
||||
return Loc(info.x, info.y, info.z);
|
||||
}
|
||||
|
||||
BelId Arch::getBelByLocation(Loc loc) const
|
||||
{
|
||||
auto it = bel_by_loc.find(loc);
|
||||
if (it != bel_by_loc.end())
|
||||
return it->second;
|
||||
return BelId();
|
||||
}
|
||||
|
||||
const std::vector<BelId> &Arch::getBelsByTile(int x, int y) const { return bels_by_tile.at(x).at(y); }
|
||||
|
||||
bool Arch::getBelGlobalBuf(BelId bel) const { return bels.at(bel).gb; }
|
||||
|
||||
uint32_t Arch::getBelChecksum(BelId bel) const
|
||||
{
|
||||
// FIXME
|
||||
return 0;
|
||||
}
|
||||
|
||||
void Arch::bindBel(BelId bel, CellInfo *cell, PlaceStrength strength)
|
||||
{
|
||||
bels.at(bel).bound_cell = cell;
|
||||
cell->bel = bel;
|
||||
cell->belStrength = strength;
|
||||
refreshUiBel(bel);
|
||||
}
|
||||
|
||||
void Arch::unbindBel(BelId bel)
|
||||
{
|
||||
bels.at(bel).bound_cell->bel = BelId();
|
||||
bels.at(bel).bound_cell->belStrength = STRENGTH_NONE;
|
||||
bels.at(bel).bound_cell = nullptr;
|
||||
refreshUiBel(bel);
|
||||
}
|
||||
|
||||
bool Arch::checkBelAvail(BelId bel) const { return bels.at(bel).bound_cell == nullptr; }
|
||||
|
||||
CellInfo *Arch::getBoundBelCell(BelId bel) const { return bels.at(bel).bound_cell; }
|
||||
|
||||
CellInfo *Arch::getConflictingBelCell(BelId bel) const { return bels.at(bel).bound_cell; }
|
||||
|
||||
const std::vector<BelId> &Arch::getBels() const { return bel_ids; }
|
||||
|
||||
IdString Arch::getBelType(BelId bel) const { return bels.at(bel).type; }
|
||||
|
||||
const std::map<IdString, std::string> &Arch::getBelAttrs(BelId bel) const { return bels.at(bel).attrs; }
|
||||
|
||||
WireId Arch::getBelPinWire(BelId bel, IdString pin) const
|
||||
{
|
||||
const auto &bdata = bels.at(bel);
|
||||
if (!bdata.pins.count(pin))
|
||||
log_error("bel '%s' has no pin '%s'\n", bel.c_str(this), pin.c_str(this));
|
||||
return bdata.pins.at(pin).wire;
|
||||
}
|
||||
|
||||
PortType Arch::getBelPinType(BelId bel, IdString pin) const { return bels.at(bel).pins.at(pin).type; }
|
||||
|
||||
std::vector<IdString> Arch::getBelPins(BelId bel) const
|
||||
{
|
||||
std::vector<IdString> ret;
|
||||
for (auto &it : bels.at(bel).pins)
|
||||
ret.push_back(it.first);
|
||||
return ret;
|
||||
}
|
||||
|
||||
// ---------------------------------------------------------------
|
||||
|
||||
WireId Arch::getWireByName(IdString name) const
|
||||
{
|
||||
if (wires.count(name))
|
||||
return name;
|
||||
return WireId();
|
||||
}
|
||||
|
||||
IdString Arch::getWireName(WireId wire) const { return wire; }
|
||||
|
||||
IdString Arch::getWireType(WireId wire) const { return wires.at(wire).type; }
|
||||
|
||||
const std::map<IdString, std::string> &Arch::getWireAttrs(WireId wire) const { return wires.at(wire).attrs; }
|
||||
|
||||
uint32_t Arch::getWireChecksum(WireId wire) const
|
||||
{
|
||||
// FIXME
|
||||
return 0;
|
||||
}
|
||||
|
||||
void Arch::bindWire(WireId wire, NetInfo *net, PlaceStrength strength)
|
||||
{
|
||||
wires.at(wire).bound_net = net;
|
||||
net->wires[wire].pip = PipId();
|
||||
net->wires[wire].strength = strength;
|
||||
refreshUiWire(wire);
|
||||
}
|
||||
|
||||
void Arch::unbindWire(WireId wire)
|
||||
{
|
||||
auto &net_wires = wires.at(wire).bound_net->wires;
|
||||
|
||||
auto pip = net_wires.at(wire).pip;
|
||||
if (pip != PipId()) {
|
||||
pips.at(pip).bound_net = nullptr;
|
||||
refreshUiPip(pip);
|
||||
}
|
||||
|
||||
net_wires.erase(wire);
|
||||
wires.at(wire).bound_net = nullptr;
|
||||
refreshUiWire(wire);
|
||||
}
|
||||
|
||||
bool Arch::checkWireAvail(WireId wire) const { return wires.at(wire).bound_net == nullptr; }
|
||||
|
||||
NetInfo *Arch::getBoundWireNet(WireId wire) const { return wires.at(wire).bound_net; }
|
||||
|
||||
NetInfo *Arch::getConflictingWireNet(WireId wire) const { return wires.at(wire).bound_net; }
|
||||
|
||||
const std::vector<BelPin> &Arch::getWireBelPins(WireId wire) const { return wires.at(wire).bel_pins; }
|
||||
|
||||
const std::vector<WireId> &Arch::getWires() const { return wire_ids; }
|
||||
|
||||
// ---------------------------------------------------------------
|
||||
|
||||
PipId Arch::getPipByName(IdString name) const
|
||||
{
|
||||
if (pips.count(name))
|
||||
return name;
|
||||
return PipId();
|
||||
}
|
||||
|
||||
IdString Arch::getPipName(PipId pip) const { return pip; }
|
||||
|
||||
IdString Arch::getPipType(PipId pip) const { return pips.at(pip).type; }
|
||||
|
||||
const std::map<IdString, std::string> &Arch::getPipAttrs(PipId pip) const { return pips.at(pip).attrs; }
|
||||
|
||||
uint32_t Arch::getPipChecksum(PipId wire) const
|
||||
{
|
||||
// FIXME
|
||||
return 0;
|
||||
}
|
||||
|
||||
void Arch::bindPip(PipId pip, NetInfo *net, PlaceStrength strength)
|
||||
{
|
||||
WireId wire = pips.at(pip).dstWire;
|
||||
pips.at(pip).bound_net = net;
|
||||
wires.at(wire).bound_net = net;
|
||||
net->wires[wire].pip = pip;
|
||||
net->wires[wire].strength = strength;
|
||||
refreshUiPip(pip);
|
||||
refreshUiWire(wire);
|
||||
}
|
||||
|
||||
void Arch::unbindPip(PipId pip)
|
||||
{
|
||||
WireId wire = pips.at(pip).dstWire;
|
||||
wires.at(wire).bound_net->wires.erase(wire);
|
||||
pips.at(pip).bound_net = nullptr;
|
||||
wires.at(wire).bound_net = nullptr;
|
||||
refreshUiPip(pip);
|
||||
refreshUiWire(wire);
|
||||
}
|
||||
|
||||
bool Arch::checkPipAvail(PipId pip) const { return pips.at(pip).bound_net == nullptr; }
|
||||
|
||||
NetInfo *Arch::getBoundPipNet(PipId pip) const { return pips.at(pip).bound_net; }
|
||||
|
||||
NetInfo *Arch::getConflictingPipNet(PipId pip) const { return pips.at(pip).bound_net; }
|
||||
|
||||
WireId Arch::getConflictingPipWire(PipId pip) const { return pips.at(pip).bound_net ? pips.at(pip).dstWire : WireId(); }
|
||||
|
||||
const std::vector<PipId> &Arch::getPips() const { return pip_ids; }
|
||||
|
||||
Loc Arch::getPipLocation(PipId pip) const { return pips.at(pip).loc; }
|
||||
|
||||
WireId Arch::getPipSrcWire(PipId pip) const { return pips.at(pip).srcWire; }
|
||||
|
||||
WireId Arch::getPipDstWire(PipId pip) const { return pips.at(pip).dstWire; }
|
||||
|
||||
DelayInfo Arch::getPipDelay(PipId pip) const { return pips.at(pip).delay; }
|
||||
|
||||
const std::vector<PipId> &Arch::getPipsDownhill(WireId wire) const { return wires.at(wire).downhill; }
|
||||
|
||||
const std::vector<PipId> &Arch::getPipsUphill(WireId wire) const { return wires.at(wire).uphill; }
|
||||
|
||||
// ---------------------------------------------------------------
|
||||
|
||||
GroupId Arch::getGroupByName(IdString name) const { return name; }
|
||||
|
||||
IdString Arch::getGroupName(GroupId group) const { return group; }
|
||||
|
||||
std::vector<GroupId> Arch::getGroups() const
|
||||
{
|
||||
std::vector<GroupId> ret;
|
||||
for (auto &it : groups)
|
||||
ret.push_back(it.first);
|
||||
return ret;
|
||||
}
|
||||
|
||||
const std::vector<BelId> &Arch::getGroupBels(GroupId group) const { return groups.at(group).bels; }
|
||||
|
||||
const std::vector<WireId> &Arch::getGroupWires(GroupId group) const { return groups.at(group).wires; }
|
||||
|
||||
const std::vector<PipId> &Arch::getGroupPips(GroupId group) const { return groups.at(group).pips; }
|
||||
|
||||
const std::vector<GroupId> &Arch::getGroupGroups(GroupId group) const { return groups.at(group).groups; }
|
||||
|
||||
// ---------------------------------------------------------------
|
||||
|
||||
delay_t Arch::estimateDelay(WireId src, WireId dst) const
|
||||
{
|
||||
const WireInfo &s = wires.at(src);
|
||||
const WireInfo &d = wires.at(dst);
|
||||
int dx = abs(s.x - d.x);
|
||||
int dy = abs(s.y - d.y);
|
||||
return (dx + dy) * args.delayScale + args.delayOffset;
|
||||
}
|
||||
|
||||
delay_t Arch::predictDelay(const NetInfo *net_info, const PortRef &sink) const
|
||||
{
|
||||
const auto &driver = net_info->driver;
|
||||
auto driver_loc = getBelLocation(driver.cell->bel);
|
||||
auto sink_loc = getBelLocation(sink.cell->bel);
|
||||
|
||||
int dx = abs(sink_loc.x - driver_loc.x);
|
||||
int dy = abs(sink_loc.y - driver_loc.y);
|
||||
return (dx + dy) * args.delayScale + args.delayOffset;
|
||||
}
|
||||
|
||||
bool Arch::getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t &budget) const { return false; }
|
||||
|
||||
ArcBounds Arch::getRouteBoundingBox(WireId src, WireId dst) const
|
||||
{
|
||||
ArcBounds bb;
|
||||
|
||||
int src_x = wires.at(src).x;
|
||||
int src_y = wires.at(src).y;
|
||||
int dst_x = wires.at(dst).x;
|
||||
int dst_y = wires.at(dst).y;
|
||||
|
||||
bb.x0 = src_x;
|
||||
bb.y0 = src_y;
|
||||
bb.x1 = src_x;
|
||||
bb.y1 = src_y;
|
||||
|
||||
auto extend = [&](int x, int y) {
|
||||
bb.x0 = std::min(bb.x0, x);
|
||||
bb.x1 = std::max(bb.x1, x);
|
||||
bb.y0 = std::min(bb.y0, y);
|
||||
bb.y1 = std::max(bb.y1, y);
|
||||
};
|
||||
extend(dst_x, dst_y);
|
||||
return bb;
|
||||
}
|
||||
|
||||
// ---------------------------------------------------------------
|
||||
|
||||
bool Arch::place()
|
||||
{
|
||||
std::string placer = str_or_default(settings, id("placer"), defaultPlacer);
|
||||
if (placer == "heap") {
|
||||
bool have_iobuf_or_constr = false;
|
||||
for (auto cell : sorted(cells)) {
|
||||
CellInfo *ci = cell.second;
|
||||
if (ci->type == id("GENERIC_IOB") || ci->bel != BelId() || ci->attrs.count(id("BEL"))) {
|
||||
have_iobuf_or_constr = true;
|
||||
break;
|
||||
}
|
||||
}
|
||||
bool retVal;
|
||||
if (!have_iobuf_or_constr) {
|
||||
log_warning("Unable to use HeAP due to a lack of IO buffers or constrained cells as anchors; reverting to "
|
||||
"SA.\n");
|
||||
retVal = placer1(getCtx(), Placer1Cfg(getCtx()));
|
||||
} else {
|
||||
PlacerHeapCfg cfg(getCtx());
|
||||
cfg.ioBufTypes.insert(id("GENERIC_IOB"));
|
||||
retVal = placer_heap(getCtx(), cfg);
|
||||
}
|
||||
getCtx()->settings[getCtx()->id("place")] = 1;
|
||||
archInfoToAttributes();
|
||||
return retVal;
|
||||
} else if (placer == "sa") {
|
||||
bool retVal = placer1(getCtx(), Placer1Cfg(getCtx()));
|
||||
getCtx()->settings[getCtx()->id("place")] = 1;
|
||||
archInfoToAttributes();
|
||||
return retVal;
|
||||
} else {
|
||||
log_error("Generic architecture does not support placer '%s'\n", placer.c_str());
|
||||
}
|
||||
}
|
||||
|
||||
bool Arch::route()
|
||||
{
|
||||
std::string router = str_or_default(settings, id("router"), defaultRouter);
|
||||
bool result;
|
||||
if (router == "router1") {
|
||||
result = router1(getCtx(), Router1Cfg(getCtx()));
|
||||
} else if (router == "router2") {
|
||||
router2(getCtx(), Router2Cfg(getCtx()));
|
||||
result = true;
|
||||
} else {
|
||||
log_error("iCE40 architecture does not support router '%s'\n", router.c_str());
|
||||
}
|
||||
getCtx()->settings[getCtx()->id("route")] = 1;
|
||||
archInfoToAttributes();
|
||||
return result;
|
||||
}
|
||||
|
||||
// ---------------------------------------------------------------
|
||||
|
||||
const std::vector<GraphicElement> &Arch::getDecalGraphics(DecalId decal) const
|
||||
{
|
||||
if (!decal_graphics.count(decal)) {
|
||||
std::cerr << "No decal named " << decal.str(this) << std::endl;
|
||||
log_error("No decal named %s!\n", decal.c_str(this));
|
||||
}
|
||||
return decal_graphics.at(decal);
|
||||
}
|
||||
|
||||
DecalXY Arch::getBelDecal(BelId bel) const { return bels.at(bel).decalxy; }
|
||||
|
||||
DecalXY Arch::getWireDecal(WireId wire) const { return wires.at(wire).decalxy; }
|
||||
|
||||
DecalXY Arch::getPipDecal(PipId pip) const { return pips.at(pip).decalxy; }
|
||||
|
||||
DecalXY Arch::getGroupDecal(GroupId group) const { return groups.at(group).decalxy; }
|
||||
|
||||
// ---------------------------------------------------------------
|
||||
|
||||
bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayInfo &delay) const
|
||||
{
|
||||
if (!cellTiming.count(cell->name))
|
||||
return false;
|
||||
const auto &tmg = cellTiming.at(cell->name);
|
||||
auto fnd = tmg.combDelays.find(CellDelayKey{fromPort, toPort});
|
||||
if (fnd != tmg.combDelays.end()) {
|
||||
delay = fnd->second;
|
||||
return true;
|
||||
} else {
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
||||
// Get the port class, also setting clockPort if applicable
|
||||
TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, int &clockInfoCount) const
|
||||
{
|
||||
if (!cellTiming.count(cell->name))
|
||||
return TMG_IGNORE;
|
||||
const auto &tmg = cellTiming.at(cell->name);
|
||||
if (tmg.clockingInfo.count(port))
|
||||
clockInfoCount = int(tmg.clockingInfo.at(port).size());
|
||||
else
|
||||
clockInfoCount = 0;
|
||||
return get_or_default(tmg.portClasses, port, TMG_IGNORE);
|
||||
}
|
||||
|
||||
TimingClockingInfo Arch::getPortClockingInfo(const CellInfo *cell, IdString port, int index) const
|
||||
{
|
||||
NPNR_ASSERT(cellTiming.count(cell->name));
|
||||
const auto &tmg = cellTiming.at(cell->name);
|
||||
NPNR_ASSERT(tmg.clockingInfo.count(port));
|
||||
return tmg.clockingInfo.at(port).at(index);
|
||||
}
|
||||
|
||||
bool Arch::isValidBelForCell(CellInfo *cell, BelId bel) const
|
||||
{
|
||||
std::vector<const CellInfo *> cells;
|
||||
cells.push_back(cell);
|
||||
Loc loc = getBelLocation(bel);
|
||||
for (auto tbel : getBelsByTile(loc.x, loc.y)) {
|
||||
if (tbel == bel)
|
||||
continue;
|
||||
CellInfo *bound = getBoundBelCell(tbel);
|
||||
if (bound != nullptr)
|
||||
cells.push_back(bound);
|
||||
}
|
||||
return cellsCompatible(cells.data(), int(cells.size()));
|
||||
}
|
||||
|
||||
bool Arch::isBelLocationValid(BelId bel) const
|
||||
{
|
||||
std::vector<const CellInfo *> cells;
|
||||
Loc loc = getBelLocation(bel);
|
||||
for (auto tbel : getBelsByTile(loc.x, loc.y)) {
|
||||
CellInfo *bound = getBoundBelCell(tbel);
|
||||
if (bound != nullptr)
|
||||
cells.push_back(bound);
|
||||
}
|
||||
return cellsCompatible(cells.data(), int(cells.size()));
|
||||
}
|
||||
|
||||
#ifdef WITH_HEAP
|
||||
const std::string Arch::defaultPlacer = "heap";
|
||||
#else
|
||||
const std::string Arch::defaultPlacer = "sa";
|
||||
#endif
|
||||
|
||||
const std::vector<std::string> Arch::availablePlacers = {"sa",
|
||||
#ifdef WITH_HEAP
|
||||
"heap"
|
||||
#endif
|
||||
};
|
||||
|
||||
const std::string Arch::defaultRouter = "router1";
|
||||
const std::vector<std::string> Arch::availableRouters = {"router1", "router2"};
|
||||
|
||||
void Arch::assignArchInfo()
|
||||
{
|
||||
for (auto &cell : getCtx()->cells) {
|
||||
CellInfo *ci = cell.second.get();
|
||||
if (ci->type == id("GENERIC_SLICE")) {
|
||||
ci->is_slice = true;
|
||||
ci->slice_clk = get_net_or_empty(ci, id("CLK"));
|
||||
} else {
|
||||
ci->is_slice = false;
|
||||
}
|
||||
ci->user_group = int_or_default(ci->attrs, id("PACK_GROUP"), -1);
|
||||
}
|
||||
}
|
||||
|
||||
bool Arch::cellsCompatible(const CellInfo **cells, int count) const
|
||||
{
|
||||
const NetInfo *clk = nullptr;
|
||||
int group = -1;
|
||||
for (int i = 0; i < count; i++) {
|
||||
const CellInfo *ci = cells[i];
|
||||
if (ci->is_slice && ci->slice_clk != nullptr) {
|
||||
if (clk == nullptr)
|
||||
clk = ci->slice_clk;
|
||||
else if (clk != ci->slice_clk)
|
||||
return false;
|
||||
}
|
||||
if (ci->user_group != -1) {
|
||||
if (group == -1)
|
||||
group = ci->user_group;
|
||||
else if (group != ci->user_group)
|
||||
return false;
|
||||
}
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
||||
NEXTPNR_NAMESPACE_END
|
||||
371
gowin/arch.h
Normal file
371
gowin/arch.h
Normal file
@ -0,0 +1,371 @@
|
||||
/*
|
||||
* nextpnr -- Next Generation Place and Route
|
||||
*
|
||||
* Copyright (C) 2018 Clifford Wolf <clifford@symbioticeda.com>
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef NEXTPNR_H
|
||||
#error Include "arch.h" via "nextpnr.h" only.
|
||||
#endif
|
||||
|
||||
NEXTPNR_NAMESPACE_BEGIN
|
||||
|
||||
template <typename T> struct RelPtr
|
||||
{
|
||||
int32_t offset;
|
||||
|
||||
// void set(const T *ptr) {
|
||||
// offset = reinterpret_cast<const char*>(ptr) -
|
||||
// reinterpret_cast<const char*>(this);
|
||||
// }
|
||||
|
||||
const T *get() const { return reinterpret_cast<const T *>(reinterpret_cast<const char *>(this) + offset); }
|
||||
|
||||
const T &operator[](size_t index) const { return get()[index]; }
|
||||
|
||||
const T &operator*() const { return *(get()); }
|
||||
|
||||
const T *operator->() const { return get(); }
|
||||
|
||||
RelPtr(const RelPtr &) = delete;
|
||||
RelPtr &operator=(const RelPtr &) = delete;
|
||||
};
|
||||
|
||||
NPNR_PACKED_STRUCT(struct PairPOD {
|
||||
uint16_t dest_id;
|
||||
uint16_t src_id;
|
||||
});
|
||||
|
||||
NPNR_PACKED_STRUCT(struct BelsPOD {
|
||||
uint16_t type_id;
|
||||
uint16_t num_ports;
|
||||
RelPtr<PairPOD> ports;
|
||||
});
|
||||
|
||||
NPNR_PACKED_STRUCT(struct TilePOD /*TidePOD*/ {
|
||||
uint32_t num_bels;
|
||||
RelPtr<BelsPOD> bels;
|
||||
uint32_t num_pips;
|
||||
RelPtr<PairPOD> pips;
|
||||
uint32_t num_clock_pips;
|
||||
RelPtr<PairPOD> clock_pips;
|
||||
uint32_t num_aliases;
|
||||
RelPtr<PairPOD> aliases;
|
||||
});
|
||||
|
||||
NPNR_PACKED_STRUCT(struct GlobalAliasPOD {
|
||||
uint16_t dest_row;
|
||||
uint16_t dest_col;
|
||||
uint16_t dest_id;
|
||||
uint16_t src_row;
|
||||
uint16_t src_col;
|
||||
uint16_t src_id;
|
||||
});
|
||||
|
||||
NPNR_PACKED_STRUCT(struct DatabasePOD {
|
||||
RelPtr<char> family;
|
||||
uint32_t version;
|
||||
uint16_t rows;
|
||||
uint16_t cols;
|
||||
RelPtr<RelPtr<TilePOD>> grid;
|
||||
uint32_t num_aliases;
|
||||
RelPtr<GlobalAliasPOD> aliases;
|
||||
uint16_t num_constids;
|
||||
uint16_t num_ids;
|
||||
RelPtr<RelPtr<char>> id_strs;
|
||||
});
|
||||
|
||||
struct ArchArgs
|
||||
{
|
||||
std::string device;
|
||||
// Number of LUT inputs
|
||||
int K = 4;
|
||||
// y = mx + c relationship between distance and delay for interconnect
|
||||
// delay estimates
|
||||
double delayScale = 0.1, delayOffset = 0;
|
||||
};
|
||||
|
||||
struct WireInfo;
|
||||
|
||||
struct PipInfo
|
||||
{
|
||||
IdString name, type;
|
||||
std::map<IdString, std::string> attrs;
|
||||
NetInfo *bound_net;
|
||||
WireId srcWire, dstWire;
|
||||
DelayInfo delay;
|
||||
DecalXY decalxy;
|
||||
Loc loc;
|
||||
};
|
||||
|
||||
struct WireInfo
|
||||
{
|
||||
IdString name, type;
|
||||
std::map<IdString, std::string> attrs;
|
||||
NetInfo *bound_net;
|
||||
std::vector<PipId> downhill, uphill;
|
||||
BelPin uphill_bel_pin;
|
||||
std::vector<BelPin> downhill_bel_pins;
|
||||
std::vector<BelPin> bel_pins;
|
||||
DecalXY decalxy;
|
||||
int x, y;
|
||||
};
|
||||
|
||||
struct PinInfo
|
||||
{
|
||||
IdString name;
|
||||
WireId wire;
|
||||
PortType type;
|
||||
};
|
||||
|
||||
struct BelInfo
|
||||
{
|
||||
IdString name, type;
|
||||
std::map<IdString, std::string> attrs;
|
||||
CellInfo *bound_cell;
|
||||
std::unordered_map<IdString, PinInfo> pins;
|
||||
DecalXY decalxy;
|
||||
int x, y, z;
|
||||
bool gb;
|
||||
};
|
||||
|
||||
struct GroupInfo
|
||||
{
|
||||
IdString name;
|
||||
std::vector<BelId> bels;
|
||||
std::vector<WireId> wires;
|
||||
std::vector<PipId> pips;
|
||||
std::vector<GroupId> groups;
|
||||
DecalXY decalxy;
|
||||
};
|
||||
|
||||
struct CellDelayKey
|
||||
{
|
||||
IdString from, to;
|
||||
inline bool operator==(const CellDelayKey &other) const { return from == other.from && to == other.to; }
|
||||
};
|
||||
|
||||
NEXTPNR_NAMESPACE_END
|
||||
namespace std {
|
||||
template <> struct hash<NEXTPNR_NAMESPACE_PREFIX CellDelayKey>
|
||||
{
|
||||
std::size_t operator()(const NEXTPNR_NAMESPACE_PREFIX CellDelayKey &dk) const noexcept
|
||||
{
|
||||
std::size_t seed = std::hash<NEXTPNR_NAMESPACE_PREFIX IdString>()(dk.from);
|
||||
seed ^= std::hash<NEXTPNR_NAMESPACE_PREFIX IdString>()(dk.to) + 0x9e3779b9 + (seed << 6) + (seed >> 2);
|
||||
return seed;
|
||||
}
|
||||
};
|
||||
} // namespace std
|
||||
NEXTPNR_NAMESPACE_BEGIN
|
||||
|
||||
struct CellTiming
|
||||
{
|
||||
std::unordered_map<IdString, TimingPortClass> portClasses;
|
||||
std::unordered_map<CellDelayKey, DelayInfo> combDelays;
|
||||
std::unordered_map<IdString, std::vector<TimingClockingInfo>> clockingInfo;
|
||||
};
|
||||
|
||||
struct Arch : BaseCtx
|
||||
{
|
||||
std::string family;
|
||||
std::string device;
|
||||
std::string package;
|
||||
std::string speed;
|
||||
|
||||
std::unordered_map<IdString, WireInfo> wires;
|
||||
std::unordered_map<IdString, PipInfo> pips;
|
||||
std::unordered_map<IdString, BelInfo> bels;
|
||||
std::unordered_map<GroupId, GroupInfo> groups;
|
||||
|
||||
// These functions include useful errors if not found
|
||||
WireInfo &wire_info(IdString wire);
|
||||
PipInfo &pip_info(IdString wire);
|
||||
BelInfo &bel_info(IdString wire);
|
||||
|
||||
std::vector<IdString> bel_ids, wire_ids, pip_ids;
|
||||
|
||||
std::unordered_map<Loc, BelId> bel_by_loc;
|
||||
std::vector<std::vector<std::vector<BelId>>> bels_by_tile;
|
||||
|
||||
std::unordered_map<DecalId, std::vector<GraphicElement>> decal_graphics;
|
||||
|
||||
int gridDimX, gridDimY;
|
||||
std::vector<std::vector<int>> tileBelDimZ;
|
||||
std::vector<std::vector<int>> tilePipDimZ;
|
||||
|
||||
std::unordered_map<IdString, CellTiming> cellTiming;
|
||||
|
||||
void addWire(IdString name, IdString type, int x, int y);
|
||||
void addPip(IdString name, IdString type, IdString srcWire, IdString dstWire, DelayInfo delay, Loc loc);
|
||||
|
||||
void addBel(IdString name, IdString type, Loc loc, bool gb);
|
||||
void addBelInput(IdString bel, IdString name, IdString wire);
|
||||
void addBelOutput(IdString bel, IdString name, IdString wire);
|
||||
void addBelInout(IdString bel, IdString name, IdString wire);
|
||||
|
||||
void addGroupBel(IdString group, IdString bel);
|
||||
void addGroupWire(IdString group, IdString wire);
|
||||
void addGroupPip(IdString group, IdString pip);
|
||||
void addGroupGroup(IdString group, IdString grp);
|
||||
|
||||
void addDecalGraphic(DecalId decal, const GraphicElement &graphic);
|
||||
void setWireDecal(WireId wire, DecalXY decalxy);
|
||||
void setPipDecal(PipId pip, DecalXY decalxy);
|
||||
void setBelDecal(BelId bel, DecalXY decalxy);
|
||||
void setGroupDecal(GroupId group, DecalXY decalxy);
|
||||
|
||||
void setWireAttr(IdString wire, IdString key, const std::string &value);
|
||||
void setPipAttr(IdString pip, IdString key, const std::string &value);
|
||||
void setBelAttr(IdString bel, IdString key, const std::string &value);
|
||||
|
||||
void setLutK(int K);
|
||||
void setDelayScaling(double scale, double offset);
|
||||
|
||||
void addCellTimingClock(IdString cell, IdString port);
|
||||
void addCellTimingDelay(IdString cell, IdString fromPort, IdString toPort, DelayInfo delay);
|
||||
void addCellTimingSetupHold(IdString cell, IdString port, IdString clock, DelayInfo setup, DelayInfo hold);
|
||||
void addCellTimingClockToOut(IdString cell, IdString port, IdString clock, DelayInfo clktoq);
|
||||
|
||||
IdString wireToGlobal(int row, int col, const DatabasePOD* db, IdString wire);
|
||||
|
||||
// ---------------------------------------------------------------
|
||||
// Common Arch API. Every arch must provide the following methods.
|
||||
|
||||
ArchArgs args;
|
||||
Arch(ArchArgs args);
|
||||
|
||||
std::string getChipName() const { return device; }
|
||||
|
||||
IdString archId() const { return id("gowin"); }
|
||||
ArchArgs archArgs() const { return args; }
|
||||
IdString archArgsToId(ArchArgs args) const { return id("none"); }
|
||||
|
||||
int getGridDimX() const { return gridDimX; }
|
||||
int getGridDimY() const { return gridDimY; }
|
||||
int getTileBelDimZ(int x, int y) const { return tileBelDimZ[x][y]; }
|
||||
int getTilePipDimZ(int x, int y) const { return tilePipDimZ[x][y]; }
|
||||
|
||||
BelId getBelByName(IdString name) const;
|
||||
IdString getBelName(BelId bel) const;
|
||||
Loc getBelLocation(BelId bel) const;
|
||||
BelId getBelByLocation(Loc loc) const;
|
||||
const std::vector<BelId> &getBelsByTile(int x, int y) const;
|
||||
bool getBelGlobalBuf(BelId bel) const;
|
||||
uint32_t getBelChecksum(BelId bel) const;
|
||||
void bindBel(BelId bel, CellInfo *cell, PlaceStrength strength);
|
||||
void unbindBel(BelId bel);
|
||||
bool checkBelAvail(BelId bel) const;
|
||||
CellInfo *getBoundBelCell(BelId bel) const;
|
||||
CellInfo *getConflictingBelCell(BelId bel) const;
|
||||
const std::vector<BelId> &getBels() const;
|
||||
IdString getBelType(BelId bel) const;
|
||||
const std::map<IdString, std::string> &getBelAttrs(BelId bel) const;
|
||||
WireId getBelPinWire(BelId bel, IdString pin) const;
|
||||
PortType getBelPinType(BelId bel, IdString pin) const;
|
||||
std::vector<IdString> getBelPins(BelId bel) const;
|
||||
|
||||
WireId getWireByName(IdString name) const;
|
||||
IdString getWireName(WireId wire) const;
|
||||
IdString getWireType(WireId wire) const;
|
||||
const std::map<IdString, std::string> &getWireAttrs(WireId wire) const;
|
||||
uint32_t getWireChecksum(WireId wire) const;
|
||||
void bindWire(WireId wire, NetInfo *net, PlaceStrength strength);
|
||||
void unbindWire(WireId wire);
|
||||
bool checkWireAvail(WireId wire) const;
|
||||
NetInfo *getBoundWireNet(WireId wire) const;
|
||||
WireId getConflictingWireWire(WireId wire) const { return wire; }
|
||||
NetInfo *getConflictingWireNet(WireId wire) const;
|
||||
DelayInfo getWireDelay(WireId wire) const { return DelayInfo(); }
|
||||
const std::vector<WireId> &getWires() const;
|
||||
const std::vector<BelPin> &getWireBelPins(WireId wire) const;
|
||||
|
||||
PipId getPipByName(IdString name) const;
|
||||
IdString getPipName(PipId pip) const;
|
||||
IdString getPipType(PipId pip) const;
|
||||
const std::map<IdString, std::string> &getPipAttrs(PipId pip) const;
|
||||
uint32_t getPipChecksum(PipId pip) const;
|
||||
void bindPip(PipId pip, NetInfo *net, PlaceStrength strength);
|
||||
void unbindPip(PipId pip);
|
||||
bool checkPipAvail(PipId pip) const;
|
||||
NetInfo *getBoundPipNet(PipId pip) const;
|
||||
WireId getConflictingPipWire(PipId pip) const;
|
||||
NetInfo *getConflictingPipNet(PipId pip) const;
|
||||
const std::vector<PipId> &getPips() const;
|
||||
Loc getPipLocation(PipId pip) const;
|
||||
WireId getPipSrcWire(PipId pip) const;
|
||||
WireId getPipDstWire(PipId pip) const;
|
||||
DelayInfo getPipDelay(PipId pip) const;
|
||||
const std::vector<PipId> &getPipsDownhill(WireId wire) const;
|
||||
const std::vector<PipId> &getPipsUphill(WireId wire) const;
|
||||
|
||||
GroupId getGroupByName(IdString name) const;
|
||||
IdString getGroupName(GroupId group) const;
|
||||
std::vector<GroupId> getGroups() const;
|
||||
const std::vector<BelId> &getGroupBels(GroupId group) const;
|
||||
const std::vector<WireId> &getGroupWires(GroupId group) const;
|
||||
const std::vector<PipId> &getGroupPips(GroupId group) const;
|
||||
const std::vector<GroupId> &getGroupGroups(GroupId group) const;
|
||||
|
||||
delay_t estimateDelay(WireId src, WireId dst) const;
|
||||
delay_t predictDelay(const NetInfo *net_info, const PortRef &sink) const;
|
||||
delay_t getDelayEpsilon() const { return 0.001; }
|
||||
delay_t getRipupDelayPenalty() const { return 0.015; }
|
||||
float getDelayNS(delay_t v) const { return v; }
|
||||
|
||||
DelayInfo getDelayFromNS(float ns) const
|
||||
{
|
||||
DelayInfo del;
|
||||
del.delay = ns;
|
||||
return del;
|
||||
}
|
||||
|
||||
uint32_t getDelayChecksum(delay_t v) const { return 0; }
|
||||
bool getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t &budget) const;
|
||||
|
||||
ArcBounds getRouteBoundingBox(WireId src, WireId dst) const;
|
||||
|
||||
bool pack();
|
||||
bool place();
|
||||
bool route();
|
||||
|
||||
const std::vector<GraphicElement> &getDecalGraphics(DecalId decal) const;
|
||||
DecalXY getBelDecal(BelId bel) const;
|
||||
DecalXY getWireDecal(WireId wire) const;
|
||||
DecalXY getPipDecal(PipId pip) const;
|
||||
DecalXY getGroupDecal(GroupId group) const;
|
||||
|
||||
bool getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayInfo &delay) const;
|
||||
// Get the port class, also setting clockInfoCount to the number of TimingClockingInfos associated with a port
|
||||
TimingPortClass getPortTimingClass(const CellInfo *cell, IdString port, int &clockInfoCount) const;
|
||||
// Get the TimingClockingInfo of a port
|
||||
TimingClockingInfo getPortClockingInfo(const CellInfo *cell, IdString port, int index) const;
|
||||
|
||||
bool isValidBelForCell(CellInfo *cell, BelId bel) const;
|
||||
bool isBelLocationValid(BelId bel) const;
|
||||
|
||||
static const std::string defaultPlacer;
|
||||
static const std::vector<std::string> availablePlacers;
|
||||
static const std::string defaultRouter;
|
||||
static const std::vector<std::string> availableRouters;
|
||||
|
||||
// ---------------------------------------------------------------
|
||||
// Internal usage
|
||||
void assignArchInfo();
|
||||
bool cellsCompatible(const CellInfo **cells, int count) const;
|
||||
};
|
||||
|
||||
NEXTPNR_NAMESPACE_END
|
||||
237
gowin/arch_pybindings.cc
Normal file
237
gowin/arch_pybindings.cc
Normal file
@ -0,0 +1,237 @@
|
||||
/*
|
||||
* nextpnr -- Next Generation Place and Route
|
||||
*
|
||||
* Copyright (C) 2018 Clifford Wolf <clifford@symbioticeda.com>
|
||||
* Copyright (C) 2018 David Shah <dave@ds0.me>
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef NO_PYTHON
|
||||
|
||||
#include "arch_pybindings.h"
|
||||
#include "nextpnr.h"
|
||||
#include "pybindings.h"
|
||||
#include "pywrappers.h"
|
||||
|
||||
using namespace pybind11::literals;
|
||||
|
||||
NEXTPNR_NAMESPACE_BEGIN
|
||||
namespace PythonConversion {
|
||||
template <> struct string_converter<const IdString &>
|
||||
{
|
||||
const IdString &from_str(Context *ctx, std::string name) { NPNR_ASSERT_FALSE("unsupported"); }
|
||||
|
||||
std::string to_str(Context *ctx, const IdString &id) { return id.str(ctx); }
|
||||
};
|
||||
} // namespace PythonConversion
|
||||
|
||||
void arch_wrap_python(py::module &m)
|
||||
{
|
||||
using namespace PythonConversion;
|
||||
|
||||
auto arch_cls = py::class_<Arch, BaseCtx>(m, "Arch").def(py::init<ArchArgs>());
|
||||
|
||||
auto dxy_cls = py::class_<ContextualWrapper<DecalXY>>(m, "DecalXY_");
|
||||
readwrite_wrapper<DecalXY, decltype(&DecalXY::decal), &DecalXY::decal, conv_to_str<DecalId>,
|
||||
conv_from_str<DecalId>>::def_wrap(dxy_cls, "decal");
|
||||
readwrite_wrapper<DecalXY, decltype(&DecalXY::x), &DecalXY::x, pass_through<float>, pass_through<float>>::def_wrap(
|
||||
dxy_cls, "x");
|
||||
readwrite_wrapper<DecalXY, decltype(&DecalXY::y), &DecalXY::y, pass_through<float>, pass_through<float>>::def_wrap(
|
||||
dxy_cls, "y");
|
||||
|
||||
auto ctx_cls = py::class_<Context, Arch>(m, "Context")
|
||||
.def("checksum", &Context::checksum)
|
||||
.def("pack", &Context::pack)
|
||||
.def("place", &Context::place)
|
||||
.def("route", &Context::route);
|
||||
|
||||
py::class_<BelPin>(m, "BelPin").def_readwrite("bel", &BelPin::bel).def_readwrite("pin", &BelPin::pin);
|
||||
|
||||
py::class_<DelayInfo>(m, "DelayInfo").def("maxDelay", &DelayInfo::maxDelay).def("minDelay", &DelayInfo::minDelay);
|
||||
|
||||
fn_wrapper_1a<Context, decltype(&Context::getBelType), &Context::getBelType, conv_to_str<IdString>,
|
||||
conv_from_str<BelId>>::def_wrap(ctx_cls, "getBelType");
|
||||
fn_wrapper_1a<Context, decltype(&Context::checkBelAvail), &Context::checkBelAvail, pass_through<bool>,
|
||||
conv_from_str<BelId>>::def_wrap(ctx_cls, "checkBelAvail");
|
||||
fn_wrapper_1a<Context, decltype(&Context::getBelChecksum), &Context::getBelChecksum, pass_through<uint32_t>,
|
||||
conv_from_str<BelId>>::def_wrap(ctx_cls, "getBelChecksum");
|
||||
fn_wrapper_3a_v<Context, decltype(&Context::bindBel), &Context::bindBel, conv_from_str<BelId>,
|
||||
addr_and_unwrap<CellInfo>, pass_through<PlaceStrength>>::def_wrap(ctx_cls, "bindBel");
|
||||
fn_wrapper_1a_v<Context, decltype(&Context::unbindBel), &Context::unbindBel, conv_from_str<BelId>>::def_wrap(
|
||||
ctx_cls, "unbindBel");
|
||||
fn_wrapper_1a<Context, decltype(&Context::getBoundBelCell), &Context::getBoundBelCell, deref_and_wrap<CellInfo>,
|
||||
conv_from_str<BelId>>::def_wrap(ctx_cls, "getBoundBelCell");
|
||||
fn_wrapper_1a<Context, decltype(&Context::getConflictingBelCell), &Context::getConflictingBelCell,
|
||||
deref_and_wrap<CellInfo>, conv_from_str<BelId>>::def_wrap(ctx_cls, "getConflictingBelCell");
|
||||
fn_wrapper_0a<Context, decltype(&Context::getBels), &Context::getBels,
|
||||
wrap_context<const std::vector<BelId> &>>::def_wrap(ctx_cls, "getBels");
|
||||
|
||||
fn_wrapper_2a<Context, decltype(&Context::getBelPinWire), &Context::getBelPinWire, conv_to_str<WireId>,
|
||||
conv_from_str<BelId>, conv_from_str<IdString>>::def_wrap(ctx_cls, "getBelPinWire");
|
||||
fn_wrapper_1a<Context, decltype(&Context::getWireBelPins), &Context::getWireBelPins,
|
||||
wrap_context<const std::vector<BelPin> &>, conv_from_str<WireId>>::def_wrap(ctx_cls,
|
||||
"getWireBelPins");
|
||||
|
||||
fn_wrapper_1a<Context, decltype(&Context::getWireChecksum), &Context::getWireChecksum, pass_through<uint32_t>,
|
||||
conv_from_str<WireId>>::def_wrap(ctx_cls, "getWireChecksum");
|
||||
fn_wrapper_3a_v<Context, decltype(&Context::bindWire), &Context::bindWire, conv_from_str<WireId>,
|
||||
addr_and_unwrap<NetInfo>, pass_through<PlaceStrength>>::def_wrap(ctx_cls, "bindWire");
|
||||
fn_wrapper_1a_v<Context, decltype(&Context::unbindWire), &Context::unbindWire, conv_from_str<WireId>>::def_wrap(
|
||||
ctx_cls, "unbindWire");
|
||||
fn_wrapper_1a<Context, decltype(&Context::checkWireAvail), &Context::checkWireAvail, pass_through<bool>,
|
||||
conv_from_str<WireId>>::def_wrap(ctx_cls, "checkWireAvail");
|
||||
fn_wrapper_1a<Context, decltype(&Context::getBoundWireNet), &Context::getBoundWireNet, deref_and_wrap<NetInfo>,
|
||||
conv_from_str<WireId>>::def_wrap(ctx_cls, "getBoundWireNet");
|
||||
fn_wrapper_1a<Context, decltype(&Context::getConflictingWireNet), &Context::getConflictingWireNet,
|
||||
deref_and_wrap<NetInfo>, conv_from_str<WireId>>::def_wrap(ctx_cls, "getConflictingWireNet");
|
||||
|
||||
fn_wrapper_0a<Context, decltype(&Context::getWires), &Context::getWires,
|
||||
wrap_context<const std::vector<WireId> &>>::def_wrap(ctx_cls, "getWires");
|
||||
|
||||
fn_wrapper_0a<Context, decltype(&Context::getPips), &Context::getPips,
|
||||
wrap_context<const std::vector<PipId> &>>::def_wrap(ctx_cls, "getPips");
|
||||
fn_wrapper_1a<Context, decltype(&Context::getPipChecksum), &Context::getPipChecksum, pass_through<uint32_t>,
|
||||
conv_from_str<PipId>>::def_wrap(ctx_cls, "getPipChecksum");
|
||||
fn_wrapper_3a_v<Context, decltype(&Context::bindPip), &Context::bindPip, conv_from_str<PipId>,
|
||||
addr_and_unwrap<NetInfo>, pass_through<PlaceStrength>>::def_wrap(ctx_cls, "bindPip");
|
||||
fn_wrapper_1a_v<Context, decltype(&Context::unbindPip), &Context::unbindPip, conv_from_str<PipId>>::def_wrap(
|
||||
ctx_cls, "unbindPip");
|
||||
fn_wrapper_1a<Context, decltype(&Context::checkPipAvail), &Context::checkPipAvail, pass_through<bool>,
|
||||
conv_from_str<PipId>>::def_wrap(ctx_cls, "checkPipAvail");
|
||||
fn_wrapper_1a<Context, decltype(&Context::getBoundPipNet), &Context::getBoundPipNet, deref_and_wrap<NetInfo>,
|
||||
conv_from_str<PipId>>::def_wrap(ctx_cls, "getBoundPipNet");
|
||||
fn_wrapper_1a<Context, decltype(&Context::getConflictingPipNet), &Context::getConflictingPipNet,
|
||||
deref_and_wrap<NetInfo>, conv_from_str<PipId>>::def_wrap(ctx_cls, "getConflictingPipNet");
|
||||
|
||||
fn_wrapper_1a<Context, decltype(&Context::getPipsDownhill), &Context::getPipsDownhill,
|
||||
wrap_context<const std::vector<PipId> &>, conv_from_str<WireId>>::def_wrap(ctx_cls,
|
||||
"getPipsDownhill");
|
||||
fn_wrapper_1a<Context, decltype(&Context::getPipsUphill), &Context::getPipsUphill,
|
||||
wrap_context<const std::vector<PipId> &>, conv_from_str<WireId>>::def_wrap(ctx_cls, "getPipsUphill");
|
||||
|
||||
fn_wrapper_1a<Context, decltype(&Context::getPipSrcWire), &Context::getPipSrcWire, conv_to_str<WireId>,
|
||||
conv_from_str<PipId>>::def_wrap(ctx_cls, "getPipSrcWire");
|
||||
fn_wrapper_1a<Context, decltype(&Context::getPipDstWire), &Context::getPipDstWire, conv_to_str<WireId>,
|
||||
conv_from_str<PipId>>::def_wrap(ctx_cls, "getPipDstWire");
|
||||
fn_wrapper_1a<Context, decltype(&Context::getPipDelay), &Context::getPipDelay, pass_through<DelayInfo>,
|
||||
conv_from_str<PipId>>::def_wrap(ctx_cls, "getPipDelay");
|
||||
|
||||
fn_wrapper_1a<Context, decltype(&Context::getDelayFromNS), &Context::getDelayFromNS, pass_through<DelayInfo>,
|
||||
pass_through<double>>::def_wrap(ctx_cls, "getDelayFromNS");
|
||||
|
||||
fn_wrapper_0a<Context, decltype(&Context::getChipName), &Context::getChipName, pass_through<std::string>>::def_wrap(
|
||||
ctx_cls, "getChipName");
|
||||
fn_wrapper_0a<Context, decltype(&Context::archId), &Context::archId, conv_to_str<IdString>>::def_wrap(ctx_cls,
|
||||
"archId");
|
||||
|
||||
fn_wrapper_3a<Context, decltype(&Context::constructDecalXY), &Context::constructDecalXY, wrap_context<DecalXY>,
|
||||
conv_from_str<DecalId>, pass_through<float>, pass_through<float>>::def_wrap(ctx_cls, "DecalXY");
|
||||
|
||||
typedef std::unordered_map<IdString, std::unique_ptr<CellInfo>> CellMap;
|
||||
typedef std::unordered_map<IdString, std::unique_ptr<NetInfo>> NetMap;
|
||||
typedef std::unordered_map<IdString, HierarchicalCell> HierarchyMap;
|
||||
|
||||
readonly_wrapper<Context, decltype(&Context::cells), &Context::cells, wrap_context<CellMap &>>::def_wrap(ctx_cls,
|
||||
"cells");
|
||||
readonly_wrapper<Context, decltype(&Context::nets), &Context::nets, wrap_context<NetMap &>>::def_wrap(ctx_cls,
|
||||
"nets");
|
||||
|
||||
fn_wrapper_2a_v<Context, decltype(&Context::addClock), &Context::addClock, conv_from_str<IdString>,
|
||||
pass_through<float>>::def_wrap(ctx_cls, "addClock");
|
||||
|
||||
// Generic arch construction API
|
||||
fn_wrapper_4a_v<Context, decltype(&Context::addWire), &Context::addWire, conv_from_str<IdString>,
|
||||
conv_from_str<IdString>, pass_through<int>, pass_through<int>>::def_wrap(ctx_cls, "addWire",
|
||||
"name"_a, "type"_a, "x"_a,
|
||||
"y"_a);
|
||||
fn_wrapper_6a_v<Context, decltype(&Context::addPip), &Context::addPip, conv_from_str<IdString>,
|
||||
conv_from_str<IdString>, conv_from_str<IdString>, conv_from_str<IdString>, pass_through<DelayInfo>,
|
||||
pass_through<Loc>>::def_wrap(ctx_cls, "addPip", "name"_a, "type"_a, "srcWire"_a, "dstWire"_a,
|
||||
"delay"_a, "loc"_a);
|
||||
|
||||
fn_wrapper_4a_v<Context, decltype(&Context::addBel), &Context::addBel, conv_from_str<IdString>,
|
||||
conv_from_str<IdString>, pass_through<Loc>, pass_through<bool>>::def_wrap(ctx_cls, "addBel",
|
||||
"name"_a, "type"_a,
|
||||
"loc"_a, "gb"_a);
|
||||
fn_wrapper_3a_v<Context, decltype(&Context::addBelInput), &Context::addBelInput, conv_from_str<IdString>,
|
||||
conv_from_str<IdString>, conv_from_str<IdString>>::def_wrap(ctx_cls, "addBelInput", "bel"_a,
|
||||
"name"_a, "wire"_a);
|
||||
fn_wrapper_3a_v<Context, decltype(&Context::addBelOutput), &Context::addBelOutput, conv_from_str<IdString>,
|
||||
conv_from_str<IdString>, conv_from_str<IdString>>::def_wrap(ctx_cls, "addBelOutput", "bel"_a,
|
||||
"name"_a, "wire"_a);
|
||||
fn_wrapper_3a_v<Context, decltype(&Context::addBelInout), &Context::addBelInout, conv_from_str<IdString>,
|
||||
conv_from_str<IdString>, conv_from_str<IdString>>::def_wrap(ctx_cls, "addBelInout", "bel"_a,
|
||||
"name"_a, "wire"_a);
|
||||
|
||||
fn_wrapper_2a_v<Context, decltype(&Context::addGroupBel), &Context::addGroupBel, conv_from_str<IdString>,
|
||||
conv_from_str<IdString>>::def_wrap(ctx_cls, "addGroupBel", "group"_a, "bel"_a);
|
||||
fn_wrapper_2a_v<Context, decltype(&Context::addGroupWire), &Context::addGroupWire, conv_from_str<IdString>,
|
||||
conv_from_str<IdString>>::def_wrap(ctx_cls, "addGroupWire", "group"_a, "wire"_a);
|
||||
fn_wrapper_2a_v<Context, decltype(&Context::addGroupPip), &Context::addGroupPip, conv_from_str<IdString>,
|
||||
conv_from_str<IdString>>::def_wrap(ctx_cls, "addGroupPip", "group"_a, "pip"_a);
|
||||
fn_wrapper_2a_v<Context, decltype(&Context::addGroupGroup), &Context::addGroupPip, conv_from_str<IdString>,
|
||||
conv_from_str<IdString>>::def_wrap(ctx_cls, "addGroupGroup", "group"_a, "grp"_a);
|
||||
|
||||
fn_wrapper_2a_v<Context, decltype(&Context::addDecalGraphic), &Context::addDecalGraphic, conv_from_str<DecalId>,
|
||||
pass_through<GraphicElement>>::def_wrap(ctx_cls, "addDecalGraphic", (py::arg("decal"), "graphic"));
|
||||
fn_wrapper_2a_v<Context, decltype(&Context::setWireDecal), &Context::setWireDecal, conv_from_str<DecalId>,
|
||||
unwrap_context<DecalXY>>::def_wrap(ctx_cls, "setWireDecal", "wire"_a, "decalxy"_a);
|
||||
fn_wrapper_2a_v<Context, decltype(&Context::setPipDecal), &Context::setPipDecal, conv_from_str<DecalId>,
|
||||
unwrap_context<DecalXY>>::def_wrap(ctx_cls, "setPipDecal", "pip"_a, "decalxy"_a);
|
||||
fn_wrapper_2a_v<Context, decltype(&Context::setBelDecal), &Context::setBelDecal, conv_from_str<DecalId>,
|
||||
unwrap_context<DecalXY>>::def_wrap(ctx_cls, "setBelDecal", "bel"_a, "decalxy"_a);
|
||||
fn_wrapper_2a_v<Context, decltype(&Context::setGroupDecal), &Context::setGroupDecal, conv_from_str<DecalId>,
|
||||
unwrap_context<DecalXY>>::def_wrap(ctx_cls, "setGroupDecal", "group"_a, "decalxy"_a);
|
||||
|
||||
fn_wrapper_3a_v<Context, decltype(&Context::setWireAttr), &Context::setWireAttr, conv_from_str<DecalId>,
|
||||
conv_from_str<IdString>, pass_through<std::string>>::def_wrap(ctx_cls, "setWireAttr", "wire"_a,
|
||||
"key"_a, "value"_a);
|
||||
fn_wrapper_3a_v<Context, decltype(&Context::setBelAttr), &Context::setBelAttr, conv_from_str<DecalId>,
|
||||
conv_from_str<IdString>, pass_through<std::string>>::def_wrap(ctx_cls, "setBelAttr", "bel"_a,
|
||||
"key"_a, "value"_a);
|
||||
fn_wrapper_3a_v<Context, decltype(&Context::setPipAttr), &Context::setPipAttr, conv_from_str<DecalId>,
|
||||
conv_from_str<IdString>, pass_through<std::string>>::def_wrap(ctx_cls, "setPipAttr", "pip"_a,
|
||||
"key"_a, "value"_a);
|
||||
|
||||
fn_wrapper_1a_v<Context, decltype(&Context::setLutK), &Context::setLutK, pass_through<int>>::def_wrap(
|
||||
ctx_cls, "setLutK", "K"_a);
|
||||
fn_wrapper_2a_v<Context, decltype(&Context::setDelayScaling), &Context::setDelayScaling, pass_through<double>,
|
||||
pass_through<double>>::def_wrap(ctx_cls, "setDelayScaling", "scale"_a, "offset"_a);
|
||||
|
||||
fn_wrapper_2a_v<Context, decltype(&Context::addCellTimingClock), &Context::addCellTimingClock,
|
||||
conv_from_str<IdString>, conv_from_str<IdString>>::def_wrap(ctx_cls, "addCellTimingClock", "cell"_a,
|
||||
"port"_a);
|
||||
fn_wrapper_4a_v<Context, decltype(&Context::addCellTimingDelay), &Context::addCellTimingDelay,
|
||||
conv_from_str<IdString>, conv_from_str<IdString>, conv_from_str<IdString>,
|
||||
pass_through<DelayInfo>>::def_wrap(ctx_cls, "addCellTimingDelay", "cell"_a, "fromPort"_a,
|
||||
"toPort"_a, "delay"_a);
|
||||
fn_wrapper_5a_v<Context, decltype(&Context::addCellTimingSetupHold), &Context::addCellTimingSetupHold,
|
||||
conv_from_str<IdString>, conv_from_str<IdString>, conv_from_str<IdString>, pass_through<DelayInfo>,
|
||||
pass_through<DelayInfo>>::def_wrap(ctx_cls, "addCellTimingSetupHold", "cell"_a, "port"_a, "clock"_a,
|
||||
"setup"_a, "hold"_a);
|
||||
fn_wrapper_4a_v<Context, decltype(&Context::addCellTimingClockToOut), &Context::addCellTimingClockToOut,
|
||||
conv_from_str<IdString>, conv_from_str<IdString>, conv_from_str<IdString>,
|
||||
pass_through<DelayInfo>>::def_wrap(ctx_cls, "addCellTimingClockToOut", "cell"_a, "port"_a,
|
||||
"clock"_a, "clktoq"_a);
|
||||
|
||||
WRAP_MAP_UPTR(m, CellMap, "IdCellMap");
|
||||
WRAP_MAP_UPTR(m, NetMap, "IdNetMap");
|
||||
WRAP_MAP(m, HierarchyMap, wrap_context<HierarchicalCell &>, "HierarchyMap");
|
||||
WRAP_VECTOR(m, const std::vector<IdString>, conv_to_str<IdString>);
|
||||
}
|
||||
|
||||
NEXTPNR_NAMESPACE_END
|
||||
|
||||
#endif
|
||||
31
gowin/arch_pybindings.h
Normal file
31
gowin/arch_pybindings.h
Normal file
@ -0,0 +1,31 @@
|
||||
/*
|
||||
* nextpnr -- Next Generation Place and Route
|
||||
*
|
||||
* Copyright (C) 2018 Clifford Wolf <clifford@symbioticeda.com>
|
||||
* Copyright (C) 2018 David Shah <david@symbioticeda.com>
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
#ifndef ARCH_PYBINDINGS_H
|
||||
#define ARCH_PYBINDINGS_H
|
||||
#ifndef NO_PYTHON
|
||||
|
||||
#include "nextpnr.h"
|
||||
#include "pybindings.h"
|
||||
|
||||
NEXTPNR_NAMESPACE_BEGIN
|
||||
|
||||
NEXTPNR_NAMESPACE_END
|
||||
#endif
|
||||
#endif
|
||||
72
gowin/archdefs.h
Normal file
72
gowin/archdefs.h
Normal file
@ -0,0 +1,72 @@
|
||||
/*
|
||||
* nextpnr -- Next Generation Place and Route
|
||||
*
|
||||
* Copyright (C) 2018 Clifford Wolf <clifford@symbioticeda.com>
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef NEXTPNR_H
|
||||
#error Include "archdefs.h" via "nextpnr.h" only.
|
||||
#endif
|
||||
|
||||
NEXTPNR_NAMESPACE_BEGIN
|
||||
|
||||
typedef float delay_t;
|
||||
|
||||
struct DelayInfo
|
||||
{
|
||||
delay_t delay = 0;
|
||||
|
||||
delay_t minRaiseDelay() const { return delay; }
|
||||
delay_t maxRaiseDelay() const { return delay; }
|
||||
|
||||
delay_t minFallDelay() const { return delay; }
|
||||
delay_t maxFallDelay() const { return delay; }
|
||||
|
||||
delay_t minDelay() const { return delay; }
|
||||
delay_t maxDelay() const { return delay; }
|
||||
|
||||
DelayInfo operator+(const DelayInfo &other) const
|
||||
{
|
||||
DelayInfo ret;
|
||||
ret.delay = this->delay + other.delay;
|
||||
return ret;
|
||||
}
|
||||
};
|
||||
|
||||
typedef IdString BelId;
|
||||
typedef IdString WireId;
|
||||
typedef IdString PipId;
|
||||
typedef IdString GroupId;
|
||||
typedef IdString DecalId;
|
||||
|
||||
struct ArchNetInfo
|
||||
{
|
||||
};
|
||||
|
||||
struct NetInfo;
|
||||
|
||||
struct ArchCellInfo
|
||||
{
|
||||
// Custom grouping set via "PACK_GROUP" attribute. All cells with the same group
|
||||
// value may share a tile (-1 = don't care, default if not set)
|
||||
int user_group;
|
||||
// Is a slice type primitive
|
||||
bool is_slice;
|
||||
// Only packing rule for slice type primitives is a single clock per tile
|
||||
const NetInfo *slice_clk;
|
||||
};
|
||||
|
||||
NEXTPNR_NAMESPACE_END
|
||||
147
gowin/cells.cc
Normal file
147
gowin/cells.cc
Normal file
@ -0,0 +1,147 @@
|
||||
/*
|
||||
* nextpnr -- Next Generation Place and Route
|
||||
*
|
||||
* Copyright (C) 2019 David Shah <david@symbioticeda.com>
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#include "cells.h"
|
||||
#include "design_utils.h"
|
||||
#include "log.h"
|
||||
#include "util.h"
|
||||
|
||||
NEXTPNR_NAMESPACE_BEGIN
|
||||
|
||||
void add_port(const Context *ctx, CellInfo *cell, std::string name, PortType dir)
|
||||
{
|
||||
IdString id = ctx->id(name);
|
||||
NPNR_ASSERT(cell->ports.count(id) == 0);
|
||||
cell->ports[id] = PortInfo{id, nullptr, dir};
|
||||
}
|
||||
|
||||
std::unique_ptr<CellInfo> create_generic_cell(Context *ctx, IdString type, std::string name)
|
||||
{
|
||||
static int auto_idx = 0;
|
||||
std::unique_ptr<CellInfo> new_cell = std::unique_ptr<CellInfo>(new CellInfo());
|
||||
if (name.empty()) {
|
||||
new_cell->name = ctx->id("$nextpnr_" + type.str(ctx) + "_" + std::to_string(auto_idx++));
|
||||
} else {
|
||||
new_cell->name = ctx->id(name);
|
||||
}
|
||||
new_cell->type = type;
|
||||
if (type == ctx->id("GENERIC_SLICE")) {
|
||||
new_cell->params[ctx->id("K")] = ctx->args.K;
|
||||
new_cell->params[ctx->id("INIT")] = 0;
|
||||
new_cell->params[ctx->id("FF_USED")] = 0;
|
||||
|
||||
for (int i = 0; i < ctx->args.K; i++)
|
||||
add_port(ctx, new_cell.get(), "I[" + std::to_string(i) + "]", PORT_IN);
|
||||
|
||||
add_port(ctx, new_cell.get(), "CLK", PORT_IN);
|
||||
|
||||
add_port(ctx, new_cell.get(), "F", PORT_OUT);
|
||||
add_port(ctx, new_cell.get(), "Q", PORT_OUT);
|
||||
} else if (type == ctx->id("GENERIC_IOB")) {
|
||||
new_cell->params[ctx->id("INPUT_USED")] = 0;
|
||||
new_cell->params[ctx->id("OUTPUT_USED")] = 0;
|
||||
new_cell->params[ctx->id("ENABLE_USED")] = 0;
|
||||
|
||||
add_port(ctx, new_cell.get(), "PAD", PORT_INOUT);
|
||||
add_port(ctx, new_cell.get(), "I", PORT_IN);
|
||||
add_port(ctx, new_cell.get(), "EN", PORT_IN);
|
||||
add_port(ctx, new_cell.get(), "O", PORT_OUT);
|
||||
} else {
|
||||
log_error("unable to create generic cell of type %s", type.c_str(ctx));
|
||||
}
|
||||
return new_cell;
|
||||
}
|
||||
|
||||
void lut_to_lc(const Context *ctx, CellInfo *lut, CellInfo *lc, bool no_dff)
|
||||
{
|
||||
lc->params[ctx->id("INIT")] = lut->params[ctx->id("INIT")];
|
||||
|
||||
int lut_k = int_or_default(lut->params, ctx->id("K"), 4);
|
||||
NPNR_ASSERT(lut_k <= ctx->args.K);
|
||||
|
||||
for (int i = 0; i < lut_k; i++) {
|
||||
IdString port = ctx->id("I[" + std::to_string(i) + "]");
|
||||
replace_port(lut, port, lc, port);
|
||||
}
|
||||
|
||||
if (no_dff) {
|
||||
lc->params[ctx->id("FF_USED")] = 0;
|
||||
replace_port(lut, ctx->id("Q"), lc, ctx->id("F"));
|
||||
}
|
||||
}
|
||||
|
||||
void dff_to_lc(const Context *ctx, CellInfo *dff, CellInfo *lc, bool pass_thru_lut)
|
||||
{
|
||||
lc->params[ctx->id("FF_USED")] = 1;
|
||||
replace_port(dff, ctx->id("CLK"), lc, ctx->id("CLK"));
|
||||
|
||||
if (pass_thru_lut) {
|
||||
// Fill LUT with alternating 10
|
||||
const int init_size = 1 << lc->params[ctx->id("K")].as_int64();
|
||||
std::string init;
|
||||
init.reserve(init_size);
|
||||
for (int i = 0; i < init_size; i += 2)
|
||||
init.append("10");
|
||||
lc->params[ctx->id("INIT")] = Property::from_string(init);
|
||||
|
||||
replace_port(dff, ctx->id("D"), lc, ctx->id("I[0]"));
|
||||
}
|
||||
|
||||
replace_port(dff, ctx->id("Q"), lc, ctx->id("Q"));
|
||||
}
|
||||
|
||||
void nxio_to_iob(Context *ctx, CellInfo *nxio, CellInfo *iob, std::unordered_set<IdString> &todelete_cells)
|
||||
{
|
||||
if (nxio->type == ctx->id("$nextpnr_ibuf")) {
|
||||
iob->params[ctx->id("INPUT_USED")] = 1;
|
||||
replace_port(nxio, ctx->id("O"), iob, ctx->id("O"));
|
||||
} else if (nxio->type == ctx->id("$nextpnr_obuf")) {
|
||||
iob->params[ctx->id("OUTPUT_USED")] = 1;
|
||||
replace_port(nxio, ctx->id("I"), iob, ctx->id("I"));
|
||||
} else if (nxio->type == ctx->id("$nextpnr_iobuf")) {
|
||||
// N.B. tristate will be dealt with below
|
||||
iob->params[ctx->id("INPUT_USED")] = 1;
|
||||
iob->params[ctx->id("OUTPUT_USED")] = 1;
|
||||
replace_port(nxio, ctx->id("I"), iob, ctx->id("I"));
|
||||
replace_port(nxio, ctx->id("O"), iob, ctx->id("O"));
|
||||
} else {
|
||||
NPNR_ASSERT(false);
|
||||
}
|
||||
NetInfo *donet = iob->ports.at(ctx->id("I")).net;
|
||||
CellInfo *tbuf = net_driven_by(
|
||||
ctx, donet, [](const Context *ctx, const CellInfo *cell) { return cell->type == ctx->id("$_TBUF_"); },
|
||||
ctx->id("Y"));
|
||||
if (tbuf) {
|
||||
iob->params[ctx->id("ENABLE_USED")] = 1;
|
||||
replace_port(tbuf, ctx->id("A"), iob, ctx->id("I"));
|
||||
replace_port(tbuf, ctx->id("E"), iob, ctx->id("EN"));
|
||||
|
||||
if (donet->users.size() > 1) {
|
||||
for (auto user : donet->users)
|
||||
log_info(" remaining tristate user: %s.%s\n", user.cell->name.c_str(ctx), user.port.c_str(ctx));
|
||||
log_error("unsupported tristate IO pattern for IO buffer '%s', "
|
||||
"instantiate GENERIC_IOB manually to ensure correct behaviour\n",
|
||||
nxio->name.c_str(ctx));
|
||||
}
|
||||
ctx->nets.erase(donet->name);
|
||||
todelete_cells.insert(tbuf->name);
|
||||
}
|
||||
}
|
||||
|
||||
NEXTPNR_NAMESPACE_END
|
||||
55
gowin/cells.h
Normal file
55
gowin/cells.h
Normal file
@ -0,0 +1,55 @@
|
||||
/*
|
||||
* nextpnr -- Next Generation Place and Route
|
||||
*
|
||||
* Copyright (C) 2019 David Shah <david@symbioticeda.com>
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#include "nextpnr.h"
|
||||
|
||||
#ifndef GENERIC_CELLS_H
|
||||
#define GENERIC_CELLS_H
|
||||
|
||||
NEXTPNR_NAMESPACE_BEGIN
|
||||
|
||||
// Create a generic arch cell and return it
|
||||
// Name will be automatically assigned if not specified
|
||||
std::unique_ptr<CellInfo> create_generic_cell(Context *ctx, IdString type, std::string name = "");
|
||||
|
||||
// Return true if a cell is a LUT
|
||||
inline bool is_lut(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == ctx->id("LUT"); }
|
||||
|
||||
// Return true if a cell is a flipflop
|
||||
inline bool is_ff(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == ctx->id("DFF"); }
|
||||
|
||||
inline bool is_lc(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == ctx->id("GENERIC_SLICE"); }
|
||||
|
||||
// Convert a LUT primitive to (part of) an GENERIC_SLICE, swapping ports
|
||||
// as needed. Set no_dff if a DFF is not being used, so that the output
|
||||
// can be reconnected
|
||||
void lut_to_lc(const Context *ctx, CellInfo *lut, CellInfo *lc, bool no_dff = true);
|
||||
|
||||
// Convert a DFF primitive to (part of) an GENERIC_SLICE, setting parameters
|
||||
// and reconnecting signals as necessary. If pass_thru_lut is True, the LUT will
|
||||
// be configured as pass through and D connected to I0, otherwise D will be
|
||||
// ignored
|
||||
void dff_to_lc(const Context *ctx, CellInfo *dff, CellInfo *lc, bool pass_thru_lut = false);
|
||||
|
||||
// Convert a nextpnr IO buffer to a GENERIC_IOB
|
||||
void nxio_to_iob(Context *ctx, CellInfo *nxio, CellInfo *sbio, std::unordered_set<IdString> &todelete_cells);
|
||||
|
||||
NEXTPNR_NAMESPACE_END
|
||||
|
||||
#endif
|
||||
53
gowin/family.cmake
Normal file
53
gowin/family.cmake
Normal file
@ -0,0 +1,53 @@
|
||||
add_subdirectory(${family})
|
||||
message(STATUS "Using Gowin chipdb: ${GOWIN_CHIPDB}")
|
||||
|
||||
set(chipdb_sources)
|
||||
set(chipdb_binaries)
|
||||
file(MAKE_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR}/${family}/chipdb)
|
||||
foreach(device ${GOWIN_DEVICES})
|
||||
set(chipdb_bba ${GOWIN_CHIPDB}/chipdb-${device}.bba)
|
||||
set(chipdb_bin ${family}/chipdb/chipdb-${device}.bin)
|
||||
set(chipdb_cc ${family}/chipdb/chipdb-${device}.cc)
|
||||
if(BBASM_MODE STREQUAL "binary")
|
||||
add_custom_command(
|
||||
OUTPUT ${chipdb_bin}
|
||||
COMMAND bbasm ${BBASM_ENDIAN_FLAG} ${chipdb_bba} ${chipdb_bin}
|
||||
DEPENDS bbasm chipdb-${family}-bbas ${chipdb_bba})
|
||||
list(APPEND chipdb_binaries ${chipdb_bin})
|
||||
elseif(BBASM_MODE STREQUAL "embed")
|
||||
add_custom_command(
|
||||
OUTPUT ${chipdb_cc} ${chipdb_bin}
|
||||
COMMAND bbasm ${BBASM_ENDIAN_FLAG} --e ${chipdb_bba} ${chipdb_cc} ${chipdb_bin}
|
||||
DEPENDS bbasm chipdb-${family}-bbas ${chipdb_bba})
|
||||
list(APPEND chipdb_sources ${chipdb_cc})
|
||||
list(APPEND chipdb_binaries ${chipdb_bin})
|
||||
elseif(BBASM_MODE STREQUAL "string")
|
||||
add_custom_command(
|
||||
OUTPUT ${chipdb_cc}
|
||||
COMMAND bbasm ${BBASM_ENDIAN_FLAG} --c ${chipdb_bba} ${chipdb_cc}
|
||||
DEPENDS bbasm chipdb-${family}-bbas ${chipdb_bba})
|
||||
list(APPEND chipdb_sources ${chipdb_cc})
|
||||
endif()
|
||||
endforeach()
|
||||
if(WIN32)
|
||||
set(chipdb_rc ${CMAKE_CURRENT_BINARY_DIR}/${family}/resource/chipdb.rc)
|
||||
list(APPEND chipdb_sources ${chipdb_rc})
|
||||
|
||||
file(WRITE ${chipdb_rc})
|
||||
foreach(device ${GOWIN_DEVICES})
|
||||
file(APPEND ${chipdb_rc}
|
||||
"${family}/chipdb-${device}.bin RCDATA \"${CMAKE_CURRENT_BINARY_DIR}/${family}/chipdb/chipdb-${device}.bin\"")
|
||||
endforeach()
|
||||
endif()
|
||||
|
||||
add_custom_target(chipdb-${family}-bins DEPENDS ${chipdb_sources} ${chipdb_binaries})
|
||||
|
||||
add_library(chipdb-${family} OBJECT ${GOWIN_CHIPDB} ${chipdb_sources})
|
||||
add_dependencies(chipdb-${family} chipdb-${family}-bins)
|
||||
target_compile_options(chipdb-${family} PRIVATE -g0 -O0 -w)
|
||||
target_compile_definitions(chipdb-${family} PRIVATE NEXTPNR_NAMESPACE=nextpnr_${family})
|
||||
target_include_directories(chipdb-${family} PRIVATE ${family})
|
||||
|
||||
foreach(family_target ${family_targets})
|
||||
target_sources(${family_target} PRIVATE $<TARGET_OBJECTS:chipdb-${family}>)
|
||||
endforeach()
|
||||
79
gowin/main.cc
Normal file
79
gowin/main.cc
Normal file
@ -0,0 +1,79 @@
|
||||
/*
|
||||
* nextpnr -- Next Generation Place and Route
|
||||
*
|
||||
* Copyright (C) 2018 Clifford Wolf <clifford@symbioticeda.com>
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifdef MAIN_EXECUTABLE
|
||||
|
||||
#include <fstream>
|
||||
#include "command.h"
|
||||
#include "design_utils.h"
|
||||
#include "log.h"
|
||||
#include "timing.h"
|
||||
|
||||
USING_NEXTPNR_NAMESPACE
|
||||
|
||||
class GowinCommandHandler : public CommandHandler
|
||||
{
|
||||
public:
|
||||
GowinCommandHandler(int argc, char **argv);
|
||||
virtual ~GowinCommandHandler(){};
|
||||
std::unique_ptr<Context> createContext(std::unordered_map<std::string, Property> &values) override;
|
||||
void setupArchContext(Context *ctx) override{};
|
||||
void customAfterLoad(Context *ctx) override;
|
||||
|
||||
protected:
|
||||
po::options_description getArchOptions() override;
|
||||
};
|
||||
|
||||
GowinCommandHandler::GowinCommandHandler(int argc, char **argv) : CommandHandler(argc, argv) {}
|
||||
|
||||
po::options_description GowinCommandHandler::getArchOptions()
|
||||
{
|
||||
po::options_description specific("Architecture specific options");
|
||||
specific.add_options()("device", po::value<std::string>(), "device name");
|
||||
specific.add_options()("family", po::value<std::string>(), "device family");
|
||||
specific.add_options()("package", po::value<std::string>(), "device package");
|
||||
specific.add_options()("speed", po::value<std::string>(), "device speed grade");
|
||||
specific.add_options()("pdc", po::value<std::string>(), "physical constraints file");
|
||||
return specific;
|
||||
}
|
||||
|
||||
std::unique_ptr<Context> GowinCommandHandler::createContext(std::unordered_map<std::string, Property> &values)
|
||||
{
|
||||
ArchArgs chipArgs;
|
||||
chipArgs.device = vm["device"].as<std::string>();
|
||||
return std::unique_ptr<Context>(new Context(chipArgs));
|
||||
}
|
||||
|
||||
void GowinCommandHandler::customAfterLoad(Context *ctx)
|
||||
{
|
||||
// if (vm.count("pdc")) {
|
||||
// std::string filename = vm["pdc"].as<std::string>();
|
||||
// std::ifstream in(filename);
|
||||
// if (!in)
|
||||
// log_error("Failed to open input PDC file %s.\n", filename.c_str());
|
||||
// ctx->read_pdc(in);
|
||||
// }
|
||||
}
|
||||
|
||||
int main(int argc, char *argv[])
|
||||
{
|
||||
GowinCommandHandler handler(argc, argv);
|
||||
return handler.exec();
|
||||
}
|
||||
#endif
|
||||
288
gowin/pack.cc
Normal file
288
gowin/pack.cc
Normal file
@ -0,0 +1,288 @@
|
||||
/*
|
||||
* nextpnr -- Next Generation Place and Route
|
||||
*
|
||||
* Copyright (C) 2018-19 David Shah <david@symbioticeda.com>
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <algorithm>
|
||||
#include <iterator>
|
||||
#include <unordered_set>
|
||||
#include "cells.h"
|
||||
#include "design_utils.h"
|
||||
#include "log.h"
|
||||
#include "util.h"
|
||||
|
||||
NEXTPNR_NAMESPACE_BEGIN
|
||||
|
||||
// Pack LUTs and LUT-FF pairs
|
||||
static void pack_lut_lutffs(Context *ctx)
|
||||
{
|
||||
log_info("Packing LUT-FFs..\n");
|
||||
|
||||
std::unordered_set<IdString> packed_cells;
|
||||
std::vector<std::unique_ptr<CellInfo>> new_cells;
|
||||
for (auto cell : sorted(ctx->cells)) {
|
||||
CellInfo *ci = cell.second;
|
||||
if (ctx->verbose)
|
||||
log_info("cell '%s' is of type '%s'\n", ci->name.c_str(ctx), ci->type.c_str(ctx));
|
||||
if (is_lut(ctx, ci)) {
|
||||
std::unique_ptr<CellInfo> packed =
|
||||
create_generic_cell(ctx, ctx->id("GENERIC_SLICE"), ci->name.str(ctx) + "_LC");
|
||||
std::copy(ci->attrs.begin(), ci->attrs.end(), std::inserter(packed->attrs, packed->attrs.begin()));
|
||||
packed_cells.insert(ci->name);
|
||||
if (ctx->verbose)
|
||||
log_info("packed cell %s into %s\n", ci->name.c_str(ctx), packed->name.c_str(ctx));
|
||||
// See if we can pack into a DFF
|
||||
// TODO: LUT cascade
|
||||
NetInfo *o = ci->ports.at(ctx->id("Q")).net;
|
||||
CellInfo *dff = net_only_drives(ctx, o, is_ff, ctx->id("D"), true);
|
||||
auto lut_bel = ci->attrs.find(ctx->id("BEL"));
|
||||
bool packed_dff = false;
|
||||
if (dff) {
|
||||
if (ctx->verbose)
|
||||
log_info("found attached dff %s\n", dff->name.c_str(ctx));
|
||||
auto dff_bel = dff->attrs.find(ctx->id("BEL"));
|
||||
if (lut_bel != ci->attrs.end() && dff_bel != dff->attrs.end() && lut_bel->second != dff_bel->second) {
|
||||
// Locations don't match, can't pack
|
||||
} else {
|
||||
lut_to_lc(ctx, ci, packed.get(), false);
|
||||
dff_to_lc(ctx, dff, packed.get(), false);
|
||||
ctx->nets.erase(o->name);
|
||||
if (dff_bel != dff->attrs.end())
|
||||
packed->attrs[ctx->id("BEL")] = dff_bel->second;
|
||||
packed_cells.insert(dff->name);
|
||||
if (ctx->verbose)
|
||||
log_info("packed cell %s into %s\n", dff->name.c_str(ctx), packed->name.c_str(ctx));
|
||||
packed_dff = true;
|
||||
}
|
||||
}
|
||||
if (!packed_dff) {
|
||||
lut_to_lc(ctx, ci, packed.get(), true);
|
||||
}
|
||||
new_cells.push_back(std::move(packed));
|
||||
}
|
||||
}
|
||||
for (auto pcell : packed_cells) {
|
||||
ctx->cells.erase(pcell);
|
||||
}
|
||||
for (auto &ncell : new_cells) {
|
||||
ctx->cells[ncell->name] = std::move(ncell);
|
||||
}
|
||||
}
|
||||
|
||||
// Pack FFs not packed as LUTFFs
|
||||
static void pack_nonlut_ffs(Context *ctx)
|
||||
{
|
||||
log_info("Packing non-LUT FFs..\n");
|
||||
|
||||
std::unordered_set<IdString> packed_cells;
|
||||
std::vector<std::unique_ptr<CellInfo>> new_cells;
|
||||
|
||||
for (auto cell : sorted(ctx->cells)) {
|
||||
CellInfo *ci = cell.second;
|
||||
if (is_ff(ctx, ci)) {
|
||||
std::unique_ptr<CellInfo> packed =
|
||||
create_generic_cell(ctx, ctx->id("GENERIC_SLICE"), ci->name.str(ctx) + "_DFFLC");
|
||||
std::copy(ci->attrs.begin(), ci->attrs.end(), std::inserter(packed->attrs, packed->attrs.begin()));
|
||||
if (ctx->verbose)
|
||||
log_info("packed cell %s into %s\n", ci->name.c_str(ctx), packed->name.c_str(ctx));
|
||||
packed_cells.insert(ci->name);
|
||||
dff_to_lc(ctx, ci, packed.get(), true);
|
||||
new_cells.push_back(std::move(packed));
|
||||
}
|
||||
}
|
||||
for (auto pcell : packed_cells) {
|
||||
ctx->cells.erase(pcell);
|
||||
}
|
||||
for (auto &ncell : new_cells) {
|
||||
ctx->cells[ncell->name] = std::move(ncell);
|
||||
}
|
||||
}
|
||||
|
||||
// Merge a net into a constant net
|
||||
static void set_net_constant(const Context *ctx, NetInfo *orig, NetInfo *constnet, bool constval)
|
||||
{
|
||||
orig->driver.cell = nullptr;
|
||||
for (auto user : orig->users) {
|
||||
if (user.cell != nullptr) {
|
||||
CellInfo *uc = user.cell;
|
||||
if (ctx->verbose)
|
||||
log_info("%s user %s\n", orig->name.c_str(ctx), uc->name.c_str(ctx));
|
||||
if ((is_lut(ctx, uc) || is_lc(ctx, uc)) && (user.port.str(ctx).at(0) == 'I') && !constval) {
|
||||
uc->ports[user.port].net = nullptr;
|
||||
} else {
|
||||
uc->ports[user.port].net = constnet;
|
||||
constnet->users.push_back(user);
|
||||
}
|
||||
}
|
||||
}
|
||||
orig->users.clear();
|
||||
}
|
||||
|
||||
// Pack constants (simple implementation)
|
||||
static void pack_constants(Context *ctx)
|
||||
{
|
||||
log_info("Packing constants..\n");
|
||||
|
||||
std::unique_ptr<CellInfo> gnd_cell = create_generic_cell(ctx, ctx->id("GENERIC_SLICE"), "$PACKER_GND");
|
||||
gnd_cell->params[ctx->id("INIT")] = Property(0, 1 << ctx->args.K);
|
||||
std::unique_ptr<NetInfo> gnd_net = std::unique_ptr<NetInfo>(new NetInfo);
|
||||
gnd_net->name = ctx->id("$PACKER_GND_NET");
|
||||
gnd_net->driver.cell = gnd_cell.get();
|
||||
gnd_net->driver.port = ctx->id("F");
|
||||
gnd_cell->ports.at(ctx->id("F")).net = gnd_net.get();
|
||||
|
||||
std::unique_ptr<CellInfo> vcc_cell = create_generic_cell(ctx, ctx->id("GENERIC_SLICE"), "$PACKER_VCC");
|
||||
// Fill with 1s
|
||||
vcc_cell->params[ctx->id("INIT")] = Property(Property::S1).extract(0, (1 << ctx->args.K), Property::S1);
|
||||
std::unique_ptr<NetInfo> vcc_net = std::unique_ptr<NetInfo>(new NetInfo);
|
||||
vcc_net->name = ctx->id("$PACKER_VCC_NET");
|
||||
vcc_net->driver.cell = vcc_cell.get();
|
||||
vcc_net->driver.port = ctx->id("F");
|
||||
vcc_cell->ports.at(ctx->id("F")).net = vcc_net.get();
|
||||
|
||||
std::vector<IdString> dead_nets;
|
||||
|
||||
bool gnd_used = false;
|
||||
|
||||
for (auto net : sorted(ctx->nets)) {
|
||||
NetInfo *ni = net.second;
|
||||
if (ni->driver.cell != nullptr && ni->driver.cell->type == ctx->id("GND")) {
|
||||
IdString drv_cell = ni->driver.cell->name;
|
||||
set_net_constant(ctx, ni, gnd_net.get(), false);
|
||||
gnd_used = true;
|
||||
dead_nets.push_back(net.first);
|
||||
ctx->cells.erase(drv_cell);
|
||||
} else if (ni->driver.cell != nullptr && ni->driver.cell->type == ctx->id("VCC")) {
|
||||
IdString drv_cell = ni->driver.cell->name;
|
||||
set_net_constant(ctx, ni, vcc_net.get(), true);
|
||||
dead_nets.push_back(net.first);
|
||||
ctx->cells.erase(drv_cell);
|
||||
}
|
||||
}
|
||||
|
||||
if (gnd_used) {
|
||||
ctx->cells[gnd_cell->name] = std::move(gnd_cell);
|
||||
ctx->nets[gnd_net->name] = std::move(gnd_net);
|
||||
}
|
||||
// Vcc cell always inserted for now, as it may be needed during carry legalisation (TODO: trim later if actually
|
||||
// never used?)
|
||||
ctx->cells[vcc_cell->name] = std::move(vcc_cell);
|
||||
ctx->nets[vcc_net->name] = std::move(vcc_net);
|
||||
|
||||
for (auto dn : dead_nets) {
|
||||
ctx->nets.erase(dn);
|
||||
}
|
||||
}
|
||||
|
||||
static bool is_nextpnr_iob(Context *ctx, CellInfo *cell)
|
||||
{
|
||||
return cell->type == ctx->id("$nextpnr_ibuf") || cell->type == ctx->id("$nextpnr_obuf") ||
|
||||
cell->type == ctx->id("$nextpnr_iobuf");
|
||||
}
|
||||
|
||||
static bool is_generic_iob(const Context *ctx, const CellInfo *cell) { return cell->type == ctx->id("GENERIC_IOB"); }
|
||||
|
||||
// Pack IO buffers
|
||||
static void pack_io(Context *ctx)
|
||||
{
|
||||
std::unordered_set<IdString> packed_cells;
|
||||
std::unordered_set<IdString> delete_nets;
|
||||
|
||||
std::vector<std::unique_ptr<CellInfo>> new_cells;
|
||||
log_info("Packing IOs..\n");
|
||||
|
||||
for (auto cell : sorted(ctx->cells)) {
|
||||
CellInfo *ci = cell.second;
|
||||
if (is_nextpnr_iob(ctx, ci)) {
|
||||
CellInfo *iob = nullptr;
|
||||
if (ci->type == ctx->id("$nextpnr_ibuf") || ci->type == ctx->id("$nextpnr_iobuf")) {
|
||||
iob = net_only_drives(ctx, ci->ports.at(ctx->id("O")).net, is_generic_iob, ctx->id("PAD"), true, ci);
|
||||
|
||||
} else if (ci->type == ctx->id("$nextpnr_obuf")) {
|
||||
NetInfo *net = ci->ports.at(ctx->id("I")).net;
|
||||
iob = net_only_drives(ctx, net, is_generic_iob, ctx->id("PAD"), true, ci);
|
||||
}
|
||||
if (iob != nullptr) {
|
||||
// Trivial case, GENERIC_IOB used. Just destroy the net and the
|
||||
// iobuf
|
||||
log_info("%s feeds GENERIC_IOB %s, removing %s %s.\n", ci->name.c_str(ctx), iob->name.c_str(ctx),
|
||||
ci->type.c_str(ctx), ci->name.c_str(ctx));
|
||||
NetInfo *net = iob->ports.at(ctx->id("PAD")).net;
|
||||
if (((ci->type == ctx->id("$nextpnr_ibuf") || ci->type == ctx->id("$nextpnr_iobuf")) &&
|
||||
net->users.size() > 1) ||
|
||||
(ci->type == ctx->id("$nextpnr_obuf") && (net->users.size() > 2 || net->driver.cell != nullptr)))
|
||||
log_error("PAD of %s '%s' connected to more than a single top level IO.\n", iob->type.c_str(ctx),
|
||||
iob->name.c_str(ctx));
|
||||
|
||||
if (net != nullptr) {
|
||||
delete_nets.insert(net->name);
|
||||
iob->ports.at(ctx->id("PAD")).net = nullptr;
|
||||
}
|
||||
if (ci->type == ctx->id("$nextpnr_iobuf")) {
|
||||
NetInfo *net2 = ci->ports.at(ctx->id("I")).net;
|
||||
if (net2 != nullptr) {
|
||||
delete_nets.insert(net2->name);
|
||||
}
|
||||
}
|
||||
} else if (bool_or_default(ctx->settings, ctx->id("disable_iobs"))) {
|
||||
// No IO buffer insertion; just remove nextpnr_[io]buf
|
||||
for (auto &p : ci->ports)
|
||||
disconnect_port(ctx, ci, p.first);
|
||||
} else {
|
||||
// Create a GENERIC_IOB buffer
|
||||
std::unique_ptr<CellInfo> ice_cell =
|
||||
create_generic_cell(ctx, ctx->id("GENERIC_IOB"), ci->name.str(ctx) + "$iob");
|
||||
nxio_to_iob(ctx, ci, ice_cell.get(), packed_cells);
|
||||
new_cells.push_back(std::move(ice_cell));
|
||||
iob = new_cells.back().get();
|
||||
}
|
||||
packed_cells.insert(ci->name);
|
||||
if (iob != nullptr)
|
||||
std::copy(ci->attrs.begin(), ci->attrs.end(), std::inserter(iob->attrs, iob->attrs.begin()));
|
||||
}
|
||||
}
|
||||
for (auto pcell : packed_cells) {
|
||||
ctx->cells.erase(pcell);
|
||||
}
|
||||
for (auto dnet : delete_nets) {
|
||||
ctx->nets.erase(dnet);
|
||||
}
|
||||
for (auto &ncell : new_cells) {
|
||||
ctx->cells[ncell->name] = std::move(ncell);
|
||||
}
|
||||
}
|
||||
|
||||
// Main pack function
|
||||
bool Arch::pack()
|
||||
{
|
||||
Context *ctx = getCtx();
|
||||
try {
|
||||
log_break();
|
||||
pack_constants(ctx);
|
||||
pack_io(ctx);
|
||||
pack_lut_lutffs(ctx);
|
||||
pack_nonlut_ffs(ctx);
|
||||
ctx->settings[ctx->id("pack")] = 1;
|
||||
ctx->assignArchInfo();
|
||||
log_info("Checksum: 0x%08x\n", ctx->checksum());
|
||||
return true;
|
||||
} catch (log_execution_error_exception) {
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
||||
NEXTPNR_NAMESPACE_END
|
||||
Loading…
Reference in New Issue
Block a user