timing: Add backwards path walking
Signed-off-by: gatecat <gatecat@ds0.me>
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0528ceead1
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@ -552,6 +552,10 @@ struct DelayPair
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{
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return {min_delay + other.min_delay, max_delay + other.max_delay};
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}
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DelayPair operator-(const DelayPair &other) const
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{
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return {min_delay - other.min_delay, max_delay - other.max_delay};
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}
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};
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// four-quadrant, min and max rise and fall delay
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@ -575,6 +579,7 @@ struct DelayQuad
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DelayPair delayPair() const { return DelayPair(minDelay(), maxDelay()); };
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DelayQuad operator+(const DelayQuad &other) const { return {rise + other.rise, fall + other.fall}; }
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DelayQuad operator-(const DelayQuad &other) const { return {rise - other.rise, fall - other.fall}; }
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};
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struct ClockConstraint;
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@ -38,6 +38,7 @@ void TimingAnalyser::setup()
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setup_port_domains();
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reset_times();
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walk_forward();
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walk_backward();
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}
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void TimingAnalyser::init_ports()
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@ -217,7 +218,7 @@ void TimingAnalyser::setup_port_domains()
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auto dom = domain_id(port.cell, fanout.other_port, fanout.edge);
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// create per-domain data
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pd.required[dom];
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domains.at(dom).startpoints.emplace_back(port, fanout.other_port);
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domains.at(dom).endpoints.emplace_back(port, fanout.other_port);
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}
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// copy port to driver
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if (pi.net != nullptr && pi.net->driver.cell != nullptr)
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@ -272,6 +273,21 @@ void TimingAnalyser::set_arrival_time(CellPortKey target, domain_id_t domain, De
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arr.path_length = std::max(arr.path_length, path_length);
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}
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void TimingAnalyser::set_required_time(CellPortKey target, domain_id_t domain, DelayPair required, int path_length,
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CellPortKey prev)
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{
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auto &req = ports.at(target).required.at(domain);
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if (required.min_delay < req.value.min_delay) {
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req.value.min_delay = required.min_delay;
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req.bwd_min = prev;
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}
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if (!setup_only && (required.max_delay > req.value.max_delay)) {
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req.value.max_delay = required.max_delay;
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req.bwd_max = prev;
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}
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req.path_length = std::max(req.path_length, path_length);
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}
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void TimingAnalyser::walk_forward()
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{
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// Assign initial arrival time to domain startpoints
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@ -322,6 +338,54 @@ void TimingAnalyser::walk_forward()
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}
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}
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void TimingAnalyser::walk_backward()
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{
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// Assign initial required time to domain endpoints
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// Note that clock frequency will be considered later in the analysis for, for now all required times are normalised
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// to 0ns
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for (domain_id_t dom_id = 0; dom_id < domain_id_t(domains.size()); ++dom_id) {
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auto &dom = domains.at(dom_id);
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for (auto &ep : dom.endpoints) {
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auto &pd = ports.at(ep.first);
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DelayPair init_setuphold(0);
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CellPortKey clock_key;
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// TODO: clock routing delay, if analysis of that is enabled
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if (ep.second != IdString()) {
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// Add setup/hold time, if this endpoint is clocked
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for (auto &fanin : pd.cell_arcs) {
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if (fanin.type == CellArc::SETUP && fanin.other_port == ep.second)
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init_setuphold.min_delay -= fanin.value.maxDelay();
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if (fanin.type == CellArc::HOLD && fanin.other_port == ep.second)
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init_setuphold.max_delay -= fanin.value.maxDelay();
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}
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clock_key = CellPortKey(ep.first.cell, ep.second);
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}
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set_required_time(ep.first, dom_id, init_setuphold, 1, clock_key);
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}
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}
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// Walk backwards in topological order
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for (auto p : reversed_range(topological_order)) {
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auto &pd = ports.at(p);
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for (auto &req : pd.required) {
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if (pd.type == PORT_IN) {
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// Input port: propagate delay back through net, subtracting route delay
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NetInfo *net = port_info(p).net;
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if (net != nullptr && net->driver.cell != nullptr)
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set_required_time(CellPortKey(net->driver), req.first, req.second.value - pd.route_delay,
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req.second.path_length, p);
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} else if (pd.type == PORT_OUT) {
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// Output port : propagate delay back through cell, subtracting combinational delay
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for (auto &fanin : pd.cell_arcs) {
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if (fanin.type != CellArc::COMBINATIONAL)
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continue;
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set_required_time(CellPortKey(p.cell, fanin.other_port), req.first,
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req.second.value - fanin.value.delayPair(), req.second.path_length + 1, p);
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}
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}
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}
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}
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}
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domain_id_t TimingAnalyser::domain_id(IdString cell, IdString clock_port, ClockEdge edge)
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{
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return domain_id(ctx->cells.at(cell)->ports.at(clock_port).net, edge);
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@ -138,6 +138,7 @@ struct TimingAnalyser
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void reset_times();
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void walk_forward();
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void walk_backward();
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const DelayPair init_delay{std::numeric_limits<delay_t>::max(), std::numeric_limits<delay_t>::lowest()};
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