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Include ALU54B in cell types with wire location overrides

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Adam Greig 2022-11-09 02:44:37 +00:00
parent f89b959b5f
commit 174848b4b3
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GPG Key ID: 8B3FE5477B1DD9A0
1 changed files with 1 additions and 1 deletions
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2
ecp5/arch_place.cc
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@ -203,7 +203,7 @@ void Arch::setup_wire_locations()
CellInfo *ci = cell.second.get();
if (ci->bel == BelId())
continue;
if (ci->type.in(id_MULT18X18D, id_DCUA, id_DDRDLL, id_DQSBUFM, id_EHXPLLL)) {
if (ci->type.in(id_ALU54B, id_MULT18X18D, id_DCUA, id_DDRDLL, id_DQSBUFM, id_EHXPLLL)) {
for (auto &port : ci->ports) {
if (port.second.net == nullptr)
continue;