Fix for multiple id_SLICE_LUT6 per actual SLICE
This commit is contained in:
parent
d05ac75fda
commit
17918b5992
106
xc7/arch.cc
106
xc7/arch.cc
@ -35,17 +35,36 @@ NEXTPNR_NAMESPACE_BEGIN
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std::unique_ptr<const TorcInfo> torc_info;
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TorcInfo::TorcInfo(Arch *ctx, const std::string &inDeviceName, const std::string &inPackageName)
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: ddb(new DDB(inDeviceName, inPackageName)), sites(ddb->getSites()), tiles(ddb->getTiles()), site_index_to_type(construct_site_index_to_type(ctx, sites)), site_index_to_z_offset(construct_site_index_to_z_offset(sites, site_index_to_type))
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: ddb(new DDB(inDeviceName, inPackageName)), sites(ddb->getSites()), tiles(ddb->getTiles()), bel_to_site_index(construct_bel_to_site_index(ctx, sites)), num_bels(bel_to_site_index.size()), site_index_to_type(construct_site_index_to_type(ctx, sites)), bel_to_z(construct_bel_to_z(sites, num_bels, site_index_to_type))
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{
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}
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std::vector<SiteIndex> TorcInfo::construct_bel_to_site_index(Arch* ctx, const Sites &sites)
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{
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std::vector<SiteIndex> bel_to_site_index;
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bel_to_site_index.reserve(sites.getSiteCount());
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for (SiteIndex i(0); i < sites.getSiteCount(); ++i) {
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const auto &s = sites.getSite(i);
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const auto &pd = s.getPrimitiveDefPtr();
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const auto &type = pd->getName();
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if (type == "SLICEL" || type == "SLICEM") {
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bel_to_site_index.push_back(i);
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bel_to_site_index.push_back(i);
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bel_to_site_index.push_back(i);
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bel_to_site_index.push_back(i);
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}
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else
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bel_to_site_index.push_back(i);
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}
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return bel_to_site_index;
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}
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std::vector<IdString> TorcInfo::construct_site_index_to_type(Arch* ctx, const Sites &sites)
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{
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std::vector<IdString> site_index_to_type;
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site_index_to_type.resize(sites.getSiteCount());
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for (SiteIndex i(0); i < sites.getSiteCount(); ++i) {
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auto s = sites.getSite(i);
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auto pd = s.getPrimitiveDefPtr();
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auto type = pd->getName();
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const auto &s = sites.getSite(i);
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const auto &pd = s.getPrimitiveDefPtr();
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const auto &type = pd->getName();
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if (type == "SLICEL" || type == "SLICEM")
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site_index_to_type[i] = id_SLICE_LUT6;
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else
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@ -53,20 +72,33 @@ std::vector<IdString> TorcInfo::construct_site_index_to_type(Arch* ctx, const Si
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}
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return site_index_to_type;
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}
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std::vector<int8_t> TorcInfo::construct_site_index_to_z_offset(const Sites &sites, const std::vector<IdString> &site_index_to_type)
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std::vector<int8_t> TorcInfo::construct_bel_to_z(const Sites &sites, const int num_bels, const std::vector<IdString> &site_index_to_type)
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{
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std::vector<int8_t> site_index_to_z_offset;
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site_index_to_z_offset.resize(site_index_to_type.size());
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std::vector<int8_t> bel_to_z;
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bel_to_z.resize(num_bels);
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int32_t bel_index = 0;
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for (SiteIndex i(0); i < site_index_to_type.size(); ++i) {
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if (site_index_to_type[i] == id_SLICE_LUT6) {
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auto site = sites.getSite(i);
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auto site_name = site.getName();
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auto site_name_back = site_name.back();
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if (site_name_back == '1' || site_name_back == '3' || site_name_back == '5' || site_name_back == '7' || site_name_back == '9')
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site_index_to_z_offset[i] = 4;
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if (site_name_back == '0' || site_name_back == '2' || site_name_back == '4' || site_name_back == '6' || site_name_back == '8') {
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bel_to_z[bel_index++] = 0;
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bel_to_z[bel_index++] = 1;
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bel_to_z[bel_index++] = 2;
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bel_to_z[bel_index++] = 3;
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}
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else {
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bel_to_z[bel_index++] = 4;
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bel_to_z[bel_index++] = 5;
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bel_to_z[bel_index++] = 6;
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bel_to_z[bel_index++] = 7;
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}
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}
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else
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++bel_index;
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}
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return site_index_to_z_offset;
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return bel_to_z;
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}
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@ -100,7 +132,7 @@ Arch::Arch(ArchArgs args) : args(args)
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// if (package_info == nullptr)
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// log_error("Unsupported package '%s'.\n", args.package.c_str());
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bel_to_cell.resize(torc_info->sites.getSiteCount());
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bel_to_cell.resize(torc_info->num_bels);
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}
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// -----------------------------------------------------------------------
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@ -141,18 +173,9 @@ BelId Arch::getBelByLocation(Loc loc) const
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BelId bel;
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if (bel_by_loc.empty()) {
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for (SiteIndex i(0); i < torc_info->sites.getSiteCount(); ++i) {
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for (int i = 0; i < torc_info->num_bels; i++) {
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BelId b;
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b.index = i;
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if (torc_info->site_index_to_type[i] == id_SLICE_LUT6) {
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b.pos = BelId::A;
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bel_by_loc[getBelLocation(b)] = b;
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b.pos = BelId::B;
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bel_by_loc[getBelLocation(b)] = b;
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b.pos = BelId::C;
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bel_by_loc[getBelLocation(b)] = b;
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b.pos = BelId::D;
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}
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bel_by_loc[getBelLocation(b)] = b;
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}
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}
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@ -168,14 +191,13 @@ BelRange Arch::getBelsByTile(int x, int y) const
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{
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BelRange br;
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auto b = getBelByLocation(Loc(x, y, 0));
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br.b.index = b.index;
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br.b.pos = b.pos;
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br.e = br.b;
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br.b.cursor = Arch::getBelByLocation(Loc(x, y, 0)).index;
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br.e.cursor = br.b.cursor;
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if (br.e.index != SiteIndex(torc_info->sites.getSiteCount())) {
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while (br.e.index < SiteIndex(torc_info->sites.getSiteCount()) && torc_info->sites.getSite((*br.e).index).getTileIndex() == torc_info->sites.getSite((*br.b).index).getTileIndex())
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br.e++;
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if (br.e.cursor != -1) {
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while (br.e.cursor < chip_info->num_bels && chip_info->bel_data[br.e.cursor].x == x &&
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chip_info->bel_data[br.e.cursor].y == y)
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br.e.cursor++;
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}
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return br;
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@ -213,17 +235,25 @@ WireId Arch::getBelPinWire(BelId bel, IdString pin) const
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{
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WireId ret;
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auto &site = torc_info->sites.getSite(bel.index);
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auto site_index = torc_info->bel_to_site_index[bel.index];
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auto pin_name = pin.str(this);
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if (torc_info->site_index_to_type[bel.index] == id_SLICE_LUT6) {
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if (torc_info->site_index_to_type[site_index] == id_SLICE_LUT6) {
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// For all LUT based inputs (I1-I6,O,OQ,OMUX) then change the I/O into the LUT
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if (pin_name[0] == 'I' || pin_name[0] == 'O')
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pin_name[0] = bel.pos;
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if (pin_name[0] == 'I' || pin_name[0] == 'O') {
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switch (torc_info->bel_to_z[bel.index]) {
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case 0: case 4: pin_name[0] = 'A'; break;
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case 1: case 5: pin_name[0] = 'B'; break;
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case 2: case 6: pin_name[0] = 'C'; break;
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case 3: case 7: pin_name[0] = 'D'; break;
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default: throw;
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}
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}
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}
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auto &site = torc_info->sites.getSite(site_index);
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ret.index = site.getPinTilewire(pin_name);
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if (ret.index.isUndefined())
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log_error("no wire found for site '%s' pin '%s' \n", torc_info->site_index_to_name(bel.index).c_str(), pin_name.c_str());
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log_error("no wire found for site '%s' pin '%s' \n", torc_info->bel_to_name(bel.index).c_str(), pin_name.c_str());
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// NPNR_ASSERT(bel != BelId());
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@ -823,14 +853,4 @@ void Arch::assignCellInfo(CellInfo *cell)
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}
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}
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void operator++(BelId::bel &b) {
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switch (b) {
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case BelId::A: b = BelId::B; return;
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case BelId::B: b = BelId::C; return;
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case BelId::C: b = BelId::D; return;
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default: break;
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}
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throw;
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}
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NEXTPNR_NAMESPACE_END
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71
xc7/arch.h
71
xc7/arch.h
@ -240,56 +240,57 @@ struct TorcInfo {
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const Sites &sites;
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const Tiles &tiles;
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SiteIndex sites_begin() const { return SiteIndex(0); }
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SiteIndex sites_end() const { return SiteIndex(sites.getSiteCount()); }
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const TileInfo& site_index_to_tile_info(SiteIndex si) const {
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const TileInfo& bel_to_tile_info(int32_t index) const {
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auto si = bel_to_site_index[index];
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auto &site = sites.getSite(si);
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return tiles.getTileInfo(site.getTileIndex());
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}
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const std::string& site_index_to_name(SiteIndex si) const {
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const std::string& bel_to_name(int32_t index) const {
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auto si = bel_to_site_index[index];
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return sites.getSite(si).getName();
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}
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const std::vector<SiteIndex> bel_to_site_index;
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const int num_bels;
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const std::vector<IdString> site_index_to_type;
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const std::vector<int8_t> site_index_to_z_offset;
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const std::vector<int8_t> bel_to_z;
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private:
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static std::vector<SiteIndex> construct_bel_to_site_index(Arch *ctx, const Sites &sites);
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static std::vector<IdString> construct_site_index_to_type(Arch *ctx, const Sites &sites);
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static std::vector<int8_t> construct_site_index_to_z_offset(const Sites &sites, const std::vector<IdString> &site_index_to_type);
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static std::vector<int8_t> construct_bel_to_z(const Sites &sites, const int num_bels, const std::vector<IdString> &site_index_to_type);
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};
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extern std::unique_ptr<const TorcInfo> torc_info;
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/************************ End of chipdb section. ************************/
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struct BelIterator : public BelId
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struct BelIterator
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{
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int cursor;
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BelIterator operator++()
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{
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if (pos >= A && pos < D) {
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++pos;
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return *this;
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}
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if (torc_info->site_index_to_type[++index] == id_SLICE_LUT6)
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pos = A;
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else
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pos = NOT_APPLICABLE;
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cursor++;
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return *this;
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}
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BelIterator operator++(int)
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{
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BelIterator prior(*this);
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operator++();
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cursor++;
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return prior;
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}
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bool operator!=(const BelIterator &other) const { return BelId::operator!=(other); }
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bool operator!=(const BelIterator &other) const { return cursor != other.cursor; }
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bool operator==(const BelIterator &other) const { return BelId::operator==(other); }
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bool operator==(const BelIterator &other) const { return cursor == other.cursor; }
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BelId operator*() const { return *this; }
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BelId operator*() const
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{
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BelId ret;
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ret.index = cursor;
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return ret;
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}
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};
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struct BelRange
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@ -447,12 +448,19 @@ struct Arch : BaseCtx
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IdString getBelName(BelId bel) const
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{
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NPNR_ASSERT(bel != BelId());
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auto name = torc_info->site_index_to_name(bel.index);
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if (torc_info->site_index_to_type[bel.index] == id_SLICE_LUT6) {
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auto name = torc_info->bel_to_name(bel.index);
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auto site_index = torc_info->bel_to_site_index[bel.index];
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if (torc_info->site_index_to_type[site_index] == id_SLICE_LUT6) {
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// Append LUT name to name
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name.reserve(name.size() + 2);
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name += "_";
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name += bel.pos;
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switch (torc_info->bel_to_z[bel.index]) {
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case 0: case 4: name += 'A'; break;
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case 1: case 5: name += 'B'; break;
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case 2: case 6: name += 'C'; break;
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case 3: case 7: name += 'D'; break;
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default: throw;
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}
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}
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return id(name);
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}
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@ -503,23 +511,19 @@ struct Arch : BaseCtx
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BelRange getBels() const
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{
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BelRange range;
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range.b.index = torc_info->sites_begin();
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range.e.index = torc_info->sites_end();
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range.b.cursor = 0;
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range.e.cursor = torc_info->num_bels;
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return range;
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}
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Loc getBelLocation(BelId bel) const
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{
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auto &tile_info = torc_info->site_index_to_tile_info(bel.index);
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auto &tile_info = torc_info->bel_to_tile_info(bel.index);
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Loc loc;
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loc.x = tile_info.getCol();
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loc.y = tile_info.getRow();
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if (torc_info->site_index_to_type[bel.index] == id_SLICE_LUT6) {
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loc.z = bel.pos - 'A';
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// Apply offset if upper slice
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loc.z += torc_info->site_index_to_z_offset[bel.index];
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}
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loc.z = torc_info->bel_to_z[bel.index];
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return loc;
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}
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@ -531,7 +535,8 @@ struct Arch : BaseCtx
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IdString getBelType(BelId bel) const
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{
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NPNR_ASSERT(bel != BelId());
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return torc_info->site_index_to_type[bel.index];
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auto site_index = torc_info->bel_to_site_index[bel.index];
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return torc_info->site_index_to_type[site_index];
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}
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WireId getBelPinWire(BelId bel, IdString pin) const;
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@ -66,13 +66,11 @@ enum ConstIds
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struct BelId
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{
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SiteIndex index = SiteIndex(-1);
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enum bel : int8_t { NOT_APPLICABLE, A='A', B='B', C='C', D='D' } pos = NOT_APPLICABLE;
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int32_t index = -1;
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bool operator==(const BelId &other) const { return index == other.index && pos == pos; }
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bool operator!=(const BelId &other) const { return index != other.index || pos != pos; }
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bool operator==(const BelId &other) const { return index == other.index; }
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bool operator!=(const BelId &other) const { return index != other.index; }
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};
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void operator++(BelId::bel &b);
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struct WireId
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{
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18
xc7/xdl.cc
18
xc7/xdl.cc
@ -37,7 +37,7 @@ void write_xdl(const Context *ctx, std::ostream &out)
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XdlExporter exporter(out);
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auto designPtr = Factory::newDesignPtr("name", torc_info->ddb->getDeviceName(), "clg484", "", "");
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std::map<SiteIndex,InstanceSharedPtr> site_to_instance;
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std::unordered_map<int32_t,InstanceSharedPtr> site_to_instance;
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for (const auto& cell : ctx->cells) {
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const char* type;
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@ -46,7 +46,8 @@ void write_xdl(const Context *ctx, std::ostream &out)
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else if (cell.second->type == id_BUFGCTRL) type = "BUFGCTRL";
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else log_error("Unsupported cell type '%s'.\n", cell.second->type.c_str(ctx));
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auto ret = site_to_instance.emplace(cell.second->bel.index, nullptr);
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auto site_index = torc_info->bel_to_site_index[cell.second->bel.index];
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auto ret = site_to_instance.emplace(site_index, nullptr);
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InstanceSharedPtr instPtr;
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if (ret.second) {
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instPtr = Factory::newInstancePtr(cell.second->name.str(ctx), type, "", "");
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@ -54,15 +55,22 @@ void write_xdl(const Context *ctx, std::ostream &out)
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assert(b);
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ret.first->second = instPtr;
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const auto& tile_info = torc_info->site_index_to_tile_info(cell.second->bel.index);
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const auto& tile_info = torc_info->bel_to_tile_info(cell.second->bel.index);
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instPtr->setTile(tile_info.getName());
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instPtr->setSite(torc_info->site_index_to_name(cell.second->bel.index));
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instPtr->setSite(torc_info->bel_to_name(cell.second->bel.index));
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}
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else
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instPtr = ret.first->second;
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if (cell.second->type == id_SLICE_LUT6) {
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std::string config(1, cell.second->bel.pos);
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std::string config;
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switch (torc_info->bel_to_z[cell.second->bel.index]) {
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case 0: case 4: config += 'A'; break;
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case 1: case 5: config += 'B'; break;
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case 2: case 6: config += 'C'; break;
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case 3: case 7: config += 'D'; break;
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default: throw;
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}
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config += "6LUT";
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instPtr->setConfig(config, cell.second->name.str(ctx), "#LUT:O6=");
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}
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