ecp5: Adding real timing data to database
Signed-off-by: David Shah <dave@ds0.me>
This commit is contained in:
David Shah
parent
9c52afcf5f
commit
18813f2056
@ -96,7 +96,7 @@ Arch::Arch(ArchArgs args) : args(args)
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break;
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}
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}
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speed_grade = &(chip_info->speed_grades[args.speedGrade]);
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if (!package_info)
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log_error("Unsupported package '%s' for '%s'.\n", args.package.c_str(), getChipName().c_str());
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61
ecp5/arch.h
61
ecp5/arch.h
@ -71,7 +71,7 @@ NPNR_PACKED_STRUCT(struct BelPortPOD {
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NPNR_PACKED_STRUCT(struct PipInfoPOD {
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LocationPOD rel_src_loc, rel_dst_loc;
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int32_t src_idx, dst_idx;
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int32_t delay;
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int32_t timing_class;
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int16_t tile_type;
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int8_t pip_type;
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int8_t padding_0;
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@ -151,6 +151,46 @@ NPNR_PACKED_STRUCT(struct GlobalInfoPOD {
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int16_t spine_col;
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});
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NPNR_PACKED_STRUCT(struct CellPropDelayPOD {
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int32_t from_port;
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int32_t to_port;
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int32_t min_delay;
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int32_t max_delay;
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});
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NPNR_PACKED_STRUCT(struct CellSetupHoldPOD {
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int32_t sig_port;
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int32_t clock_port;
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int32_t min_setup;
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int32_t max_setup;
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int32_t min_hold;
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int32_t max_hold;
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});
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NPNR_PACKED_STRUCT(struct CellTimingPOD {
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int32_t cell_type;
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int32_t num_prop_delays;
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int32_t num_setup_holds;
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RelPtr<CellPropDelayPOD> prop_delays;
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RelPtr<CellSetupHoldPOD> setup_holds;
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});
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NPNR_PACKED_STRUCT(struct PipDelayPOD {
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int32_t min_base_delay;
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int32_t max_base_delay;
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int32_t min_fanout_adder;
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int32_t max_fanout_adder;
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});
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NPNR_PACKED_STRUCT(struct SpeedGradePOD {
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int32_t num_cell_timings;
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int32_t num_pip_classes;
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RelPtr<CellTimingPOD> cell_timings;
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RelPtr<PipDelayPOD> pip_classes;
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});
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NPNR_PACKED_STRUCT(struct ChipInfoPOD {
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int32_t width, height;
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int32_t num_tiles;
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@ -163,6 +203,7 @@ NPNR_PACKED_STRUCT(struct ChipInfoPOD {
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RelPtr<PackageInfoPOD> package_info;
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RelPtr<PIOInfoPOD> pio_info;
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RelPtr<TileInfoPOD> tile_info;
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RelPtr<SpeedGradePOD> speed_grades;
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});
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#if defined(_MSC_VER)
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@ -400,13 +441,20 @@ struct ArchArgs
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LFE5UM5G_85F,
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} type = NONE;
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std::string package;
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int speed = 6;
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enum SpeedGrade
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{
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SPEED_6,
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SPEED_7,
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SPEED_8,
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SPEED_8_5G,
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} speedGrade = SPEED_6;
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};
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struct Arch : BaseCtx
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{
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const ChipInfoPOD *chip_info;
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const PackageInfoPOD *package_info;
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const SpeedGradePOD *speed_grade;
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mutable std::unordered_map<IdString, BelId> bel_by_name;
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mutable std::unordered_map<IdString, WireId> wire_by_name;
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@ -633,7 +681,8 @@ struct Arch : BaseCtx
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DelayInfo getWireDelay(WireId wire) const
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{
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DelayInfo delay;
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delay.delay = 0;
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delay.min_delay = 0;
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delay.max_delay = 0;
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return delay;
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}
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@ -772,7 +821,8 @@ struct Arch : BaseCtx
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{
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DelayInfo delay;
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NPNR_ASSERT(pip != PipId());
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delay.delay = locInfo(pip)->pip_data[pip.index].delay;
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delay.min_delay = speed_grade->pip_classes[locInfo(pip)->pip_data[pip.index].timing_class].min_base_delay;
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delay.max_delay = speed_grade->pip_classes[locInfo(pip)->pip_data[pip.index].timing_class].max_base_delay;
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return delay;
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}
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@ -862,7 +912,8 @@ struct Arch : BaseCtx
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DelayInfo getDelayFromNS(float ns) const
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{
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DelayInfo del;
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del.delay = delay_t(ns * 1000);
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del.min_delay = delay_t(ns * 1000);
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del.max_delay = delay_t(ns * 1000);
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return del;
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}
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uint32_t getDelayChecksum(delay_t v) const { return v; }
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@ -30,21 +30,22 @@ typedef int delay_t;
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struct DelayInfo
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{
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delay_t delay = 0;
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delay_t min_delay = 0, max_delay = 0;
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delay_t minRaiseDelay() const { return delay; }
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delay_t maxRaiseDelay() const { return delay; }
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delay_t minRaiseDelay() const { return min_delay; }
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delay_t maxRaiseDelay() const { return max_delay; }
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delay_t minFallDelay() const { return delay; }
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delay_t maxFallDelay() const { return delay; }
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delay_t minFallDelay() const { return min_delay; }
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delay_t maxFallDelay() const { return max_delay; }
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delay_t minDelay() const { return delay; }
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delay_t maxDelay() const { return delay; }
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delay_t minDelay() const { return min_delay; }
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delay_t maxDelay() const { return max_delay; }
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DelayInfo operator+(const DelayInfo &other) const
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{
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DelayInfo ret;
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ret.delay = this->delay + other.delay;
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ret.min_delay = this->min_delay + other.min_delay;
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ret.max_delay = this->max_delay + other.max_delay;
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return ret;
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}
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};
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@ -811,7 +811,6 @@ X(INTLOCK)
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X(REFCLK)
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X(CLKINTFB)
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X(EXTREFB)
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X(REFCLKP)
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X(REFCLKN)
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@ -1116,4 +1115,30 @@ X(SEL2)
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X(SEL1)
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X(SEL0)
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X(CDIV1)
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X(CDIVX)
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X(CDIVX)
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X(DP16KD_REGMODE_A_NOREG_REGMODE_B_NOREG)
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X(DP16KD_REGMODE_A_NOREG_REGMODE_B_OUTREG)
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X(DP16KD_REGMODE_A_OUTREG_REGMODE_B_NOREG)
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X(DP16KD_REGMODE_A_OUTREG_REGMODE_B_OUTREG)
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X(DP16KD_WRITEMODE_A_NORMAL_WRITEMODE_B_NORMAL)
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X(DP16KD_WRITEMODE_A_NORMAL_WRITEMODE_B_READBEFOREWRITE)
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X(DP16KD_WRITEMODE_A_NORMAL_WRITEMODE_B_WRITETHROUGH)
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X(PIO_IOTYPE_LVCMOS12)
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X(PIO_IOTYPE_LVCMOS15)
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X(PIO_IOTYPE_LVCMOS18)
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X(PIO_IOTYPE_LVCMOS25)
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X(PIO_IOTYPE_LVCMOS33)
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X(PIO_IOTYPE_LVDS)
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X(PIO_IOTYPE_SSTL15_I)
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X(PIO_IOTYPE_SSTL15_II)
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X(PIO_IOTYPE_SSTL18_I)
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X(PIO_IOTYPE_SSTL18_II)
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X(SCCU2C)
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X(SDPRAME)
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X(SLOGICB)
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X(SRAMWB)
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X(PAD)
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X(PADDI)
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X(PADDO)
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X(PADDT)
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@ -18,11 +18,13 @@ file(MAKE_DIRECTORY ecp5/chipdbs/)
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add_library(ecp5_chipdb OBJECT ecp5/chipdbs/)
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target_compile_definitions(ecp5_chipdb PRIVATE NEXTPNR_NAMESPACE=nextpnr_${family})
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target_include_directories(ecp5_chipdb PRIVATE ${family}/)
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if (WIN32)
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set(ENV_CMD ${CMAKE_COMMAND} -E env "PYTHONPATH=\"${TRELLIS_ROOT}/libtrellis\;${TRELLIS_ROOT}/util/common\"")
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set(ENV_CMD ${CMAKE_COMMAND} -E env "PYTHONPATH=\"${TRELLIS_ROOT}/libtrellis\;${TRELLIS_ROOT}/util/common\;${TRELLIS_ROOT}/timing/util\"")
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else()
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set(ENV_CMD ${CMAKE_COMMAND} -E env "PYTHONPATH=${TRELLIS_ROOT}/libtrellis:${TRELLIS_ROOT}/util/common")
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set(ENV_CMD ${CMAKE_COMMAND} -E env "PYTHONPATH=${TRELLIS_ROOT}/libtrellis:${TRELLIS_ROOT}/util/common:${TRELLIS_ROOT}/timing/util")
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endif()
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if (MSVC)
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target_sources(ecp5_chipdb PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/ecp5/resource/embed.cc)
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set_source_files_properties(${CMAKE_CURRENT_SOURCE_DIR}/ecp5/resources/chipdb.rc PROPERTIES LANGUAGE RC)
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@ -3,6 +3,8 @@ import pytrellis
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import database
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import argparse
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import json
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import pip_classes
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import timing_dbs
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from os import path
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location_types = dict()
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@ -135,34 +137,62 @@ def process_loc_globals(chip):
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spine = (-1, -1)
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global_data[x, y] = (quadrants.index(quad), int(tapdrv.dir), tapdrv.col, spine)
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def get_wire_type(name):
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if "H00" in name or "V00" in name:
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return "X0"
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if "H01" in name or "V01" in name:
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return "X1"
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if "H02" in name or "V02" in name:
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return "X2"
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if "H06" in name or "V06" in name:
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return "X6"
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if "_SLICE" in name or "_EBR" in name:
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return "SLICE"
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return "LOCAL"
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def get_pip_delay(wire_from, wire_to):
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# ECP5 timings WIP!!!
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type_from = get_wire_type(wire_from)
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type_to = get_wire_type(wire_to)
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if type_from == "X2" and type_to == "X2":
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return 170
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if type_from == "SLICE" or type_to == "SLICE":
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return 205
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if type_from in ("LOCAL", "X0") and type_to in ("X1", "X2", "X6"):
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return 90
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if type_from == "X6" or type_to == "X6":
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return 200
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if type_from in ("X1", "X2", "X6") and type_to in ("LOCAL", "X0"):
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return 90
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return 100
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speed_grade_names = ["6", "7", "8", "8_5G"]
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speed_grade_cells = {}
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speed_grade_pips = {}
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pip_class_to_idx = {"default": 0}
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def process_timing_data():
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for grade in speed_grade_names:
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with open(timing_dbs.cells_db_path("ECP5", grade)) as f:
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cell_data = json.load(f)
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cells = []
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for cell, cdata in sorted(cell_data.items()):
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celltype = constids[cell.replace(":", "_").replace("=", "_").replace(",", "_")]
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delays = []
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setupholds = []
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for entry in cdata:
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if entry["type"] == "Width":
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continue
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elif entry["type"] == "IOPath":
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from_pin = constids[entry["from_pin"]]
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to_pin = constids[entry["to_pin"]]
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min_delay = min(entry["rising"][0], entry["falling"][0])
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max_delay = min(entry["rising"][2], entry["falling"][2])
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delays.append((from_pin, to_pin, min_delay, max_delay))
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elif entry["type"] == "SetupHold":
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pin = constids[entry["pin"]]
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clock = constids[entry["clock"]]
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min_setup = entry["setup"][0]
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max_setup = entry["setup"][2]
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min_hold = entry["hold"][0]
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max_hold = entry["hold"][2]
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setupholds.append((pin, clock, min_setup, max_setup, min_hold, max_hold))
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else:
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assert False, entry["type"]
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cells.append((celltype, delays, setupholds))
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pip_class_delays = [(50, 50, 0, 0)] # default: 50ps delay, 0ps fanout
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with open(timing_dbs.interconnect_db_path("ECP5", grade)) as f:
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interconn_data = json.load(f)
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for pipclass, pipdata in sorted(interconn_data.items()):
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pip_class_to_idx[pipclass] = len(pip_class_delays)
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min_delay = pipdata["delay"][0]
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max_delay = pipdata["delay"][2]
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min_fanout = pipdata["fanout"][0]
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max_fanout = pipdata["fanout"][2]
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pip_class_delays.append((min_delay, max_delay, min_fanout, max_fanout))
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speed_grade_cells[grade] = cells
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speed_grade_pips[grade] = pip_class_delays
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def get_pip_class(wire_from, wire_to):
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class_name = pip_classes.get_pip_class(wire_from, wire_to)
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if class_name is None:
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class_name = "default"
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return pip_class_to_idx[class_name]
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@ -181,7 +211,7 @@ def write_database(dev_name, chip, ddrg, endianness):
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loc = loc_with_type[arc_loctype]
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lt = ddrg.typeAtLocation[pytrellis.Location(loc[0] + rel.x, loc[1] + rel.y)]
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wire = ddrg.locationTypes[lt].wires[idx]
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return ddrg.to_str(wire.name)
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return "R{}C{}_{}".format(loc[0] + rel.x, loc[1] + rel.y, ddrg.to_str(wire.name))
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bba = BinaryBlobAssembler()
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bba.pre('#include "nextpnr.h"')
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@ -202,7 +232,7 @@ def write_database(dev_name, chip, ddrg, endianness):
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bba.u32(arc.sinkWire.id, "dst_idx")
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src_name = get_wire_name(idx, arc.srcWire.rel, arc.srcWire.id)
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snk_name = get_wire_name(idx, arc.sinkWire.rel, arc.sinkWire.id)
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bba.u32(get_pip_delay(src_name, snk_name), "delay") # TODO:delay
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bba.u32(get_pip_class(src_name, snk_name), "timing_class")
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bba.u16(get_tiletype_index(ddrg.to_str(arc.tiletype)), "tile_type")
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cls = arc.cls
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if cls == 1 and "PCS" in snk_name or "DCU" in snk_name or "DCU" in src_name:
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@ -321,11 +351,53 @@ def write_database(dev_name, chip, ddrg, endianness):
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bba.u16(bank, "bank")
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bba.u16(0, "padding")
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bba.l("tiletype_names", "RelPtr<char>")
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for tt, idx in sorted(tiletype_names.items(), key=lambda x: x[1]):
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bba.s(tt, "name")
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for grade in speed_grade_names:
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for cell in speed_grade_cells[grade]:
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celltype, delays, setupholds = cell
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if len(delays) > 0:
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bba.l("cell_%d_delays_%s" % (celltype, grade))
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for delay in delays:
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from_pin, to_pin, min_delay, max_delay = delay
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bba.u32(from_pin, "from_pin")
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bba.u32(to_pin, "to_pin")
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bba.u32(min_delay, "min_delay")
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bba.u32(max_delay, "max_delay")
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if len(setupholds) > 0:
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bba.l("cell_%d_setupholds_%s" % (celltype, grade))
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for sh in setupholds:
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pin, clock, min_setup, max_setup, min_hold, max_hold = sh
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bba.u32(pin, "sig_port")
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bba.u32(clock, "clock_port")
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bba.u32(min_setup, "min_setup")
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bba.u32(max_setup, "max_setup")
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bba.u32(min_hold, "min_hold")
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bba.u32(max_hold, "max_hold")
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bba.l("cell_timing_data_%s" % grade)
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for cell in speed_grade_cells[grade]:
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celltype, delays, setupholds = cell
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bba.u32(celltype, "cell_type")
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bba.u32(len(delays), "num_delays")
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bba.u32(len(setupholds), "num_setup_hold")
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bba.r("cell_%d_delays_%s" % (celltype, grade) if len(delays) > 0 else None, "delays")
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bba.r("cell_%d_setupholds_%s" % (celltype, grade) if len(delays) > 0 else None, "setupholds")
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bba.l("pip_timing_data_%s" % grade)
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for pipclass in speed_grade_pips[grade]:
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min_delay, max_delay, min_fanout, max_fanout = pipclass
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bba.u32(min_delay, "min_delay")
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bba.u32(max_delay, "max_delay")
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bba.u32(min_fanout, "min_fanout")
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bba.u32(max_fanout, "max_fanout")
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bba.l("speed_grade_data")
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for grade in speed_grade_names:
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bba.u32(len(speed_grade_cells[grade]), "num_cell_timings")
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bba.u32(len(speed_grade_pips[grade]), "num_pip_classes")
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bba.r("cell_timing_data_%s" % grade, "cell_timings")
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bba.r("pip_timing_data_%s" % grade, "pip_classes")
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bba.l("chip_info")
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bba.u32(max_col + 1, "width")
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bba.u32(max_row + 1, "height")
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@ -341,6 +413,7 @@ def write_database(dev_name, chip, ddrg, endianness):
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bba.r("package_data", "package_info")
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bba.r("pio_info", "pio_info")
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bba.r("tiles_info", "tile_info")
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bba.r("speed_grade_data", "speed_grades")
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bba.pop()
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return bba
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@ -375,6 +448,7 @@ def main():
|
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ddrg = pytrellis.make_dedup_chipdb(chip)
|
||||
max_row = chip.get_max_row()
|
||||
max_col = chip.get_max_col()
|
||||
process_timing_data()
|
||||
process_pio_db(ddrg, args.device)
|
||||
process_loc_globals(chip)
|
||||
# print("{} unique location types".format(len(ddrg.locationTypes)))
|
||||
|
||||
Loading…
Reference in New Issue
Block a user