From 18cee5d279cb12827bb221b74af202d20dc369c2 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Tue, 20 Nov 2018 14:26:29 -0800
Subject: [PATCH] More changes for upstream

---
 xc7/arch.cc | 25 ++++++++++++++++++++++---
 xc7/arch.h  | 12 +++++++++++-
 2 files changed, 33 insertions(+), 4 deletions(-)

diff --git a/xc7/arch.cc b/xc7/arch.cc
index 17785776..4ef66aa7 100644
--- a/xc7/arch.cc
+++ b/xc7/arch.cc
@@ -993,7 +993,7 @@ bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort
         if (fromPort == id_CLK) {
             if (toPort == id_OQ) {
                 delay.delay = 456; // Tcko
-                return false; // No path CLK->OQ, but this fn is used for getting clkToQ delay
+                return true;
             }
         }
     } else if (cell->type == id_BUFGCTRL) {
@@ -1003,7 +1003,7 @@ bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort
 }
 
 // Get the port class, also setting clockPort to associated clock if applicable
-TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, IdString &clockPort) const
+TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, int &clockInfoCount) const
 {
     if (cell->type == id_SLICE_LUT6) {
         if (port == id_CLK)
@@ -1019,7 +1019,7 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, Id
             return TMG_COMB_OUTPUT;
         }
         if (cell->lcInfo.dffEnable) {
-            clockPort = id_CLK;
+            clockInfoCount = 1;
             if (port == id_OQ)
                 return TMG_REGISTER_OUTPUT;
             return TMG_REGISTER_INPUT;
@@ -1045,6 +1045,25 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, Id
     log_error("no timing info for port '%s' of cell type '%s'\n", port.c_str(this), cell->type.c_str(this));
 }
 
+TimingClockingInfo Arch::getPortClockingInfo(const CellInfo *cell, IdString port, int index) const
+{
+    TimingClockingInfo info;
+    if (cell->type == id_SLICE_LUT6) {
+        info.clock_port = id_CLK;
+        info.edge = cell->lcInfo.negClk ? FALLING_EDGE : RISING_EDGE;
+        if (port == id_OQ) {
+            bool has_clktoq = getCellDelay(cell, id_CLK, id_OQ, info.clockToQ);
+            NPNR_ASSERT(has_clktoq);
+        } else {
+            info.setup.delay = 124; // Tilo
+            info.hold.delay = 0;
+        }
+    } else {
+        NPNR_ASSERT_FALSE("unhandled cell type in getPortClockingInfo");
+    }
+    return info;
+}
+
 bool Arch::isGlobalNet(const NetInfo *net) const
 {
     if (net == nullptr)
diff --git a/xc7/arch.h b/xc7/arch.h
index 24501d61..9dea8de8 100644
--- a/xc7/arch.h
+++ b/xc7/arch.h
@@ -898,6 +898,14 @@ struct Arch : BaseCtx
     delay_t getDelayEpsilon() const { return 20; }
     delay_t getRipupDelayPenalty() const { return 200; }
     float getDelayNS(delay_t v) const { return v * 0.001; }
+
+    DelayInfo getDelayFromNS(float ns) const
+    {
+        DelayInfo del;
+        del.delay = ns;
+        return del;
+    }
+
     uint32_t getDelayChecksum(delay_t v) const { return v; }
     bool getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t &budget) const;
 
@@ -922,7 +930,9 @@ struct Arch : BaseCtx
     // if no path exists
     bool getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayInfo &delay) const;
     // Get the port class, also setting clockDomain if applicable
-    TimingPortClass getPortTimingClass(const CellInfo *cell, IdString port, IdString &clockDomain) const;
+    TimingPortClass getPortTimingClass(const CellInfo *cell, IdString port, int &clockInfoCount) const;
+    // Get the TimingClockingInfo of a port
+    TimingClockingInfo getPortClockingInfo(const CellInfo *cell, IdString port, int index) const;
     // Return true if a port is a net
     bool isGlobalNet(const NetInfo *net) const;