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Signed-off-by: gatecat <gatecat@ds0.me>
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@ -5,7 +5,7 @@ nextpnr aims to be a vendor neutral, timing driven, FOSS FPGA place and route
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tool.
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Currently nextpnr supports:
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* Lattice iCE40 devices supported by [Project IceStorm](http://www.clifford.at/icestorm/)
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* Lattice iCE40 devices supported by [Project IceStorm](http://bygone.clairexen.net/icestorm/)
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* Lattice ECP5 devices supported by [Project Trellis](https://github.com/YosysHQ/prjtrellis)
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* Lattice Nexus devices supported by [Project Oxide](https://github.com/gatecat/prjoxide)
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* Gowin LittleBee devices supported by [Project Apicula](https://github.com/YosysHQ/apicula)
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@ -53,7 +53,7 @@ Getting started
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### nextpnr-ice40
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For iCE40 support, install [Project IceStorm](http://www.clifford.at/icestorm/) to `/usr/local` or another location, which should be passed as `-DICESTORM_INSTALL_PREFIX=/usr` to CMake. Then build and install `nextpnr-ice40` using the following commands:
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For iCE40 support, install [Project IceStorm](http://bygone.clairexen.net/icestorm/) to `/usr/local` or another location, which should be passed as `-DICESTORM_INSTALL_PREFIX=/usr` to CMake. Then build and install `nextpnr-ice40` using the following commands:
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```
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cmake . -DARCH=ice40
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@ -244,13 +244,13 @@ Links and references
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### Synthesis, simulation, and logic optimization
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- [Yosys](http://www.clifford.at/yosys/)
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- [Yosys](https://yosyshq.net/yosys/)
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- [Icarus Verilog](http://iverilog.icarus.com/)
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- [ABC](https://people.eecs.berkeley.edu/~alanmi/abc/)
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### FPGA bitstream documentation (and tools) projects
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- [Project IceStorm (Lattice iCE40)](http://www.clifford.at/icestorm/)
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- [Project IceStorm (Lattice iCE40)](http://bygone.clairexen.net/icestorm/)
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- [Project Trellis (Lattice ECP5)](https://yosyshq.github.io/prjtrellis-db/)
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- [Project X-Ray (Xilinx 7-Series)](https://symbiflow.github.io/prjxray-db/)
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- [Project Chibi (Intel MAX-V)](https://github.com/rqou/project-chibi)
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@ -137,7 +137,7 @@ Nextpnr and other tools
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[Verilog to Routing](https://verilogtorouting.org). If you want to use nextpnr, you might also be able to use the [Generic Arch](generic.md).
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* If you are developing FPGA code in **Verilog** for a **Lattice iCE40** and
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need an open source toolchain, we suggest you use [Yosys](http://www.clifford.at/yosys/) and nextpnr.
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need an open source toolchain, we suggest you use [Yosys](https://yosyshq.net/yosys/) and nextpnr.
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* If you are developing FPGA code in **Verilog** for a **Lattice iCE40** with
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Yosys and the **existing arachne-pnr toolchain**, we suggest you start thinking about
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@ -151,7 +151,7 @@ Nextpnr and other tools
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### Why didn't you just improve [arachne-pnr](https://github.com/cseed/arachne-pnr)?
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[arachne-pnr](https://github.com/cseed/arachne-pnr) was originally developed as
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part of [Project IceStorm](http://www.clifford.at/icestorm/) to demonstrate it
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part of [Project IceStorm](http://bygone.clairexen.net/icestorm/) to demonstrate it
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was possible to create an open source place and route tool for the iCE40 FPGAs
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that actually produced valid bitstreams.
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@ -215,9 +215,9 @@ tooling around bitstream generation for these parts.
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While upstream nextpnr currently does **not** support these Xilinx parts, we expect it might soon be using Project X-Ray in a similar manner to Project Trellis.
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### What is [Project IceStorm](http://www.clifford.at/icestorm/)?
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### What is [Project IceStorm](http://bygone.clairexen.net/icestorm/)?
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[Project IceStorm](http://www.clifford.at/icestorm/) is both a project to
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[Project IceStorm](http://bygone.clairexen.net/icestorm/) is both a project to
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document the bitstream for the Lattice iCE40 series of parts **and** a full
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flow including Yosys and arachne-pnr for converting Verilog into a bitstream
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for these parts.
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@ -23,7 +23,7 @@
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* This is designed to make it possible to build frontends for parsing any format isomorphic to Yosys JSON [1]
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* with maximal inlining and minimal need for overhead such as runtime polymorphism or extra wrapper types.
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*
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* [1] http://www.clifford.at/yosys/cmd_write_json.html
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* [1] https://yosyshq.net/yosys/cmd_write_json.html
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*
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* The frontend should implement a class referred to as FrontendType that defines the following type(def)s and
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* functions:
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