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ecp5: Add SYSCONFIG settings to bitstream

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Signed-off-by: David Shah <dave@ds0.me>
This commit is contained in:
David Shah 2020-07-12 13:29:56 +01:00
parent 6016e54d6c
commit 19a4ddf2f0
4 changed files with 38 additions and 3 deletions
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1
ecp5/baseconfigs.cc
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@ -514,7 +514,6 @@ void config_empty_lfe5u_45f(ChipConfig &cc)
cc.tiles["MIB_R10C41:CMUX_UR_0"].add_arc("G_DCS0CLK1", "G_VPFN0000"); cc.tiles["MIB_R10C41:CMUX_UR_0"].add_arc("G_DCS0CLK1", "G_VPFN0000");
cc.tiles["MIB_R58C40:CMUX_LL_0"].add_arc("G_DCS1CLK0", "G_VPFN0000"); cc.tiles["MIB_R58C40:CMUX_LL_0"].add_arc("G_DCS1CLK0", "G_VPFN0000");
cc.tiles["MIB_R58C41:CMUX_LR_0"].add_arc("G_DCS1CLK1", "G_VPFN0000"); cc.tiles["MIB_R58C41:CMUX_LR_0"].add_arc("G_DCS1CLK1", "G_VPFN0000");
cc.tiles["MIB_R71C3:BANKREF8"].add_unknown(18, 0);
cc.tiles["MIB_R71C4:EFB0_PICB0"].add_unknown(54, 1); cc.tiles["MIB_R71C4:EFB0_PICB0"].add_unknown(54, 1);
cc.tiles["MIB_R71C4:EFB0_PICB0"].add_unknown(56, 1); cc.tiles["MIB_R71C4:EFB0_PICB0"].add_unknown(56, 1);
cc.tiles["MIB_R71C4:EFB0_PICB0"].add_unknown(82, 1); cc.tiles["MIB_R71C4:EFB0_PICB0"].add_unknown(82, 1);

33
ecp5/bitstream.cc
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@ -701,9 +701,13 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
auto tiles = ctx->getTilesAtLocation(y, x); auto tiles = ctx->getTilesAtLocation(y, x);
for (auto tile : tiles) { for (auto tile : tiles) {
std::string type = tile.second; std::string type = tile.second;
if (type.find("BANKREF") != std::string::npos && type != "BANKREF8") { if (type.find("BANKREF") != std::string::npos) {
int bank = std::stoi(type.substr(7)); int bank = std::stoi(type.substr(7));
if (bankVcc.find(bank) != bankVcc.end()) { if (bank == 8 && ctx->settings.count(ctx->id("arch.sysconfig.CONFIG_IOVOLTAGE"))) {
std::string vcc = str_or_default(ctx->settings, ctx->id("arch.sysconfig.CONFIG_IOVOLTAGE"));
vcc.at(1) = 'V';
cc.tiles[tile.first].add_enum("BANK.VCCIO", vcc);
} else if (bankVcc.find(bank) != bankVcc.end()) {
if (bankVcc[bank] == IOVoltage::VCC_1V35) if (bankVcc[bank] == IOVoltage::VCC_1V35)
cc.tiles[tile.first].add_enum("BANK.VCCIO", "1V2"); cc.tiles[tile.first].add_enum("BANK.VCCIO", "1V2");
else else
@ -1404,6 +1408,8 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
cc.tiles[ctx->getTileByType("EFB1_PICB1")].add_enum("OSC.MODE", "OSCG"); cc.tiles[ctx->getTileByType("EFB1_PICB1")].add_enum("OSC.MODE", "OSCG");
cc.tiles[ctx->getTileByType("EFB1_PICB1")].add_enum("CCLK.MODE", "_NONE_"); cc.tiles[ctx->getTileByType("EFB1_PICB1")].add_enum("CCLK.MODE", "_NONE_");
} else if (ci->type == id_USRMCLK) { } else if (ci->type == id_USRMCLK) {
if (str_or_default(ctx->settings, ctx->id("arch.sysconfig.MASTER_SPI_PORT"), "") == "ENABLE")
log_warning("USRMCLK will not function correctly when MASTER_SPI_PORT is set to ENABLE.\n");
cc.tiles[ctx->getTileByType("EFB3_PICB1")].add_enum("CCLK.MODE", "USRMCLK"); cc.tiles[ctx->getTileByType("EFB3_PICB1")].add_enum("CCLK.MODE", "USRMCLK");
} else if (ci->type == id_GSR) { } else if (ci->type == id_GSR) {
cc.tiles[ctx->getTileByType("EFB0_PICB0")].add_enum( cc.tiles[ctx->getTileByType("EFB0_PICB0")].add_enum(
@ -1485,6 +1491,29 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
} }
} }
// Add some SYSCONFIG settings
const std::string prefix = "arch.sysconfig.";
for (auto &setting : ctx->settings) {
std::string key = setting.first.str(ctx);
if (key.substr(0, prefix.length()) != prefix)
continue;
key = key.substr(prefix.length());
std::string value = setting.second.as_string();
if (key == "SLAVE_SPI_PORT" || key == "DONE_EX") {
cc.tiles[ctx->getTileByType("EFB0_PICB0")].add_enum("SYSCONFIG." + key, value);
cc.tiles[ctx->getTileByType("EFB2_PICB0")].add_enum("SYSCONFIG." + key, value);
} else if (key == "SLAVE_PARALLEL_PORT" || key == "BACKGROUND_RECONFIG" || key == "WAKE_UP") {
cc.tiles[ctx->getTileByType("EFB0_PICB0")].add_enum("SYSCONFIG." + key, value);
} else if (key == "MASTER_SPI_PORT") {
cc.tiles[ctx->getTileByType("EFB1_PICB1")].add_enum("SYSCONFIG." + key, value);
} else if (key == "TRANSFR") {
cc.tiles[ctx->getTileByType("EFB0_PICB0")].add_enum("SYSCONFIG." + key, value);
cc.tiles[ctx->getTileByType("EFB1_PICB1")].add_enum("SYSCONFIG." + key, value);
} else {
cc.sysconfig[key] = value;
}
}
// Fixup tile names // Fixup tile names
fix_tile_names(ctx, cc); fix_tile_names(ctx, cc);
// Configure chip // Configure chip

6
ecp5/config.cc
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@ -267,6 +267,8 @@ std::ostream &operator<<(std::ostream &out, const ChipConfig &cc)
out << ".device " << cc.chip_name << std::endl << std::endl; out << ".device " << cc.chip_name << std::endl << std::endl;
for (const auto &meta : cc.metadata) for (const auto &meta : cc.metadata)
out << ".comment " << meta << std::endl; out << ".comment " << meta << std::endl;
for (const auto &sc : cc.sysconfig)
out << ".sysconfig " << sc.first << " " << sc.second << std::endl;
out << std::endl; out << std::endl;
for (const auto &tile : cc.tiles) { for (const auto &tile : cc.tiles) {
if (!tile.second.empty()) { if (!tile.second.empty()) {
@ -311,6 +313,10 @@ std::istream &operator>>(std::istream &in, ChipConfig &cc)
std::string line; std::string line;
getline(in, line); getline(in, line);
cc.metadata.push_back(line); cc.metadata.push_back(line);
} else if (verb == ".sysconfig") {
std::string key, value;
in >> key >> value;
cc.sysconfig[key] = value;
} else if (verb == ".tile") { } else if (verb == ".tile") {
std::string tilename; std::string tilename;
in >> tilename; in >> tilename;

1
ecp5/config.h
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@ -114,6 +114,7 @@ class ChipConfig
std::vector<std::string> metadata; std::vector<std::string> metadata;
std::map<std::string, TileConfig> tiles; std::map<std::string, TileConfig> tiles;
std::vector<TileGroup> tilegroups; std::vector<TileGroup> tilegroups;
std::map<std::string, std::string> sysconfig;
std::map<uint16_t, std::vector<uint16_t>> bram_data; std::map<uint16_t, std::vector<uint16_t>> bram_data;
}; };