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Move top-level ChipInfoPOD into ice40 chipdb blob

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Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2018-06-17 16:12:52 +02:00
parent 6f4af8387e
commit 19b665177e
4 changed files with 139 additions and 126 deletions
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4
ice40/bitstream.cc
View File

@ -24,7 +24,7 @@ NEXTPNR_NAMESPACE_BEGIN
inline TileType tile_at(const Chip &chip, int x, int y) inline TileType tile_at(const Chip &chip, int x, int y)
{ {
return chip.chip_info.tile_grid[y * chip.chip_info.width + x]; return chip.chip_info->tile_grid[y * chip.chip_info->width + x];
} }
const ConfigEntryPOD &find_config(const TileInfoPOD &tile, const ConfigEntryPOD &find_config(const TileInfoPOD &tile,
@ -93,7 +93,7 @@ void write_asc(const Design &design, std::ostream &out)
{ {
const Chip &chip = design.chip; const Chip &chip = design.chip;
// [y][x][row][col] // [y][x][row][col]
const ChipInfoPOD &ci = chip.chip_info; const ChipInfoPOD &ci = *chip.chip_info;
const BitstreamInfoPOD &bi = *ci.bits_info; const BitstreamInfoPOD &bi = *ci.bits_info;
std::vector<std::vector<std::vector<std::vector<int8_t>>>> config; std::vector<std::vector<std::vector<std::vector<int8_t>>>> config;
config.resize(ci.height); config.resize(ci.height);

128
ice40/chip.cc
View File

@ -82,38 +82,38 @@ Chip::Chip(ChipArgs args) : args(args)
{ {
#ifdef ICE40_HX1K_ONLY #ifdef ICE40_HX1K_ONLY
if (args.type == ChipArgs::HX1K) { if (args.type == ChipArgs::HX1K) {
chip_info = chip_info_1k; chip_info = reinterpret_cast<RelPtr<ChipInfoPOD>*>(chipdb_blob_1k)->get();
} else { } else {
log_error("Unsupported iCE40 chip type.\n"); log_error("Unsupported iCE40 chip type.\n");
} }
#else #else
if (args.type == ChipArgs::LP384) { if (args.type == ChipArgs::LP384) {
chip_info = chip_info_384; chip_info = reinterpret_cast<RelPtr<ChipInfoPOD>*>(chipdb_blob_384)->get();
} else if (args.type == ChipArgs::LP1K || args.type == ChipArgs::HX1K) { } else if (args.type == ChipArgs::LP1K || args.type == ChipArgs::HX1K) {
chip_info = chip_info_1k; chip_info = reinterpret_cast<RelPtr<ChipInfoPOD>*>(chipdb_blob_1k)->get();
} else if (args.type == ChipArgs::UP5K) { } else if (args.type == ChipArgs::UP5K) {
chip_info = chip_info_5k; chip_info = reinterpret_cast<RelPtr<ChipInfoPOD>*>(chipdb_blob_5k)->get();
} else if (args.type == ChipArgs::LP8K || args.type == ChipArgs::HX8K) { } else if (args.type == ChipArgs::LP8K || args.type == ChipArgs::HX8K) {
chip_info = chip_info_8k; chip_info = reinterpret_cast<RelPtr<ChipInfoPOD>*>(chipdb_blob_8k)->get();
} else { } else {
log_error("Unsupported iCE40 chip type.\n"); log_error("Unsupported iCE40 chip type.\n");
} }
#endif #endif
package_info = nullptr; package_info = nullptr;
for (int i = 0; i < chip_info.num_packages; i++) { for (int i = 0; i < chip_info->num_packages; i++) {
if (chip_info.packages_data[i].name.get() == args.package) { if (chip_info->packages_data[i].name.get() == args.package) {
package_info = &(chip_info.packages_data[i]); package_info = &(chip_info->packages_data[i]);
break; break;
} }
} }
if (package_info == nullptr) if (package_info == nullptr)
log_error("Unsupported package '%s'.\n", args.package.c_str()); log_error("Unsupported package '%s'.\n", args.package.c_str());
bel_to_cell.resize(chip_info.num_bels); bel_to_cell.resize(chip_info->num_bels);
wire_to_net.resize(chip_info.num_wires); wire_to_net.resize(chip_info->num_wires);
pip_to_net.resize(chip_info.num_pips); pip_to_net.resize(chip_info->num_pips);
switches_locked.resize(chip_info.num_switches); switches_locked.resize(chip_info->num_switches);
} }
// ----------------------------------------------------------------------- // -----------------------------------------------------------------------
@ -152,8 +152,8 @@ BelId Chip::getBelByName(IdString name) const
BelId ret; BelId ret;
if (bel_by_name.empty()) { if (bel_by_name.empty()) {
for (int i = 0; i < chip_info.num_bels; i++) for (int i = 0; i < chip_info->num_bels; i++)
bel_by_name[chip_info.bel_data[i].name.get()] = i; bel_by_name[chip_info->bel_data[i].name.get()] = i;
} }
auto it = bel_by_name.find(name); auto it = bel_by_name.find(name);
@ -168,16 +168,16 @@ BelRange Chip::getBelsAtSameTile(BelId bel) const
BelRange br; BelRange br;
assert(bel != BelId()); assert(bel != BelId());
// This requires Bels at the same tile are consecutive // This requires Bels at the same tile are consecutive
int x = chip_info.bel_data[bel.index].x; int x = chip_info->bel_data[bel.index].x;
int y = chip_info.bel_data[bel.index].y; int y = chip_info->bel_data[bel.index].y;
int start = bel.index, end = bel.index; int start = bel.index, end = bel.index;
while (start >= 0 && chip_info.bel_data[start].x == x && while (start >= 0 && chip_info->bel_data[start].x == x &&
chip_info.bel_data[start].y == y) chip_info->bel_data[start].y == y)
start--; start--;
start++; start++;
br.b.cursor = start; br.b.cursor = start;
while (end < chip_info.num_bels && chip_info.bel_data[end].x == x && while (end < chip_info->num_bels && chip_info->bel_data[end].x == x &&
chip_info.bel_data[end].y == y) chip_info->bel_data[end].y == y)
end++; end++;
br.e.cursor = end; br.e.cursor = end;
return br; return br;
@ -189,8 +189,8 @@ WireId Chip::getWireBelPin(BelId bel, PortPin pin) const
assert(bel != BelId()); assert(bel != BelId());
int num_bel_wires = chip_info.bel_data[bel.index].num_bel_wires; int num_bel_wires = chip_info->bel_data[bel.index].num_bel_wires;
const BelWirePOD *bel_wires = chip_info.bel_data[bel.index].bel_wires.get(); const BelWirePOD *bel_wires = chip_info->bel_data[bel.index].bel_wires.get();
for (int i = 0; i < num_bel_wires; i++) for (int i = 0; i < num_bel_wires; i++)
if (bel_wires[i].port == pin) { if (bel_wires[i].port == pin) {
@ -208,8 +208,8 @@ WireId Chip::getWireByName(IdString name) const
WireId ret; WireId ret;
if (wire_by_name.empty()) { if (wire_by_name.empty()) {
for (int i = 0; i < chip_info.num_wires; i++) for (int i = 0; i < chip_info->num_wires; i++)
wire_by_name[chip_info.wire_data[i].name.get()] = i; wire_by_name[chip_info->wire_data[i].name.get()] = i;
} }
auto it = wire_by_name.find(name); auto it = wire_by_name.find(name);
@ -226,7 +226,7 @@ PipId Chip::getPipByName(IdString name) const
PipId ret; PipId ret;
if (pip_by_name.empty()) { if (pip_by_name.empty()) {
for (int i = 0; i < chip_info.num_pips; i++) { for (int i = 0; i < chip_info->num_pips; i++) {
PipId pip; PipId pip;
pip.index = i; pip.index = i;
pip_by_name[getPipName(pip)] = i; pip_by_name[getPipName(pip)] = i;
@ -244,15 +244,15 @@ IdString Chip::getPipName(PipId pip) const
{ {
assert(pip != PipId()); assert(pip != PipId());
int x = chip_info.pip_data[pip.index].x; int x = chip_info->pip_data[pip.index].x;
int y = chip_info.pip_data[pip.index].y; int y = chip_info->pip_data[pip.index].y;
std::string src_name = std::string src_name =
chip_info.wire_data[chip_info.pip_data[pip.index].src].name.get(); chip_info->wire_data[chip_info->pip_data[pip.index].src].name.get();
std::replace(src_name.begin(), src_name.end(), '/', '.'); std::replace(src_name.begin(), src_name.end(), '/', '.');
std::string dst_name = std::string dst_name =
chip_info.wire_data[chip_info.pip_data[pip.index].dst].name.get(); chip_info->wire_data[chip_info->pip_data[pip.index].dst].name.get();
std::replace(dst_name.begin(), dst_name.end(), '/', '.'); std::replace(dst_name.begin(), dst_name.end(), '/', '.');
return "X" + std::to_string(x) + "/Y" + std::to_string(y) + "/" + src_name + return "X" + std::to_string(x) + "/Y" + std::to_string(y) + "/" + src_name +
@ -287,21 +287,21 @@ std::string Chip::getBelPackagePin(BelId bel) const
bool Chip::estimatePosition(BelId bel, int &x, int &y) const bool Chip::estimatePosition(BelId bel, int &x, int &y) const
{ {
assert(bel != BelId()); assert(bel != BelId());
x = chip_info.bel_data[bel.index].x; x = chip_info->bel_data[bel.index].x;
y = chip_info.bel_data[bel.index].y; y = chip_info->bel_data[bel.index].y;
return chip_info.bel_data[bel.index].type != TYPE_SB_GB; return chip_info->bel_data[bel.index].type != TYPE_SB_GB;
} }
delay_t Chip::estimateDelay(WireId src, WireId dst) const delay_t Chip::estimateDelay(WireId src, WireId dst) const
{ {
assert(src != WireId()); assert(src != WireId());
delay_t x1 = chip_info.wire_data[src.index].x; delay_t x1 = chip_info->wire_data[src.index].x;
delay_t y1 = chip_info.wire_data[src.index].y; delay_t y1 = chip_info->wire_data[src.index].y;
assert(dst != WireId()); assert(dst != WireId());
delay_t x2 = chip_info.wire_data[dst.index].x; delay_t x2 = chip_info->wire_data[dst.index].x;
delay_t y2 = chip_info.wire_data[dst.index].y; delay_t y2 = chip_info->wire_data[dst.index].y;
return fabsf(x1 - x2) + fabsf(y1 - y2); return fabsf(x1 - x2) + fabsf(y1 - y2);
} }
@ -312,8 +312,8 @@ std::vector<GraphicElement> Chip::getFrameGraphics() const
{ {
std::vector<GraphicElement> ret; std::vector<GraphicElement> ret;
for (int x = 0; x <= chip_info.width; x++) for (int x = 0; x <= chip_info->width; x++)
for (int y = 0; y <= chip_info.height; y++) { for (int y = 0; y <= chip_info->height; y++) {
GraphicElement el; GraphicElement el;
el.type = GraphicElement::G_LINE; el.type = GraphicElement::G_LINE;
el.x1 = x - 0.05, el.x2 = x + 0.05, el.y1 = y, el.y2 = y, el.z = 0; el.x1 = x - 0.05, el.x2 = x + 0.05, el.y1 = y, el.y2 = y, el.z = 0;
@ -334,44 +334,44 @@ std::vector<GraphicElement> Chip::getBelGraphics(BelId bel) const
if (bel_type == TYPE_ICESTORM_LC) { if (bel_type == TYPE_ICESTORM_LC) {
GraphicElement el; GraphicElement el;
el.type = GraphicElement::G_BOX; el.type = GraphicElement::G_BOX;
el.x1 = chip_info.bel_data[bel.index].x + 0.1; el.x1 = chip_info->bel_data[bel.index].x + 0.1;
el.x2 = chip_info.bel_data[bel.index].x + 0.9; el.x2 = chip_info->bel_data[bel.index].x + 0.9;
el.y1 = chip_info.bel_data[bel.index].y + 0.10 + el.y1 = chip_info->bel_data[bel.index].y + 0.10 +
(chip_info.bel_data[bel.index].z) * (0.8 / 8); (chip_info->bel_data[bel.index].z) * (0.8 / 8);
el.y2 = chip_info.bel_data[bel.index].y + 0.18 + el.y2 = chip_info->bel_data[bel.index].y + 0.18 +
(chip_info.bel_data[bel.index].z) * (0.8 / 8); (chip_info->bel_data[bel.index].z) * (0.8 / 8);
el.z = 0; el.z = 0;
ret.push_back(el); ret.push_back(el);
} }
if (bel_type == TYPE_SB_IO) { if (bel_type == TYPE_SB_IO) {
if (chip_info.bel_data[bel.index].x == 0 || if (chip_info->bel_data[bel.index].x == 0 ||
chip_info.bel_data[bel.index].x == chip_info.width - 1) { chip_info->bel_data[bel.index].x == chip_info->width - 1) {
GraphicElement el; GraphicElement el;
el.type = GraphicElement::G_BOX; el.type = GraphicElement::G_BOX;
el.x1 = chip_info.bel_data[bel.index].x + 0.1; el.x1 = chip_info->bel_data[bel.index].x + 0.1;
el.x2 = chip_info.bel_data[bel.index].x + 0.9; el.x2 = chip_info->bel_data[bel.index].x + 0.9;
if (chip_info.bel_data[bel.index].z == 0) { if (chip_info->bel_data[bel.index].z == 0) {
el.y1 = chip_info.bel_data[bel.index].y + 0.10; el.y1 = chip_info->bel_data[bel.index].y + 0.10;
el.y2 = chip_info.bel_data[bel.index].y + 0.45; el.y2 = chip_info->bel_data[bel.index].y + 0.45;
} else { } else {
el.y1 = chip_info.bel_data[bel.index].y + 0.55; el.y1 = chip_info->bel_data[bel.index].y + 0.55;
el.y2 = chip_info.bel_data[bel.index].y + 0.90; el.y2 = chip_info->bel_data[bel.index].y + 0.90;
} }
el.z = 0; el.z = 0;
ret.push_back(el); ret.push_back(el);
} else { } else {
GraphicElement el; GraphicElement el;
el.type = GraphicElement::G_BOX; el.type = GraphicElement::G_BOX;
if (chip_info.bel_data[bel.index].z == 0) { if (chip_info->bel_data[bel.index].z == 0) {
el.x1 = chip_info.bel_data[bel.index].x + 0.10; el.x1 = chip_info->bel_data[bel.index].x + 0.10;
el.x2 = chip_info.bel_data[bel.index].x + 0.45; el.x2 = chip_info->bel_data[bel.index].x + 0.45;
} else { } else {
el.x1 = chip_info.bel_data[bel.index].x + 0.55; el.x1 = chip_info->bel_data[bel.index].x + 0.55;
el.x2 = chip_info.bel_data[bel.index].x + 0.90; el.x2 = chip_info->bel_data[bel.index].x + 0.90;
} }
el.y1 = chip_info.bel_data[bel.index].y + 0.1; el.y1 = chip_info->bel_data[bel.index].y + 0.1;
el.y2 = chip_info.bel_data[bel.index].y + 0.9; el.y2 = chip_info->bel_data[bel.index].y + 0.9;
el.z = 0; el.z = 0;
ret.push_back(el); ret.push_back(el);
} }
@ -380,10 +380,10 @@ std::vector<GraphicElement> Chip::getBelGraphics(BelId bel) const
if (bel_type == TYPE_ICESTORM_RAM) { if (bel_type == TYPE_ICESTORM_RAM) {
GraphicElement el; GraphicElement el;
el.type = GraphicElement::G_BOX; el.type = GraphicElement::G_BOX;
el.x1 = chip_info.bel_data[bel.index].x + 0.1; el.x1 = chip_info->bel_data[bel.index].x + 0.1;
el.x2 = chip_info.bel_data[bel.index].x + 0.9; el.x2 = chip_info->bel_data[bel.index].x + 0.9;
el.y1 = chip_info.bel_data[bel.index].y + 0.1; el.y1 = chip_info->bel_data[bel.index].y + 0.1;
el.y2 = chip_info.bel_data[bel.index].y + 1.9; el.y2 = chip_info->bel_data[bel.index].y + 1.9;
el.z = 0; el.z = 0;
ret.push_back(el); ret.push_back(el);
} }

82
ice40/chip.h
View File

@ -209,21 +209,21 @@ struct BitstreamInfoPOD
struct ChipInfoPOD struct ChipInfoPOD
{ {
int width, height; int32_t width, height;
int num_bels, num_wires, num_pips; int32_t num_bels, num_wires, num_pips;
int num_switches, num_packages; int32_t num_switches, num_packages;
BelInfoPOD *bel_data; RelPtr<BelInfoPOD> bel_data;
WireInfoPOD *wire_data; RelPtr<WireInfoPOD> wire_data;
PipInfoPOD *pip_data; RelPtr<PipInfoPOD> pip_data;
TileType *tile_grid; RelPtr<TileType> tile_grid;
BitstreamInfoPOD *bits_info; RelPtr<BitstreamInfoPOD> bits_info;
PackageInfoPOD *packages_data; RelPtr<PackageInfoPOD> packages_data;
} __attribute__((packed)); } __attribute__((packed));
extern ChipInfoPOD chip_info_384; extern uint8_t chipdb_blob_384[];
extern ChipInfoPOD chip_info_1k; extern uint8_t chipdb_blob_1k[];
extern ChipInfoPOD chip_info_5k; extern uint8_t chipdb_blob_5k[];
extern ChipInfoPOD chip_info_8k; extern uint8_t chipdb_blob_8k[];
/************************ End of chipdb section. ************************/ /************************ End of chipdb section. ************************/
@ -463,8 +463,8 @@ struct ChipArgs
struct Chip struct Chip
{ {
ChipInfoPOD chip_info; const ChipInfoPOD *chip_info;
PackageInfoPOD *package_info; const PackageInfoPOD *package_info;
mutable std::unordered_map<IdString, int> bel_by_name; mutable std::unordered_map<IdString, int> bel_by_name;
mutable std::unordered_map<IdString, int> wire_by_name; mutable std::unordered_map<IdString, int> wire_by_name;
@ -486,7 +486,7 @@ struct Chip
IdString getBelName(BelId bel) const IdString getBelName(BelId bel) const
{ {
assert(bel != BelId()); assert(bel != BelId());
return chip_info.bel_data[bel.index].name.get(); return chip_info->bel_data[bel.index].name.get();
} }
void bindBel(BelId bel, IdString cell) void bindBel(BelId bel, IdString cell)
@ -519,7 +519,7 @@ struct Chip
{ {
BelRange range; BelRange range;
range.b.cursor = 0; range.b.cursor = 0;
range.e.cursor = chip_info.num_bels; range.e.cursor = chip_info->num_bels;
return range; return range;
} }
@ -542,7 +542,7 @@ struct Chip
BelType getBelType(BelId bel) const BelType getBelType(BelId bel) const
{ {
assert(bel != BelId()); assert(bel != BelId());
return chip_info.bel_data[bel.index].type; return chip_info->bel_data[bel.index].type;
} }
WireId getWireBelPin(BelId bel, PortPin pin) const; WireId getWireBelPin(BelId bel, PortPin pin) const;
@ -552,10 +552,10 @@ struct Chip
BelPin ret; BelPin ret;
assert(wire != WireId()); assert(wire != WireId());
if (chip_info.wire_data[wire.index].bel_uphill.bel_index >= 0) { if (chip_info->wire_data[wire.index].bel_uphill.bel_index >= 0) {
ret.bel.index = ret.bel.index =
chip_info.wire_data[wire.index].bel_uphill.bel_index; chip_info->wire_data[wire.index].bel_uphill.bel_index;
ret.pin = chip_info.wire_data[wire.index].bel_uphill.port; ret.pin = chip_info->wire_data[wire.index].bel_uphill.port;
} }
return ret; return ret;
@ -565,9 +565,9 @@ struct Chip
{ {
BelPinRange range; BelPinRange range;
assert(wire != WireId()); assert(wire != WireId());
range.b.ptr = chip_info.wire_data[wire.index].bels_downhill.get(); range.b.ptr = chip_info->wire_data[wire.index].bels_downhill.get();
range.e.ptr = range.e.ptr =
range.b.ptr + chip_info.wire_data[wire.index].num_bels_downhill; range.b.ptr + chip_info->wire_data[wire.index].num_bels_downhill;
return range; return range;
} }
@ -578,7 +578,7 @@ struct Chip
IdString getWireName(WireId wire) const IdString getWireName(WireId wire) const
{ {
assert(wire != WireId()); assert(wire != WireId());
return chip_info.wire_data[wire.index].name.get(); return chip_info->wire_data[wire.index].name.get();
} }
void bindWire(WireId wire, IdString net) void bindWire(WireId wire, IdString net)
@ -611,7 +611,7 @@ struct Chip
{ {
WireRange range; WireRange range;
range.b.cursor = 0; range.b.cursor = 0;
range.e.cursor = chip_info.num_wires; range.e.cursor = chip_info->num_wires;
return range; return range;
} }
@ -624,20 +624,20 @@ struct Chip
{ {
assert(pip != PipId()); assert(pip != PipId());
assert(pip_to_net[pip.index] == IdString()); assert(pip_to_net[pip.index] == IdString());
assert(switches_locked[chip_info.pip_data[pip.index].switch_index] == assert(switches_locked[chip_info->pip_data[pip.index].switch_index] ==
IdString()); IdString());
pip_to_net[pip.index] = net; pip_to_net[pip.index] = net;
switches_locked[chip_info.pip_data[pip.index].switch_index] = net; switches_locked[chip_info->pip_data[pip.index].switch_index] = net;
} }
void unbindPip(PipId pip) void unbindPip(PipId pip)
{ {
assert(pip != PipId()); assert(pip != PipId());
assert(pip_to_net[pip.index] != IdString()); assert(pip_to_net[pip.index] != IdString());
assert(switches_locked[chip_info.pip_data[pip.index].switch_index] != assert(switches_locked[chip_info->pip_data[pip.index].switch_index] !=
IdString()); IdString());
pip_to_net[pip.index] = IdString(); pip_to_net[pip.index] = IdString();
switches_locked[chip_info.pip_data[pip.index].switch_index] = switches_locked[chip_info->pip_data[pip.index].switch_index] =
IdString(); IdString();
} }
@ -645,11 +645,11 @@ struct Chip
{ {
assert(pip != PipId()); assert(pip != PipId());
if (args.type == ChipArgs::UP5K) { if (args.type == ChipArgs::UP5K) {
int x = chip_info.pip_data[pip.index].x; int x = chip_info->pip_data[pip.index].x;
if (x == 0 || x == (chip_info.width - 1)) if (x == 0 || x == (chip_info->width - 1))
return false; return false;
} }
return switches_locked[chip_info.pip_data[pip.index].switch_index] == return switches_locked[chip_info->pip_data[pip.index].switch_index] ==
IdString(); IdString();
} }
@ -657,7 +657,7 @@ struct Chip
{ {
assert(pip != PipId()); assert(pip != PipId());
if (conflicting) if (conflicting)
return switches_locked[chip_info.pip_data[pip.index].switch_index]; return switches_locked[chip_info->pip_data[pip.index].switch_index];
return pip_to_net[pip.index]; return pip_to_net[pip.index];
} }
@ -665,7 +665,7 @@ struct Chip
{ {
AllPipRange range; AllPipRange range;
range.b.cursor = 0; range.b.cursor = 0;
range.e.cursor = chip_info.num_pips; range.e.cursor = chip_info->num_pips;
return range; return range;
} }
@ -673,7 +673,7 @@ struct Chip
{ {
WireId wire; WireId wire;
assert(pip != PipId()); assert(pip != PipId());
wire.index = chip_info.pip_data[pip.index].src; wire.index = chip_info->pip_data[pip.index].src;
return wire; return wire;
} }
@ -681,7 +681,7 @@ struct Chip
{ {
WireId wire; WireId wire;
assert(pip != PipId()); assert(pip != PipId());
wire.index = chip_info.pip_data[pip.index].dst; wire.index = chip_info->pip_data[pip.index].dst;
return wire; return wire;
} }
@ -689,7 +689,7 @@ struct Chip
{ {
DelayInfo delay; DelayInfo delay;
assert(pip != PipId()); assert(pip != PipId());
delay.delay = chip_info.pip_data[pip.index].delay; delay.delay = chip_info->pip_data[pip.index].delay;
return delay; return delay;
} }
@ -697,9 +697,9 @@ struct Chip
{ {
PipRange range; PipRange range;
assert(wire != WireId()); assert(wire != WireId());
range.b.cursor = chip_info.wire_data[wire.index].pips_downhill.get(); range.b.cursor = chip_info->wire_data[wire.index].pips_downhill.get();
range.e.cursor = range.e.cursor =
range.b.cursor + chip_info.wire_data[wire.index].num_downhill; range.b.cursor + chip_info->wire_data[wire.index].num_downhill;
return range; return range;
} }
@ -707,9 +707,9 @@ struct Chip
{ {
PipRange range; PipRange range;
assert(wire != WireId()); assert(wire != WireId());
range.b.cursor = chip_info.wire_data[wire.index].pips_uphill.get(); range.b.cursor = chip_info->wire_data[wire.index].pips_uphill.get();
range.e.cursor = range.e.cursor =
range.b.cursor + chip_info.wire_data[wire.index].num_uphill; range.b.cursor + chip_info->wire_data[wire.index].num_uphill;
return range; return range;
} }

51
ice40/chipdb.py
View File

@ -549,11 +549,8 @@ class BinaryBlobAssembler:
print("#define %s ((%s*)(%s+%d))" % (self.labels_byaddr[cursor], self.ltypes_byaddr[cursor], self.cname, cursor), file=f) print("#define %s ((%s*)(%s+%d))" % (self.labels_byaddr[cursor], self.ltypes_byaddr[cursor], self.cname, cursor), file=f)
print("};", file=f) print("};", file=f)
bba = BinaryBlobAssembler("binblob_%s" % dev_name, endianness, "static uint8_t") bba = BinaryBlobAssembler("chipdb_blob_%s" % dev_name, endianness, "uint8_t")
bba.r("chip_info_%s" % dev_name, "chip_info")
print('#include "nextpnr.h"')
print('namespace {')
print('USING_NEXTPNR_NAMESPACE')
index = 0 index = 0
for bel in range(len(bel_name)): for bel in range(len(bel_name)):
@ -563,7 +560,7 @@ for bel in range(len(bel_name)):
bba.u32(portpins[bel_wires[bel][i][1]], "port") bba.u32(portpins[bel_wires[bel][i][1]], "port")
index += 1 index += 1
bba.l("bel_data", "BelInfoPOD", export=True) bba.l("bel_data_%s" % dev_name, "BelInfoPOD")
for bel in range(len(bel_name)): for bel in range(len(bel_name)):
bba.s(bel_name[bel], "name") bba.s(bel_name[bel], "name")
bba.u32(beltypes[bel_type[bel]], "type") bba.u32(beltypes[bel_type[bel]], "type")
@ -722,7 +719,7 @@ for t in range(num_tile_types):
ti["entries"] = "tile%d_config" % t ti["entries"] = "tile%d_config" % t
tileinfo.append(ti) tileinfo.append(ti)
bba.l("wire_data_%s" % dev_name, "WireInfoPOD", export=True) bba.l("wire_data_%s" % dev_name, "WireInfoPOD")
for info in wireinfo: for info in wireinfo:
bba.s(info["name"], "name") bba.s(info["name"], "name")
bba.u32(info["num_uphill"], "num_uphill") bba.u32(info["num_uphill"], "num_uphill")
@ -736,7 +733,7 @@ for info in wireinfo:
bba.u16(info["x"], "x") bba.u16(info["x"], "x")
bba.u16(info["y"], "y") bba.u16(info["y"], "y")
bba.l("pip_data_%s" % dev_name, "PipInfoPOD", export=True) bba.l("pip_data_%s" % dev_name, "PipInfoPOD")
for info in pipinfo: for info in pipinfo:
bba.u32(info["src"], "src") bba.u32(info["src"], "src")
bba.u32(info["dst"], "dst") bba.u32(info["dst"], "dst")
@ -792,36 +789,52 @@ for ieren in ierens:
if len(ierens) % 2 == 1: if len(ierens) % 2 == 1:
bba.u16(0, "padding") bba.u16(0, "padding")
bba.l("bits_info_%s" % dev_name, "BitstreamInfoPOD", export=True) bba.l("bits_info_%s" % dev_name, "BitstreamInfoPOD")
bba.u32(len(switchinfo), "num_switches") bba.u32(len(switchinfo), "num_switches")
bba.u32(len(ierens), "num_ierens") bba.u32(len(ierens), "num_ierens")
bba.r("tile_data_%s" % dev_name, "tiles_nonrouting") bba.r("tile_data_%s" % dev_name, "tiles_nonrouting")
bba.r("switch_data_%s" % dev_name, "switches") bba.r("switch_data_%s" % dev_name, "switches")
bba.r("ieren_data_%s" % dev_name, "ierens") bba.r("ieren_data_%s" % dev_name, "ierens")
bba.l("tile_grid_%s" % dev_name, "TileType", export=True) bba.l("tile_grid_%s" % dev_name, "TileType")
for t in tilegrid: for t in tilegrid:
bba.u32(tiletypes[t], "tiletype") bba.u32(tiletypes[t], "tiletype")
bba.l("package_info_%s" % dev_name, "PackageInfoPOD", export=True) bba.l("package_info_%s" % dev_name, "PackageInfoPOD")
for info in packageinfo: for info in packageinfo:
bba.s(info[0], "name") bba.s(info[0], "name")
bba.u32(info[1], "num_pins") bba.u32(info[1], "num_pins")
bba.r(info[2], "pins") bba.r(info[2], "pins")
bba.l("chip_info_%s" % dev_name)
bba.u32(dev_width, "dev_width")
bba.u32(dev_height, "dev_height")
bba.u32(len(bel_name), "num_bels")
bba.u32(num_wires, "num_wires")
bba.u32(len(pipinfo), "num_pips")
bba.u32(len(switchinfo), "num_switches")
bba.u32(len(packageinfo), "num_packages")
bba.r("bel_data_%s" % dev_name, "bel_data")
bba.r("wire_data_%s" % dev_name, "wire_data")
bba.r("pip_data_%s" % dev_name, "pip_data")
bba.r("tile_grid_%s" % dev_name, "tile_grid")
bba.r("bits_info_%s" % dev_name, "bits_info")
bba.r("package_info_%s" % dev_name, "packages_data")
bba.finalize() bba.finalize()
print('#include "nextpnr.h"')
print('NEXTPNR_NAMESPACE_BEGIN')
if compact_output: if compact_output:
bba.write_compact_c(sys.stdout) bba.write_compact_c(sys.stdout)
else: else:
bba.write_verbose_c(sys.stdout) bba.write_verbose_c(sys.stdout)
print('} // namespace') # print("ChipInfoPOD chip_info_%s = {" % dev_name)
print('NEXTPNR_NAMESPACE_BEGIN') # print(" %d, %d, %d, %d, %d, %d, %d," % (dev_width, dev_height, len(bel_name), num_wires, len(pipinfo), len(switchinfo), len(packageinfo)))
# print(" bel_data, wire_data_%s, pip_data_%s," % (dev_name, dev_name))
print("ChipInfoPOD chip_info_%s = {" % dev_name) # print(" tile_grid_%s, bits_info_%s, package_info_%s" % (dev_name, dev_name, dev_name))
print(" %d, %d, %d, %d, %d, %d, %d," % (dev_width, dev_height, len(bel_name), num_wires, len(pipinfo), len(switchinfo), len(packageinfo))) # print("};")
print(" bel_data, wire_data_%s, pip_data_%s," % (dev_name, dev_name))
print(" tile_grid_%s, bits_info_%s, package_info_%s" % (dev_name, dev_name, dev_name))
print("};")
print('NEXTPNR_NAMESPACE_END') print('NEXTPNR_NAMESPACE_END')