Move top-level ChipInfoPOD into ice40 chipdb blob
Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf
parent
6f4af8387e
commit
19b665177e
@ -24,7 +24,7 @@ NEXTPNR_NAMESPACE_BEGIN
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inline TileType tile_at(const Chip &chip, int x, int y)
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{
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return chip.chip_info.tile_grid[y * chip.chip_info.width + x];
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return chip.chip_info->tile_grid[y * chip.chip_info->width + x];
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}
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const ConfigEntryPOD &find_config(const TileInfoPOD &tile,
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@ -93,7 +93,7 @@ void write_asc(const Design &design, std::ostream &out)
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{
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const Chip &chip = design.chip;
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// [y][x][row][col]
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const ChipInfoPOD &ci = chip.chip_info;
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const ChipInfoPOD &ci = *chip.chip_info;
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const BitstreamInfoPOD &bi = *ci.bits_info;
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std::vector<std::vector<std::vector<std::vector<int8_t>>>> config;
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config.resize(ci.height);
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128
ice40/chip.cc
128
ice40/chip.cc
@ -82,38 +82,38 @@ Chip::Chip(ChipArgs args) : args(args)
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{
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#ifdef ICE40_HX1K_ONLY
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if (args.type == ChipArgs::HX1K) {
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chip_info = chip_info_1k;
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chip_info = reinterpret_cast<RelPtr<ChipInfoPOD>*>(chipdb_blob_1k)->get();
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} else {
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log_error("Unsupported iCE40 chip type.\n");
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}
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#else
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if (args.type == ChipArgs::LP384) {
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chip_info = chip_info_384;
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chip_info = reinterpret_cast<RelPtr<ChipInfoPOD>*>(chipdb_blob_384)->get();
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} else if (args.type == ChipArgs::LP1K || args.type == ChipArgs::HX1K) {
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chip_info = chip_info_1k;
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chip_info = reinterpret_cast<RelPtr<ChipInfoPOD>*>(chipdb_blob_1k)->get();
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} else if (args.type == ChipArgs::UP5K) {
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chip_info = chip_info_5k;
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chip_info = reinterpret_cast<RelPtr<ChipInfoPOD>*>(chipdb_blob_5k)->get();
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} else if (args.type == ChipArgs::LP8K || args.type == ChipArgs::HX8K) {
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chip_info = chip_info_8k;
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chip_info = reinterpret_cast<RelPtr<ChipInfoPOD>*>(chipdb_blob_8k)->get();
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} else {
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log_error("Unsupported iCE40 chip type.\n");
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}
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#endif
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package_info = nullptr;
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for (int i = 0; i < chip_info.num_packages; i++) {
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if (chip_info.packages_data[i].name.get() == args.package) {
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package_info = &(chip_info.packages_data[i]);
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for (int i = 0; i < chip_info->num_packages; i++) {
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if (chip_info->packages_data[i].name.get() == args.package) {
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package_info = &(chip_info->packages_data[i]);
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break;
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}
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}
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if (package_info == nullptr)
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log_error("Unsupported package '%s'.\n", args.package.c_str());
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bel_to_cell.resize(chip_info.num_bels);
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wire_to_net.resize(chip_info.num_wires);
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pip_to_net.resize(chip_info.num_pips);
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switches_locked.resize(chip_info.num_switches);
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bel_to_cell.resize(chip_info->num_bels);
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wire_to_net.resize(chip_info->num_wires);
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pip_to_net.resize(chip_info->num_pips);
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switches_locked.resize(chip_info->num_switches);
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}
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// -----------------------------------------------------------------------
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@ -152,8 +152,8 @@ BelId Chip::getBelByName(IdString name) const
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BelId ret;
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if (bel_by_name.empty()) {
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for (int i = 0; i < chip_info.num_bels; i++)
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bel_by_name[chip_info.bel_data[i].name.get()] = i;
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for (int i = 0; i < chip_info->num_bels; i++)
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bel_by_name[chip_info->bel_data[i].name.get()] = i;
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}
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auto it = bel_by_name.find(name);
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@ -168,16 +168,16 @@ BelRange Chip::getBelsAtSameTile(BelId bel) const
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BelRange br;
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assert(bel != BelId());
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// This requires Bels at the same tile are consecutive
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int x = chip_info.bel_data[bel.index].x;
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int y = chip_info.bel_data[bel.index].y;
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int x = chip_info->bel_data[bel.index].x;
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int y = chip_info->bel_data[bel.index].y;
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int start = bel.index, end = bel.index;
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while (start >= 0 && chip_info.bel_data[start].x == x &&
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chip_info.bel_data[start].y == y)
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while (start >= 0 && chip_info->bel_data[start].x == x &&
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chip_info->bel_data[start].y == y)
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start--;
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start++;
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br.b.cursor = start;
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while (end < chip_info.num_bels && chip_info.bel_data[end].x == x &&
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chip_info.bel_data[end].y == y)
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while (end < chip_info->num_bels && chip_info->bel_data[end].x == x &&
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chip_info->bel_data[end].y == y)
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end++;
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br.e.cursor = end;
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return br;
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@ -189,8 +189,8 @@ WireId Chip::getWireBelPin(BelId bel, PortPin pin) const
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assert(bel != BelId());
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int num_bel_wires = chip_info.bel_data[bel.index].num_bel_wires;
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const BelWirePOD *bel_wires = chip_info.bel_data[bel.index].bel_wires.get();
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int num_bel_wires = chip_info->bel_data[bel.index].num_bel_wires;
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const BelWirePOD *bel_wires = chip_info->bel_data[bel.index].bel_wires.get();
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for (int i = 0; i < num_bel_wires; i++)
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if (bel_wires[i].port == pin) {
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@ -208,8 +208,8 @@ WireId Chip::getWireByName(IdString name) const
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WireId ret;
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if (wire_by_name.empty()) {
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for (int i = 0; i < chip_info.num_wires; i++)
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wire_by_name[chip_info.wire_data[i].name.get()] = i;
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for (int i = 0; i < chip_info->num_wires; i++)
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wire_by_name[chip_info->wire_data[i].name.get()] = i;
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}
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auto it = wire_by_name.find(name);
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@ -226,7 +226,7 @@ PipId Chip::getPipByName(IdString name) const
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PipId ret;
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if (pip_by_name.empty()) {
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for (int i = 0; i < chip_info.num_pips; i++) {
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for (int i = 0; i < chip_info->num_pips; i++) {
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PipId pip;
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pip.index = i;
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pip_by_name[getPipName(pip)] = i;
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@ -244,15 +244,15 @@ IdString Chip::getPipName(PipId pip) const
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{
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assert(pip != PipId());
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int x = chip_info.pip_data[pip.index].x;
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int y = chip_info.pip_data[pip.index].y;
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int x = chip_info->pip_data[pip.index].x;
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int y = chip_info->pip_data[pip.index].y;
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std::string src_name =
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chip_info.wire_data[chip_info.pip_data[pip.index].src].name.get();
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chip_info->wire_data[chip_info->pip_data[pip.index].src].name.get();
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std::replace(src_name.begin(), src_name.end(), '/', '.');
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std::string dst_name =
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chip_info.wire_data[chip_info.pip_data[pip.index].dst].name.get();
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chip_info->wire_data[chip_info->pip_data[pip.index].dst].name.get();
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std::replace(dst_name.begin(), dst_name.end(), '/', '.');
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return "X" + std::to_string(x) + "/Y" + std::to_string(y) + "/" + src_name +
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@ -287,21 +287,21 @@ std::string Chip::getBelPackagePin(BelId bel) const
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bool Chip::estimatePosition(BelId bel, int &x, int &y) const
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{
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assert(bel != BelId());
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x = chip_info.bel_data[bel.index].x;
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y = chip_info.bel_data[bel.index].y;
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x = chip_info->bel_data[bel.index].x;
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y = chip_info->bel_data[bel.index].y;
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return chip_info.bel_data[bel.index].type != TYPE_SB_GB;
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return chip_info->bel_data[bel.index].type != TYPE_SB_GB;
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}
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delay_t Chip::estimateDelay(WireId src, WireId dst) const
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{
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assert(src != WireId());
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delay_t x1 = chip_info.wire_data[src.index].x;
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delay_t y1 = chip_info.wire_data[src.index].y;
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delay_t x1 = chip_info->wire_data[src.index].x;
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delay_t y1 = chip_info->wire_data[src.index].y;
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assert(dst != WireId());
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delay_t x2 = chip_info.wire_data[dst.index].x;
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delay_t y2 = chip_info.wire_data[dst.index].y;
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delay_t x2 = chip_info->wire_data[dst.index].x;
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delay_t y2 = chip_info->wire_data[dst.index].y;
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return fabsf(x1 - x2) + fabsf(y1 - y2);
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}
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@ -312,8 +312,8 @@ std::vector<GraphicElement> Chip::getFrameGraphics() const
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{
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std::vector<GraphicElement> ret;
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for (int x = 0; x <= chip_info.width; x++)
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for (int y = 0; y <= chip_info.height; y++) {
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for (int x = 0; x <= chip_info->width; x++)
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for (int y = 0; y <= chip_info->height; y++) {
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GraphicElement el;
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el.type = GraphicElement::G_LINE;
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el.x1 = x - 0.05, el.x2 = x + 0.05, el.y1 = y, el.y2 = y, el.z = 0;
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@ -334,44 +334,44 @@ std::vector<GraphicElement> Chip::getBelGraphics(BelId bel) const
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if (bel_type == TYPE_ICESTORM_LC) {
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GraphicElement el;
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el.type = GraphicElement::G_BOX;
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el.x1 = chip_info.bel_data[bel.index].x + 0.1;
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el.x2 = chip_info.bel_data[bel.index].x + 0.9;
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el.y1 = chip_info.bel_data[bel.index].y + 0.10 +
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(chip_info.bel_data[bel.index].z) * (0.8 / 8);
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el.y2 = chip_info.bel_data[bel.index].y + 0.18 +
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(chip_info.bel_data[bel.index].z) * (0.8 / 8);
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el.x1 = chip_info->bel_data[bel.index].x + 0.1;
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el.x2 = chip_info->bel_data[bel.index].x + 0.9;
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el.y1 = chip_info->bel_data[bel.index].y + 0.10 +
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(chip_info->bel_data[bel.index].z) * (0.8 / 8);
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el.y2 = chip_info->bel_data[bel.index].y + 0.18 +
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(chip_info->bel_data[bel.index].z) * (0.8 / 8);
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el.z = 0;
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ret.push_back(el);
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}
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if (bel_type == TYPE_SB_IO) {
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if (chip_info.bel_data[bel.index].x == 0 ||
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chip_info.bel_data[bel.index].x == chip_info.width - 1) {
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if (chip_info->bel_data[bel.index].x == 0 ||
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chip_info->bel_data[bel.index].x == chip_info->width - 1) {
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GraphicElement el;
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el.type = GraphicElement::G_BOX;
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el.x1 = chip_info.bel_data[bel.index].x + 0.1;
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el.x2 = chip_info.bel_data[bel.index].x + 0.9;
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if (chip_info.bel_data[bel.index].z == 0) {
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el.y1 = chip_info.bel_data[bel.index].y + 0.10;
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el.y2 = chip_info.bel_data[bel.index].y + 0.45;
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el.x1 = chip_info->bel_data[bel.index].x + 0.1;
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el.x2 = chip_info->bel_data[bel.index].x + 0.9;
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if (chip_info->bel_data[bel.index].z == 0) {
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el.y1 = chip_info->bel_data[bel.index].y + 0.10;
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el.y2 = chip_info->bel_data[bel.index].y + 0.45;
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} else {
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el.y1 = chip_info.bel_data[bel.index].y + 0.55;
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el.y2 = chip_info.bel_data[bel.index].y + 0.90;
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el.y1 = chip_info->bel_data[bel.index].y + 0.55;
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el.y2 = chip_info->bel_data[bel.index].y + 0.90;
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}
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el.z = 0;
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ret.push_back(el);
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} else {
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GraphicElement el;
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el.type = GraphicElement::G_BOX;
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if (chip_info.bel_data[bel.index].z == 0) {
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el.x1 = chip_info.bel_data[bel.index].x + 0.10;
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el.x2 = chip_info.bel_data[bel.index].x + 0.45;
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if (chip_info->bel_data[bel.index].z == 0) {
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el.x1 = chip_info->bel_data[bel.index].x + 0.10;
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el.x2 = chip_info->bel_data[bel.index].x + 0.45;
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} else {
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el.x1 = chip_info.bel_data[bel.index].x + 0.55;
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el.x2 = chip_info.bel_data[bel.index].x + 0.90;
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el.x1 = chip_info->bel_data[bel.index].x + 0.55;
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el.x2 = chip_info->bel_data[bel.index].x + 0.90;
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}
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el.y1 = chip_info.bel_data[bel.index].y + 0.1;
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el.y2 = chip_info.bel_data[bel.index].y + 0.9;
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el.y1 = chip_info->bel_data[bel.index].y + 0.1;
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el.y2 = chip_info->bel_data[bel.index].y + 0.9;
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el.z = 0;
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ret.push_back(el);
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}
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@ -380,10 +380,10 @@ std::vector<GraphicElement> Chip::getBelGraphics(BelId bel) const
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if (bel_type == TYPE_ICESTORM_RAM) {
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GraphicElement el;
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el.type = GraphicElement::G_BOX;
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el.x1 = chip_info.bel_data[bel.index].x + 0.1;
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el.x2 = chip_info.bel_data[bel.index].x + 0.9;
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el.y1 = chip_info.bel_data[bel.index].y + 0.1;
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el.y2 = chip_info.bel_data[bel.index].y + 1.9;
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el.x1 = chip_info->bel_data[bel.index].x + 0.1;
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el.x2 = chip_info->bel_data[bel.index].x + 0.9;
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el.y1 = chip_info->bel_data[bel.index].y + 0.1;
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el.y2 = chip_info->bel_data[bel.index].y + 1.9;
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el.z = 0;
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ret.push_back(el);
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}
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82
ice40/chip.h
82
ice40/chip.h
@ -209,21 +209,21 @@ struct BitstreamInfoPOD
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struct ChipInfoPOD
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{
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int width, height;
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int num_bels, num_wires, num_pips;
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int num_switches, num_packages;
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BelInfoPOD *bel_data;
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WireInfoPOD *wire_data;
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PipInfoPOD *pip_data;
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TileType *tile_grid;
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BitstreamInfoPOD *bits_info;
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PackageInfoPOD *packages_data;
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int32_t width, height;
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int32_t num_bels, num_wires, num_pips;
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int32_t num_switches, num_packages;
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RelPtr<BelInfoPOD> bel_data;
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RelPtr<WireInfoPOD> wire_data;
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RelPtr<PipInfoPOD> pip_data;
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RelPtr<TileType> tile_grid;
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RelPtr<BitstreamInfoPOD> bits_info;
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RelPtr<PackageInfoPOD> packages_data;
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} __attribute__((packed));
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extern ChipInfoPOD chip_info_384;
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extern ChipInfoPOD chip_info_1k;
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extern ChipInfoPOD chip_info_5k;
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extern ChipInfoPOD chip_info_8k;
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extern uint8_t chipdb_blob_384[];
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extern uint8_t chipdb_blob_1k[];
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extern uint8_t chipdb_blob_5k[];
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extern uint8_t chipdb_blob_8k[];
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/************************ End of chipdb section. ************************/
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@ -463,8 +463,8 @@ struct ChipArgs
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struct Chip
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{
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ChipInfoPOD chip_info;
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PackageInfoPOD *package_info;
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const ChipInfoPOD *chip_info;
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const PackageInfoPOD *package_info;
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mutable std::unordered_map<IdString, int> bel_by_name;
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mutable std::unordered_map<IdString, int> wire_by_name;
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@ -486,7 +486,7 @@ struct Chip
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IdString getBelName(BelId bel) const
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{
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assert(bel != BelId());
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return chip_info.bel_data[bel.index].name.get();
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return chip_info->bel_data[bel.index].name.get();
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}
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void bindBel(BelId bel, IdString cell)
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@ -519,7 +519,7 @@ struct Chip
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{
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BelRange range;
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range.b.cursor = 0;
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range.e.cursor = chip_info.num_bels;
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range.e.cursor = chip_info->num_bels;
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return range;
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}
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@ -542,7 +542,7 @@ struct Chip
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BelType getBelType(BelId bel) const
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{
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assert(bel != BelId());
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return chip_info.bel_data[bel.index].type;
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return chip_info->bel_data[bel.index].type;
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}
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WireId getWireBelPin(BelId bel, PortPin pin) const;
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@ -552,10 +552,10 @@ struct Chip
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BelPin ret;
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assert(wire != WireId());
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if (chip_info.wire_data[wire.index].bel_uphill.bel_index >= 0) {
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if (chip_info->wire_data[wire.index].bel_uphill.bel_index >= 0) {
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ret.bel.index =
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chip_info.wire_data[wire.index].bel_uphill.bel_index;
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ret.pin = chip_info.wire_data[wire.index].bel_uphill.port;
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chip_info->wire_data[wire.index].bel_uphill.bel_index;
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ret.pin = chip_info->wire_data[wire.index].bel_uphill.port;
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}
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return ret;
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@ -565,9 +565,9 @@ struct Chip
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{
|
||||
BelPinRange range;
|
||||
assert(wire != WireId());
|
||||
range.b.ptr = chip_info.wire_data[wire.index].bels_downhill.get();
|
||||
range.b.ptr = chip_info->wire_data[wire.index].bels_downhill.get();
|
||||
range.e.ptr =
|
||||
range.b.ptr + chip_info.wire_data[wire.index].num_bels_downhill;
|
||||
range.b.ptr + chip_info->wire_data[wire.index].num_bels_downhill;
|
||||
return range;
|
||||
}
|
||||
|
||||
@ -578,7 +578,7 @@ struct Chip
|
||||
IdString getWireName(WireId wire) const
|
||||
{
|
||||
assert(wire != WireId());
|
||||
return chip_info.wire_data[wire.index].name.get();
|
||||
return chip_info->wire_data[wire.index].name.get();
|
||||
}
|
||||
|
||||
void bindWire(WireId wire, IdString net)
|
||||
@ -611,7 +611,7 @@ struct Chip
|
||||
{
|
||||
WireRange range;
|
||||
range.b.cursor = 0;
|
||||
range.e.cursor = chip_info.num_wires;
|
||||
range.e.cursor = chip_info->num_wires;
|
||||
return range;
|
||||
}
|
||||
|
||||
@ -624,20 +624,20 @@ struct Chip
|
||||
{
|
||||
assert(pip != PipId());
|
||||
assert(pip_to_net[pip.index] == IdString());
|
||||
assert(switches_locked[chip_info.pip_data[pip.index].switch_index] ==
|
||||
assert(switches_locked[chip_info->pip_data[pip.index].switch_index] ==
|
||||
IdString());
|
||||
pip_to_net[pip.index] = net;
|
||||
switches_locked[chip_info.pip_data[pip.index].switch_index] = net;
|
||||
switches_locked[chip_info->pip_data[pip.index].switch_index] = net;
|
||||
}
|
||||
|
||||
void unbindPip(PipId pip)
|
||||
{
|
||||
assert(pip != PipId());
|
||||
assert(pip_to_net[pip.index] != IdString());
|
||||
assert(switches_locked[chip_info.pip_data[pip.index].switch_index] !=
|
||||
assert(switches_locked[chip_info->pip_data[pip.index].switch_index] !=
|
||||
IdString());
|
||||
pip_to_net[pip.index] = IdString();
|
||||
switches_locked[chip_info.pip_data[pip.index].switch_index] =
|
||||
switches_locked[chip_info->pip_data[pip.index].switch_index] =
|
||||
IdString();
|
||||
}
|
||||
|
||||
@ -645,11 +645,11 @@ struct Chip
|
||||
{
|
||||
assert(pip != PipId());
|
||||
if (args.type == ChipArgs::UP5K) {
|
||||
int x = chip_info.pip_data[pip.index].x;
|
||||
if (x == 0 || x == (chip_info.width - 1))
|
||||
int x = chip_info->pip_data[pip.index].x;
|
||||
if (x == 0 || x == (chip_info->width - 1))
|
||||
return false;
|
||||
}
|
||||
return switches_locked[chip_info.pip_data[pip.index].switch_index] ==
|
||||
return switches_locked[chip_info->pip_data[pip.index].switch_index] ==
|
||||
IdString();
|
||||
}
|
||||
|
||||
@ -657,7 +657,7 @@ struct Chip
|
||||
{
|
||||
assert(pip != PipId());
|
||||
if (conflicting)
|
||||
return switches_locked[chip_info.pip_data[pip.index].switch_index];
|
||||
return switches_locked[chip_info->pip_data[pip.index].switch_index];
|
||||
return pip_to_net[pip.index];
|
||||
}
|
||||
|
||||
@ -665,7 +665,7 @@ struct Chip
|
||||
{
|
||||
AllPipRange range;
|
||||
range.b.cursor = 0;
|
||||
range.e.cursor = chip_info.num_pips;
|
||||
range.e.cursor = chip_info->num_pips;
|
||||
return range;
|
||||
}
|
||||
|
||||
@ -673,7 +673,7 @@ struct Chip
|
||||
{
|
||||
WireId wire;
|
||||
assert(pip != PipId());
|
||||
wire.index = chip_info.pip_data[pip.index].src;
|
||||
wire.index = chip_info->pip_data[pip.index].src;
|
||||
return wire;
|
||||
}
|
||||
|
||||
@ -681,7 +681,7 @@ struct Chip
|
||||
{
|
||||
WireId wire;
|
||||
assert(pip != PipId());
|
||||
wire.index = chip_info.pip_data[pip.index].dst;
|
||||
wire.index = chip_info->pip_data[pip.index].dst;
|
||||
return wire;
|
||||
}
|
||||
|
||||
@ -689,7 +689,7 @@ struct Chip
|
||||
{
|
||||
DelayInfo delay;
|
||||
assert(pip != PipId());
|
||||
delay.delay = chip_info.pip_data[pip.index].delay;
|
||||
delay.delay = chip_info->pip_data[pip.index].delay;
|
||||
return delay;
|
||||
}
|
||||
|
||||
@ -697,9 +697,9 @@ struct Chip
|
||||
{
|
||||
PipRange range;
|
||||
assert(wire != WireId());
|
||||
range.b.cursor = chip_info.wire_data[wire.index].pips_downhill.get();
|
||||
range.b.cursor = chip_info->wire_data[wire.index].pips_downhill.get();
|
||||
range.e.cursor =
|
||||
range.b.cursor + chip_info.wire_data[wire.index].num_downhill;
|
||||
range.b.cursor + chip_info->wire_data[wire.index].num_downhill;
|
||||
return range;
|
||||
}
|
||||
|
||||
@ -707,9 +707,9 @@ struct Chip
|
||||
{
|
||||
PipRange range;
|
||||
assert(wire != WireId());
|
||||
range.b.cursor = chip_info.wire_data[wire.index].pips_uphill.get();
|
||||
range.b.cursor = chip_info->wire_data[wire.index].pips_uphill.get();
|
||||
range.e.cursor =
|
||||
range.b.cursor + chip_info.wire_data[wire.index].num_uphill;
|
||||
range.b.cursor + chip_info->wire_data[wire.index].num_uphill;
|
||||
return range;
|
||||
}
|
||||
|
||||
|
||||
@ -549,11 +549,8 @@ class BinaryBlobAssembler:
|
||||
print("#define %s ((%s*)(%s+%d))" % (self.labels_byaddr[cursor], self.ltypes_byaddr[cursor], self.cname, cursor), file=f)
|
||||
print("};", file=f)
|
||||
|
||||
bba = BinaryBlobAssembler("binblob_%s" % dev_name, endianness, "static uint8_t")
|
||||
|
||||
print('#include "nextpnr.h"')
|
||||
print('namespace {')
|
||||
print('USING_NEXTPNR_NAMESPACE')
|
||||
bba = BinaryBlobAssembler("chipdb_blob_%s" % dev_name, endianness, "uint8_t")
|
||||
bba.r("chip_info_%s" % dev_name, "chip_info")
|
||||
|
||||
index = 0
|
||||
for bel in range(len(bel_name)):
|
||||
@ -563,7 +560,7 @@ for bel in range(len(bel_name)):
|
||||
bba.u32(portpins[bel_wires[bel][i][1]], "port")
|
||||
index += 1
|
||||
|
||||
bba.l("bel_data", "BelInfoPOD", export=True)
|
||||
bba.l("bel_data_%s" % dev_name, "BelInfoPOD")
|
||||
for bel in range(len(bel_name)):
|
||||
bba.s(bel_name[bel], "name")
|
||||
bba.u32(beltypes[bel_type[bel]], "type")
|
||||
@ -722,7 +719,7 @@ for t in range(num_tile_types):
|
||||
ti["entries"] = "tile%d_config" % t
|
||||
tileinfo.append(ti)
|
||||
|
||||
bba.l("wire_data_%s" % dev_name, "WireInfoPOD", export=True)
|
||||
bba.l("wire_data_%s" % dev_name, "WireInfoPOD")
|
||||
for info in wireinfo:
|
||||
bba.s(info["name"], "name")
|
||||
bba.u32(info["num_uphill"], "num_uphill")
|
||||
@ -736,7 +733,7 @@ for info in wireinfo:
|
||||
bba.u16(info["x"], "x")
|
||||
bba.u16(info["y"], "y")
|
||||
|
||||
bba.l("pip_data_%s" % dev_name, "PipInfoPOD", export=True)
|
||||
bba.l("pip_data_%s" % dev_name, "PipInfoPOD")
|
||||
for info in pipinfo:
|
||||
bba.u32(info["src"], "src")
|
||||
bba.u32(info["dst"], "dst")
|
||||
@ -792,36 +789,52 @@ for ieren in ierens:
|
||||
if len(ierens) % 2 == 1:
|
||||
bba.u16(0, "padding")
|
||||
|
||||
bba.l("bits_info_%s" % dev_name, "BitstreamInfoPOD", export=True)
|
||||
bba.l("bits_info_%s" % dev_name, "BitstreamInfoPOD")
|
||||
bba.u32(len(switchinfo), "num_switches")
|
||||
bba.u32(len(ierens), "num_ierens")
|
||||
bba.r("tile_data_%s" % dev_name, "tiles_nonrouting")
|
||||
bba.r("switch_data_%s" % dev_name, "switches")
|
||||
bba.r("ieren_data_%s" % dev_name, "ierens")
|
||||
|
||||
bba.l("tile_grid_%s" % dev_name, "TileType", export=True)
|
||||
bba.l("tile_grid_%s" % dev_name, "TileType")
|
||||
for t in tilegrid:
|
||||
bba.u32(tiletypes[t], "tiletype")
|
||||
|
||||
bba.l("package_info_%s" % dev_name, "PackageInfoPOD", export=True)
|
||||
bba.l("package_info_%s" % dev_name, "PackageInfoPOD")
|
||||
for info in packageinfo:
|
||||
bba.s(info[0], "name")
|
||||
bba.u32(info[1], "num_pins")
|
||||
bba.r(info[2], "pins")
|
||||
|
||||
bba.l("chip_info_%s" % dev_name)
|
||||
bba.u32(dev_width, "dev_width")
|
||||
bba.u32(dev_height, "dev_height")
|
||||
bba.u32(len(bel_name), "num_bels")
|
||||
bba.u32(num_wires, "num_wires")
|
||||
bba.u32(len(pipinfo), "num_pips")
|
||||
bba.u32(len(switchinfo), "num_switches")
|
||||
bba.u32(len(packageinfo), "num_packages")
|
||||
bba.r("bel_data_%s" % dev_name, "bel_data")
|
||||
bba.r("wire_data_%s" % dev_name, "wire_data")
|
||||
bba.r("pip_data_%s" % dev_name, "pip_data")
|
||||
bba.r("tile_grid_%s" % dev_name, "tile_grid")
|
||||
bba.r("bits_info_%s" % dev_name, "bits_info")
|
||||
bba.r("package_info_%s" % dev_name, "packages_data")
|
||||
|
||||
bba.finalize()
|
||||
|
||||
print('#include "nextpnr.h"')
|
||||
print('NEXTPNR_NAMESPACE_BEGIN')
|
||||
|
||||
if compact_output:
|
||||
bba.write_compact_c(sys.stdout)
|
||||
else:
|
||||
bba.write_verbose_c(sys.stdout)
|
||||
|
||||
print('} // namespace')
|
||||
print('NEXTPNR_NAMESPACE_BEGIN')
|
||||
|
||||
print("ChipInfoPOD chip_info_%s = {" % dev_name)
|
||||
print(" %d, %d, %d, %d, %d, %d, %d," % (dev_width, dev_height, len(bel_name), num_wires, len(pipinfo), len(switchinfo), len(packageinfo)))
|
||||
print(" bel_data, wire_data_%s, pip_data_%s," % (dev_name, dev_name))
|
||||
print(" tile_grid_%s, bits_info_%s, package_info_%s" % (dev_name, dev_name, dev_name))
|
||||
print("};")
|
||||
# print("ChipInfoPOD chip_info_%s = {" % dev_name)
|
||||
# print(" %d, %d, %d, %d, %d, %d, %d," % (dev_width, dev_height, len(bel_name), num_wires, len(pipinfo), len(switchinfo), len(packageinfo)))
|
||||
# print(" bel_data, wire_data_%s, pip_data_%s," % (dev_name, dev_name))
|
||||
# print(" tile_grid_%s, bits_info_%s, package_info_%s" % (dev_name, dev_name, dev_name))
|
||||
# print("};")
|
||||
|
||||
print('NEXTPNR_NAMESPACE_END')
|
||||
|
||||
Loading…
Reference in New Issue
Block a user