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ecp5: Dummy timing entry for BRAM

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Signed-off-by: David Shah <dave@ds0.me>
This commit is contained in:
David Shah 2018-10-05 11:35:37 +01:00
parent 48f08e6d39
commit 19f828c91c
1 changed files with 3 additions and 0 deletions
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3
ecp5/arch.cc
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@ -582,6 +582,9 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, Id
if (port == id_CLKO) if (port == id_CLKO)
return TMG_COMB_OUTPUT; return TMG_COMB_OUTPUT;
return TMG_IGNORE; return TMG_IGNORE;
} else if (cell->type == id_DP16KD) {
// FIXME
return TMG_IGNORE;
} else { } else {
NPNR_ASSERT_FALSE_STR("no timing data for cell type '" + cell->type.str(this) + "'"); NPNR_ASSERT_FALSE_STR("no timing data for cell type '" + cell->type.str(this) + "'");
} }