From 1a3d0f2f5dd763e08a237d53e92d775704f46f01 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 13 Jun 2018 17:38:34 +0200 Subject: [PATCH] Add picorv32_top module with fewer IO pins Signed-off-by: Clifford Wolf --- ice40/picorv32.sh | 2 +- ice40/picorv32_top.v | 31 +++++++++++++++++++++++++++++++ 2 files changed, 32 insertions(+), 1 deletion(-) create mode 100644 ice40/picorv32_top.v diff --git a/ice40/picorv32.sh b/ice40/picorv32.sh index 9d171e76..2c67f641 100755 --- a/ice40/picorv32.sh +++ b/ice40/picorv32.sh @@ -2,5 +2,5 @@ set -ex rm -f picorv32.v wget https://raw.githubusercontent.com/cliffordwolf/picorv32/master/picorv32.v -yosys -p 'synth_ice40 -nocarry -json picorv32.json -top picorv32' picorv32.v +yosys -p 'synth_ice40 -nocarry -json picorv32.json -top top' picorv32.v picorv32_top.v ../nextpnr-ice40 --hx8k --asc picorv32.asc --json picorv32.json diff --git a/ice40/picorv32_top.v b/ice40/picorv32_top.v new file mode 100644 index 00000000..27f0ef0c --- /dev/null +++ b/ice40/picorv32_top.v @@ -0,0 +1,31 @@ +module top ( + input clk, resetn, + output trap, + + output mem_valid, + output mem_instr, + input mem_ready, + + output [31:0] mem_addr, + output [31:0] mem_wdata, + output [ 3:0] mem_wstrb, + input [31:0] mem_rdata +); + picorv32 #( + .ENABLE_COUNTERS(0), + .TWO_STAGE_SHIFT(0), + .CATCH_MISALIGN(0), + .CATCH_ILLINSN(0) + ) cpu ( + .clk (clk ), + .resetn (resetn ), + .trap (trap ), + .mem_valid(mem_valid), + .mem_instr(mem_instr), + .mem_ready(mem_ready), + .mem_addr (mem_addr ), + .mem_wdata(mem_wdata), + .mem_wstrb(mem_wstrb), + .mem_rdata(mem_rdata) + ); +endmodule