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ecp5: clangformat timing changes

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Signed-off-by: David Shah <dave@ds0.me>
This commit is contained in:
David Shah 2018-11-16 13:27:03 +00:00
parent 50b85da619
commit 1ae722272a
4 changed files with 18 additions and 19 deletions
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2
common/timing.cc
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@ -659,7 +659,6 @@ void timing_analysis(Context *ctx, bool print_histogram, bool print_fmax, bool p
} }
} }
last_port = sink->port; last_port = sink->port;
} }
int clockCount = 0; int clockCount = 0;
auto sinkClass = ctx->getPortTimingClass(crit_path.back()->cell, crit_path.back()->port, clockCount); auto sinkClass = ctx->getPortTimingClass(crit_path.back()->cell, crit_path.back()->port, clockCount);
@ -670,7 +669,6 @@ void timing_analysis(Context *ctx, bool print_histogram, bool print_fmax, bool p
log_info("%4.1f %4.1f Setup %s.%s\n", ctx->getDelayNS(setup), ctx->getDelayNS(total), log_info("%4.1f %4.1f Setup %s.%s\n", ctx->getDelayNS(setup), ctx->getDelayNS(total),
crit_path.back()->cell->name.c_str(ctx), crit_path.back()->port.c_str(ctx)); crit_path.back()->cell->name.c_str(ctx), crit_path.back()->port.c_str(ctx));
} }
}; };
for (auto &clock : clock_reports) { for (auto &clock : clock_reports) {

2
ecp5/arch.cc
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@ -740,7 +740,7 @@ TimingClockingInfo Arch::getPortClockingInfo(const CellInfo *cell, IdString port
info.clockToQ = getDelayFromNS(0.7); info.clockToQ = getDelayFromNS(0.7);
} else { } else {
info.setup = getDelayFromNS(1); info.setup = getDelayFromNS(1);
info.hold = getDelayFromNS(0); info.hold = getDelayFromNS(0);
} }
} }
return info; return info;

10
ecp5/arch.h
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@ -828,10 +828,12 @@ struct Arch : BaseCtx
if (fnd_fanout != wire_fanout.end()) if (fnd_fanout != wire_fanout.end())
fanout = fnd_fanout->second; fanout = fnd_fanout->second;
NPNR_ASSERT(locInfo(pip)->pip_data[pip.index].timing_class < speed_grade->num_pip_classes); NPNR_ASSERT(locInfo(pip)->pip_data[pip.index].timing_class < speed_grade->num_pip_classes);
delay.min_delay = speed_grade->pip_classes[locInfo(pip)->pip_data[pip.index].timing_class].min_base_delay delay.min_delay =
+ fanout * speed_grade->pip_classes[locInfo(pip)->pip_data[pip.index].timing_class].min_fanout_adder; speed_grade->pip_classes[locInfo(pip)->pip_data[pip.index].timing_class].min_base_delay +
delay.max_delay = speed_grade->pip_classes[locInfo(pip)->pip_data[pip.index].timing_class].max_base_delay fanout * speed_grade->pip_classes[locInfo(pip)->pip_data[pip.index].timing_class].min_fanout_adder;
+ fanout * speed_grade->pip_classes[locInfo(pip)->pip_data[pip.index].timing_class].max_fanout_adder; delay.max_delay =
speed_grade->pip_classes[locInfo(pip)->pip_data[pip.index].timing_class].max_base_delay +
fanout * speed_grade->pip_classes[locInfo(pip)->pip_data[pip.index].timing_class].max_fanout_adder;
return delay; return delay;
} }

23
ecp5/main.cc
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@ -122,24 +122,23 @@ std::unique_ptr<Context> ECP5CommandHandler::createContext()
if (vm.count("speed")) { if (vm.count("speed")) {
int speed = vm["speed"].as<int>(); int speed = vm["speed"].as<int>();
switch (speed) { switch (speed) {
case 6: case 6:
chipArgs.speed = ArchArgs::SPEED_6; chipArgs.speed = ArchArgs::SPEED_6;
break; break;
case 7: case 7:
chipArgs.speed = ArchArgs::SPEED_7; chipArgs.speed = ArchArgs::SPEED_7;
break; break;
case 8: case 8:
chipArgs.speed = ArchArgs::SPEED_8; chipArgs.speed = ArchArgs::SPEED_8;
break; break;
default: default:
log_error("Unsupported speed grade '%d'\n", speed); log_error("Unsupported speed grade '%d'\n", speed);
} }
} else { } else {
chipArgs.speed = ArchArgs::SPEED_6; chipArgs.speed = ArchArgs::SPEED_6;
} }
} }
return std::unique_ptr<Context>(new Context(chipArgs)); return std::unique_ptr<Context>(new Context(chipArgs));
} }