From 1b077320dc63b4dc1ecd1e9310dc80d89492d113 Mon Sep 17 00:00:00 2001 From: David Shah Date: Sun, 17 Jun 2018 12:53:39 +0200 Subject: [PATCH] General reformatting Signed-off-by: David Shah --- common/design_utils.h | 1 - ice40/bitstream.cc | 2 +- ice40/cells.h | 2 +- ice40/main.cc | 2 +- 4 files changed, 3 insertions(+), 4 deletions(-) diff --git a/common/design_utils.h b/common/design_utils.h index b63c75c3..d640bf68 100644 --- a/common/design_utils.h +++ b/common/design_utils.h @@ -86,7 +86,6 @@ CellInfo *net_driven_by(const NetInfo *net, F1 cell_pred, IdString port) void print_utilisation(const Design *design); - NEXTPNR_NAMESPACE_END #endif diff --git a/ice40/bitstream.cc b/ice40/bitstream.cc index 918eb01b..9309a7da 100644 --- a/ice40/bitstream.cc +++ b/ice40/bitstream.cc @@ -398,7 +398,7 @@ void write_asc(const Design &design, std::ostream &out) for (auto wire : chip.getWires()) { IdString net = chip.getWireNet(wire, false); if (net != IdString()) - out << ".sym " << wire.index << " net_" << net << std::endl; + out << ".sym " << wire.index << " " << net << std::endl; } } diff --git a/ice40/cells.h b/ice40/cells.h index 82d9f60e..45e81fd1 100644 --- a/ice40/cells.h +++ b/ice40/cells.h @@ -3,7 +3,7 @@ * * Copyright (C) 2018 Clifford Wolf * Copyright (C) 2018 David Shah - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. diff --git a/ice40/main.cc b/ice40/main.cc index 3cd97f48..eb92d92f 100644 --- a/ice40/main.cc +++ b/ice40/main.cc @@ -25,6 +25,7 @@ #include #include #include "bitstream.h" +#include "design_utils.h" #include "jsonparse.h" #include "log.h" #include "mainwindow.h" @@ -35,7 +36,6 @@ #include "pybindings.h" #include "route.h" #include "version.h" -#include "design_utils.h" void svg_dump_el(const GraphicElement &el) {