From 1b3283fb7cff0e08ddfa12d939b9a4cedf2156b5 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Mon, 10 Apr 2023 10:18:18 +0200
Subject: [PATCH] Add constants for new bels

---
 machxo2/constids.inc | 200 ++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 198 insertions(+), 2 deletions(-)

diff --git a/machxo2/constids.inc b/machxo2/constids.inc
index 0debca18..6d763a58 100644
--- a/machxo2/constids.inc
+++ b/machxo2/constids.inc
@@ -102,7 +102,6 @@ X(IOLTO)
 
 
 X(OSCH)
-X(STDBY)
 X(OSC)
 X(SEDSTDBY)
 
@@ -162,4 +161,201 @@ X(COUT)
 X(E)
 X(Y)
 
-X(WCKMUX)
\ No newline at end of file
+X(WCKMUX)
+
+X(EHXPLLJ)
+X(CLKFB)
+X(PHASESEL1)
+X(PHASESEL0)
+X(PHASEDIR)
+X(PHASESTEP)
+X(LOADREG)
+X(STDBY)
+X(PLLWAKESYNC)
+X(RST)
+X(ENCLKOP)
+X(ENCLKOS)
+X(ENCLKOS2)
+X(ENCLKOS3)
+X(CLKOP)
+X(CLKOS)
+X(CLKOS2)
+X(CLKOS3)
+X(LOCK)
+X(INTLOCK)
+X(REFCLK)
+X(CLKINTFB)
+
+X(DP8KC)
+X(DIA0)
+X(DIA1)
+X(DIA2)
+X(DIA3)
+X(DIA4)
+X(DIA5)
+X(DIA6)
+X(DIA7)
+X(DIA8)
+X(ADA0)
+X(ADA1)
+X(ADA2)
+X(ADA3)
+X(ADA4)
+X(ADA5)
+X(ADA6)
+X(ADA7)
+X(ADA8)
+X(ADA9)
+X(ADA10)
+X(ADA11)
+X(ADA12)
+X(OCEA)
+X(CLKA)
+X(WEA)
+X(CSA2)
+X(CSA1)
+X(CSA0)
+X(RSTA)
+X(DIB0)
+X(DIB1)
+X(DIB2)
+X(DIB3)
+X(DIB4)
+X(DIB5)
+X(DIB6)
+X(DIB7)
+X(DIB8)
+X(ADB0)
+X(ADB1)
+X(ADB2)
+X(ADB3)
+X(ADB4)
+X(ADB5)
+X(ADB6)
+X(ADB7)
+X(ADB8)
+X(ADB9)
+X(ADB10)
+X(ADB11)
+X(ADB12)
+X(CEB)
+X(OCEB)
+X(CLKB)
+X(WEB)
+X(CSB2)
+X(CSB1)
+X(CSB0)
+X(RSTB)
+X(DOA0)
+X(DOA1)
+X(DOA2)
+X(DOA3)
+X(DOA4)
+X(DOA5)
+X(DOA6)
+X(DOA7)
+X(DOA8)
+X(DOB0)
+X(DOB1)
+X(DOB2)
+X(DOB3)
+X(DOB4)
+X(DOB5)
+X(DOB6)
+X(DOB7)
+X(DOB8)
+X(AE)
+X(AF)
+X(EF)
+X(FF)
+X(WID)
+
+
+X(CLKI_DIV)
+X(CLKFB_DIV)
+X(CLKOP_DIV)
+X(CLKOS_DIV)
+X(CLKOS2_DIV)
+X(CLKOS3_DIV)
+X(CLOCK_ENABLE_PORTS)
+X(CLKOP_ENABLE)
+X(CLKOS_ENABLE)
+X(CLKOS2_ENABLE)
+X(CLKOS3_ENABLE)
+X(VCO_BYPASS_A0)
+X(VCO_BYPASS_B0)
+X(VCO_BYPASS_C0)
+X(VCO_BYPASS_D0)
+X(CLKOP_CPHASE)
+X(CLKOS_CPHASE)
+X(CLKOS2_CPHASE)
+X(CLKOS3_CPHASE)
+X(CLKOP_FPHASE)
+X(CLKOS_FPHASE)
+X(CLKOS2_FPHASE)
+X(CLKOS3_FPHASE)
+X(FEEDBK_PATH)
+X(KVCO)
+X(LPF_CAPACITOR)
+X(LPF_RESISTOR)
+X(ICP_CURRENT)
+X(FRACN_ENABLE)
+X(FRACN_DIV)
+X(FRACN_ORDER)
+X(CLKOP_TRIM_POL)
+X(CLKOP_TRIM_DELAY)
+X(CLKOS_TRIM_POL)
+X(CLKOS_TRIM_DELAY)
+X(PLL_EXPERT)
+X(PLL_USE_WB)
+X(PREDIVIDER_MUXA1)
+X(PREDIVIDER_MUXB1)
+X(PREDIVIDER_MUXC1)
+X(PREDIVIDER_MUXD1)
+X(OUTDIVIDER_MUXA2)
+X(OUTDIVIDER_MUXB2)
+X(OUTDIVIDER_MUXC2)
+X(OUTDIVIDER_MUXD2)
+X(FREQ_LOCK_ACCURACY)
+X(PLL_LOCK_MODE)
+X(PLL_LOCK_DELAY)
+X(GMC_GAIN)
+X(GMC_TEST)
+X(MFG1_TEST)
+X(MFG2_TEST)
+X(MFG_FORCE_VFILTER)
+X(MFG_ICP_TEST)
+X(MFG_EN_UP)
+X(MFG_FLOAT_ICP)
+X(MFG_GMC_PRESET)
+X(MFG_LF_PRESET)
+X(MFG_GMC_RESET)
+X(MFG_LF_RESET)
+X(MFG_LF_RESGRND)
+X(MFG_GMCREF_SEL)
+X(MFG_ENABLE_FILTEROPAMP)
+X(STDBY_ENABLE)
+X(REFIN_RESET)
+X(SYNC_ENABLE)
+X(INT_LOCK_STICKY)
+X(DPHASE_SOURCE)
+X(INTFB_WAKE)
+X(PLLRST_ENA)
+X(MRST_ENA)
+X(DCRST_ENA)
+X(DDRST_ENA)
+
+X(DATA_WIDTH_A)
+X(DATA_WIDTH_B)
+X(WRITEMODE_A)
+X(WRITEMODE_B)
+X(CSDECODE_A)
+X(CSDECODE_B)
+X(REGMODE_A)
+X(REGMODE_B)
+X(RESETMODE)
+X(ASYNC_RESET_RELEASE)
+X(RSTAMUX)
+X(RSTBMUX)
+X(WEAMUX)
+X(WEBMUX)