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Merge pull request #1004 from yrabbit/fix-muxes

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gowin: Remove incomprehensible names of the muxes
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myrtle 2022-07-21 11:34:51 +01:00 committed by GitHub
commit 1b54fa2a1c
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7 changed files with 26 additions and 38 deletions
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15
gowin/arch.cc
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@ -553,7 +553,10 @@ void Arch::setDelayScaling(double scale, double offset)
args.delayOffset = offset; args.delayOffset = offset;
} }
void Arch::addCellTimingClass(IdString cell, IdString port, TimingPortClass cls) {cellTiming[cell].portClasses[port] = cls;} void Arch::addCellTimingClass(IdString cell, IdString port, TimingPortClass cls)
{
cellTiming[cell].portClasses[port] = cls;
}
void Arch::addCellTimingClock(IdString cell, IdString port) { cellTiming[cell].portClasses[port] = TMG_CLOCK_INPUT; } void Arch::addCellTimingClock(IdString cell, IdString port) { cellTiming[cell].portClasses[port] = TMG_CLOCK_INPUT; }
@ -1019,7 +1022,7 @@ void Arch::addMuxBels(const DatabasePOD *db, int row, int col)
// bel // bel
snprintf(buf, 40, "R%dC%d_MUX2_LUT%c%c", grow, gcol, mux_names[j].type, mux_names[j].bel_idx); snprintf(buf, 40, "R%dC%d_MUX2_LUT%c%c", grow, gcol, mux_names[j].type, mux_names[j].bel_idx);
belname = id(buf); belname = id(buf);
snprintf(buf, 40, "GW_MUX2_LUT%c", mux_names[j].type); snprintf(buf, 40, "MUX2_LUT%c", mux_names[j].type);
bel_id = id(buf); bel_id = id(buf);
addBel(belname, bel_id, Loc(col, row, z), false); addBel(belname, bel_id, Loc(col, row, z), false);
@ -2041,16 +2044,16 @@ void Arch::assignArchInfo()
} }
break; break;
} }
case ID_GW_MUX2_LUT8: case ID_MUX2_LUT8:
delay = delay + delayLookup(speed->lut.timings.get(), speed->lut.num_timings, id_fx_ofx1); delay = delay + delayLookup(speed->lut.timings.get(), speed->lut.num_timings, id_fx_ofx1);
/* FALLTHRU */ /* FALLTHRU */
case ID_GW_MUX2_LUT7: case ID_MUX2_LUT7:
delay = delay + delayLookup(speed->lut.timings.get(), speed->lut.num_timings, id_fx_ofx1); delay = delay + delayLookup(speed->lut.timings.get(), speed->lut.num_timings, id_fx_ofx1);
/* FALLTHRU */ /* FALLTHRU */
case ID_GW_MUX2_LUT6: case ID_MUX2_LUT6:
delay = delay + delayLookup(speed->lut.timings.get(), speed->lut.num_timings, id_fx_ofx1); delay = delay + delayLookup(speed->lut.timings.get(), speed->lut.num_timings, id_fx_ofx1);
/* FALLTHRU */ /* FALLTHRU */
case ID_GW_MUX2_LUT5: { case ID_MUX2_LUT5: {
delay = delay + delayLookup(speed->lut.timings.get(), speed->lut.num_timings, id_fx_ofx1); delay = delay + delayLookup(speed->lut.timings.get(), speed->lut.num_timings, id_fx_ofx1);
addCellTimingDelay(cname, id_I0, id_OF, delay); addCellTimingDelay(cname, id_I0, id_OF, delay);
addCellTimingDelay(cname, id_I1, id_OF, delay); addCellTimingDelay(cname, id_I1, id_OF, delay);

2
gowin/arch.h
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@ -502,7 +502,7 @@ enum
{ {
mux_0_z = 10, // start Z for the MUX2LUT5 bels mux_0_z = 10, // start Z for the MUX2LUT5 bels
iologic_0_z = 20, // start Z for the IOLOGIC bels iologic_0_z = 20, // start Z for the IOLOGIC bels
lutram_0_z = 30, // start Z for the IOLOGIC bels lutram_0_z = 30, // start Z for the IOLOGIC bels
vcc_0_z = 277, // virtual VCC bel Z vcc_0_z = 277, // virtual VCC bel Z
gnd_0_z = 278, // virtual VSS bel Z gnd_0_z = 278, // virtual VSS bel Z
osc_z = 280, // Z for the oscillator bels osc_z = 280, // Z for the oscillator bels

6
gowin/cells.cc
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@ -56,8 +56,8 @@ std::unique_ptr<CellInfo> create_generic_cell(Context *ctx, IdString type, std::
new_cell->addInput(id_CLK); new_cell->addInput(id_CLK);
new_cell->addInput(id_CE); new_cell->addInput(id_CE);
new_cell->addInput(id_LSR); new_cell->addInput(id_LSR);
} else if (type == id_GW_MUX2_LUT5 || type == id_GW_MUX2_LUT6 || type == id_GW_MUX2_LUT7 || } else if (type == id_MUX2_LUT5 || type == id_MUX2_LUT6 || type == id_MUX2_LUT7 || type == id_MUX2_LUT7 ||
type == id_GW_MUX2_LUT7 || type == id_GW_MUX2_LUT8) { type == id_MUX2_LUT8) {
new_cell->addInput(id_I0); new_cell->addInput(id_I0);
new_cell->addInput(id_I1); new_cell->addInput(id_I1);
new_cell->addInput(id_SEL); new_cell->addInput(id_SEL);
@ -190,7 +190,7 @@ void sram_to_ramw_split(Context *ctx, CellInfo *ram, CellInfo *ramw)
ram->movePortTo(ctx->id("DI[1]"), ramw, id_B5); ram->movePortTo(ctx->id("DI[1]"), ramw, id_B5);
ram->movePortTo(ctx->id("DI[2]"), ramw, id_C5); ram->movePortTo(ctx->id("DI[2]"), ramw, id_C5);
ram->movePortTo(ctx->id("DI[3]"), ramw, id_D5); ram->movePortTo(ctx->id("DI[3]"), ramw, id_D5);
ram->movePortTo(ctx->id("CLK"), ramw, id_CLK); ram->movePortTo(ctx->id("CLK"), ramw, id_CLK);
ram->movePortTo(ctx->id("WRE"), ramw, id_LSR); ram->movePortTo(ctx->id("WRE"), ramw, id_LSR);
} }

8
gowin/cells.h
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@ -62,23 +62,15 @@ inline bool is_alu(const BaseCtx *ctx, const CellInfo *cell) { return (cell->typ
// is MUX2_LUT5 // is MUX2_LUT5
inline bool is_mux2_lut5(const BaseCtx *ctx, const CellInfo *cell) { return (cell->type.index == ID_MUX2_LUT5); } inline bool is_mux2_lut5(const BaseCtx *ctx, const CellInfo *cell) { return (cell->type.index == ID_MUX2_LUT5); }
inline bool is_gw_mux2_lut5(const BaseCtx *ctx, const CellInfo *cell) { return (cell->type.index == ID_GW_MUX2_LUT5); }
// is MUX2_LUT6 // is MUX2_LUT6
inline bool is_mux2_lut6(const BaseCtx *ctx, const CellInfo *cell) { return (cell->type.index == ID_MUX2_LUT6); } inline bool is_mux2_lut6(const BaseCtx *ctx, const CellInfo *cell) { return (cell->type.index == ID_MUX2_LUT6); }
inline bool is_gw_mux2_lut6(const BaseCtx *ctx, const CellInfo *cell) { return (cell->type.index == ID_GW_MUX2_LUT6); }
// is MUX2_LUT7 // is MUX2_LUT7
inline bool is_mux2_lut7(const BaseCtx *ctx, const CellInfo *cell) { return (cell->type.index == ID_MUX2_LUT7); } inline bool is_mux2_lut7(const BaseCtx *ctx, const CellInfo *cell) { return (cell->type.index == ID_MUX2_LUT7); }
inline bool is_gw_mux2_lut7(const BaseCtx *ctx, const CellInfo *cell) { return (cell->type.index == ID_GW_MUX2_LUT7); }
// is MUX2_LUT8 // is MUX2_LUT8
inline bool is_mux2_lut8(const BaseCtx *ctx, const CellInfo *cell) { return (cell->type.index == ID_MUX2_LUT8); } inline bool is_mux2_lut8(const BaseCtx *ctx, const CellInfo *cell) { return (cell->type.index == ID_MUX2_LUT8); }
inline bool is_gw_mux2_lut8(const BaseCtx *ctx, const CellInfo *cell) { return (cell->type.index == ID_GW_MUX2_LUT8); }
// Return true if a cell is a flipflop // Return true if a cell is a flipflop
inline bool is_ff(const BaseCtx *ctx, const CellInfo *cell) inline bool is_ff(const BaseCtx *ctx, const CellInfo *cell)
{ {

4
gowin/constids.inc
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@ -775,10 +775,6 @@ X(MUX2_LUT5)
X(MUX2_LUT6) X(MUX2_LUT6)
X(MUX2_LUT7) X(MUX2_LUT7)
X(MUX2_LUT8) X(MUX2_LUT8)
X(GW_MUX2_LUT5)
X(GW_MUX2_LUT6)
X(GW_MUX2_LUT7)
X(GW_MUX2_LUT8)
X(I0MUX0) X(I0MUX0)
X(I1MUX0) X(I1MUX0)
X(I0MUX1) X(I0MUX1)

8
gowin/gfx.cc
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@ -5637,28 +5637,28 @@ void gfxSetBelDefaultDecal(Arch *arch, BelInfo &bel)
} }
arch->setBelDecal(bel.name, active, inactive); arch->setBelDecal(bel.name, active, inactive);
break; break;
case ID_GW_MUX2_LUT5: case ID_MUX2_LUT5:
active.x = inactive.x = bel.x + mux2lut5_x; active.x = inactive.x = bel.x + mux2lut5_x;
active.y = inactive.y = arch->gridDimY - 1. - bel.y + mux2lut5_y[(bel.z - BelZ::mux_0_z) >> 1]; active.y = inactive.y = arch->gridDimY - 1. - bel.y + mux2lut5_y[(bel.z - BelZ::mux_0_z) >> 1];
active.decal = id_DECAL_MUXUPPER_ACTIVE; active.decal = id_DECAL_MUXUPPER_ACTIVE;
inactive.decal = id_DECAL_MUXUPPER_INACTIVE; inactive.decal = id_DECAL_MUXUPPER_INACTIVE;
arch->setBelDecal(bel.name, active, inactive); arch->setBelDecal(bel.name, active, inactive);
break; break;
case ID_GW_MUX2_LUT6: case ID_MUX2_LUT6:
active.x = inactive.x = bel.x + mux2lut6_x; active.x = inactive.x = bel.x + mux2lut6_x;
active.y = inactive.y = arch->gridDimY - 1. - bel.y + mux2lut6_y[(bel.z - BelZ::mux_0_z) / 5]; active.y = inactive.y = arch->gridDimY - 1. - bel.y + mux2lut6_y[(bel.z - BelZ::mux_0_z) / 5];
active.decal = id_DECAL_MUXLOWER_ACTIVE; active.decal = id_DECAL_MUXLOWER_ACTIVE;
inactive.decal = id_DECAL_MUXLOWER_INACTIVE; inactive.decal = id_DECAL_MUXLOWER_INACTIVE;
arch->setBelDecal(bel.name, active, inactive); arch->setBelDecal(bel.name, active, inactive);
break; break;
case ID_GW_MUX2_LUT7: case ID_MUX2_LUT7:
active.x = inactive.x = bel.x + mux2lut7_x; active.x = inactive.x = bel.x + mux2lut7_x;
active.y = inactive.y = arch->gridDimY - 1. - bel.y + mux2lut7_y; active.y = inactive.y = arch->gridDimY - 1. - bel.y + mux2lut7_y;
active.decal = id_DECAL_MUXLOWER_ACTIVE; active.decal = id_DECAL_MUXLOWER_ACTIVE;
inactive.decal = id_DECAL_MUXLOWER_INACTIVE; inactive.decal = id_DECAL_MUXLOWER_INACTIVE;
arch->setBelDecal(bel.name, active, inactive); arch->setBelDecal(bel.name, active, inactive);
break; break;
case ID_GW_MUX2_LUT8: case ID_MUX2_LUT8:
active.x = inactive.x = bel.x + mux2lut8_x; active.x = inactive.x = bel.x + mux2lut8_x;
active.y = inactive.y = arch->gridDimY - 1. - bel.y + mux2lut8_y; active.y = inactive.y = arch->gridDimY - 1. - bel.y + mux2lut8_y;
active.decal = id_DECAL_MUXUPPER_ACTIVE; active.decal = id_DECAL_MUXUPPER_ACTIVE;

21
gowin/pack.cc
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@ -266,7 +266,7 @@ static void pack_mux2_lut5(Context *ctx, CellInfo *ci, pool<IdString> &packed_ce
return; return;
} }
std::unique_ptr<CellInfo> packed = create_generic_cell(ctx, id_GW_MUX2_LUT5, ci->name.str(ctx) + "_LC"); std::unique_ptr<CellInfo> packed = create_generic_cell(ctx, id_MUX2_LUT5, ci->name.str(ctx) + "_LC");
if (ctx->verbose) { if (ctx->verbose) {
log_info("packed cell %s into %s\n", ctx->nameOf(ci), ctx->nameOf(packed.get())); log_info("packed cell %s into %s\n", ctx->nameOf(ci), ctx->nameOf(packed.get()));
} }
@ -309,7 +309,7 @@ static void pack_mux2_lut5(Context *ctx, CellInfo *ci, pool<IdString> &packed_ce
return; return;
} }
std::unique_ptr<CellInfo> packed = create_generic_cell(ctx, id_GW_MUX2_LUT5, ci->name.str(ctx) + "_LC"); std::unique_ptr<CellInfo> packed = create_generic_cell(ctx, id_MUX2_LUT5, ci->name.str(ctx) + "_LC");
if (ctx->verbose) { if (ctx->verbose) {
log_info("packed cell %s into %s\n", ctx->nameOf(ci), ctx->nameOf(packed.get())); log_info("packed cell %s into %s\n", ctx->nameOf(ci), ctx->nameOf(packed.get()));
} }
@ -413,7 +413,7 @@ static void pack_mux2_lut6(Context *ctx, CellInfo *ci, pool<IdString> &packed_ce
{ {
static int x[] = {0, 0}; static int x[] = {0, 0};
static int z[] = {+1, -1}; static int z[] = {+1, -1};
pack_mux2_lut(ctx, ci, is_gw_mux2_lut5, '6', id_GW_MUX2_LUT6, x, z, packed_cells, delete_nets, new_cells); pack_mux2_lut(ctx, ci, is_mux2_lut5, '6', id_MUX2_LUT6, x, z, packed_cells, delete_nets, new_cells);
} }
// pack MUX2_LUT7 // pack MUX2_LUT7
@ -422,7 +422,7 @@ static void pack_mux2_lut7(Context *ctx, CellInfo *ci, pool<IdString> &packed_ce
{ {
static int x[] = {0, 0}; static int x[] = {0, 0};
static int z[] = {+2, -2}; static int z[] = {+2, -2};
pack_mux2_lut(ctx, ci, is_gw_mux2_lut6, '7', id_GW_MUX2_LUT7, x, z, packed_cells, delete_nets, new_cells); pack_mux2_lut(ctx, ci, is_mux2_lut6, '7', id_MUX2_LUT7, x, z, packed_cells, delete_nets, new_cells);
} }
// pack MUX2_LUT8 // pack MUX2_LUT8
@ -431,7 +431,7 @@ static void pack_mux2_lut8(Context *ctx, CellInfo *ci, pool<IdString> &packed_ce
{ {
static int x[] = {1, 0}; static int x[] = {1, 0};
static int z[] = {-4, -4}; static int z[] = {-4, -4};
pack_mux2_lut(ctx, ci, is_gw_mux2_lut7, '8', id_GW_MUX2_LUT8, x, z, packed_cells, delete_nets, new_cells); pack_mux2_lut(ctx, ci, is_mux2_lut7, '8', id_MUX2_LUT8, x, z, packed_cells, delete_nets, new_cells);
} }
// Pack wide LUTs // Pack wide LUTs
@ -707,16 +707,14 @@ void pack_sram(Context *ctx)
if (is_sram(ctx, ci)) { if (is_sram(ctx, ci)) {
// Create RAMW slice // Create RAMW slice
std::unique_ptr<CellInfo> ramw_slice = std::unique_ptr<CellInfo> ramw_slice = create_generic_cell(ctx, id_RAMW, ci->name.str(ctx) + "$RAMW_SLICE");
create_generic_cell(ctx, id_RAMW, ci->name.str(ctx) + "$RAMW_SLICE");
sram_to_ramw_split(ctx, ci, ramw_slice.get()); sram_to_ramw_split(ctx, ci, ramw_slice.get());
ramw_slice->connectPort(id_CE, ctx->nets[ctx->id("$PACKER_VCC_NET")].get()); ramw_slice->connectPort(id_CE, ctx->nets[ctx->id("$PACKER_VCC_NET")].get());
// Create actual RAM slices // Create actual RAM slices
std::unique_ptr<CellInfo> ram_comb[4]; std::unique_ptr<CellInfo> ram_comb[4];
for (int i = 0; i < 4; i++) { for (int i = 0; i < 4; i++) {
ram_comb[i] = create_generic_cell(ctx, id_SLICE, ram_comb[i] = create_generic_cell(ctx, id_SLICE, ci->name.str(ctx) + "$SRAM_SLICE" + std::to_string(i));
ci->name.str(ctx) + "$SRAM_SLICE" + std::to_string(i));
ram_comb[i]->params[id_FF_USED] = 1; ram_comb[i]->params[id_FF_USED] = 1;
ram_comb[i]->params[id_FF_TYPE] = std::string("RAM"); ram_comb[i]->params[id_FF_TYPE] = std::string("RAM");
sram_to_slice(ctx, ci, ram_comb[i].get(), i); sram_to_slice(ctx, ci, ram_comb[i].get(), i);
@ -724,8 +722,8 @@ void pack_sram(Context *ctx)
// Create 'block' SLICEs as a placement hint that these cells are mutually exclusive with the RAMW // Create 'block' SLICEs as a placement hint that these cells are mutually exclusive with the RAMW
std::unique_ptr<CellInfo> ramw_block[2]; std::unique_ptr<CellInfo> ramw_block[2];
for (int i = 0; i < 2; i++) { for (int i = 0; i < 2; i++) {
ramw_block[i] = create_generic_cell(ctx, id_SLICE, ramw_block[i] =
ci->name.str(ctx) + "$RAMW_BLOCK" + std::to_string(i)); create_generic_cell(ctx, id_SLICE, ci->name.str(ctx) + "$RAMW_BLOCK" + std::to_string(i));
ram_comb[i]->params[id_FF_USED] = 1; ram_comb[i]->params[id_FF_USED] = 1;
ramw_block[i]->params[id_FF_TYPE] = std::string("RAM"); ramw_block[i]->params[id_FF_TYPE] = std::string("RAM");
} }
@ -782,7 +780,6 @@ void pack_sram(Context *ctx)
} }
} }
static bool is_nextpnr_iob(const Context *ctx, CellInfo *cell) static bool is_nextpnr_iob(const Context *ctx, CellInfo *cell)
{ {
return cell->type == ctx->id("$nextpnr_ibuf") || cell->type == ctx->id("$nextpnr_obuf") || return cell->type == ctx->id("$nextpnr_ibuf") || cell->type == ctx->id("$nextpnr_obuf") ||