diff --git a/himbaechel/uarch/gowin/gowin_arch_gen.py b/himbaechel/uarch/gowin/gowin_arch_gen.py
index 7b0f37e3..0921c089 100644
--- a/himbaechel/uarch/gowin/gowin_arch_gen.py
+++ b/himbaechel/uarch/gowin/gowin_arch_gen.py
@@ -402,7 +402,7 @@ def create_io_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int, tdesc:
         tt.create_wire(portmap['OE'], "IO_OE")
         # bels
         io = tt.create_bel(name, "IOB", z = IOBA_Z + i)
-        if simple_io:
+        if simple_io and chip.name in {'GW1N-1'}:
             io.flags |= BEL_FLAG_SIMPLE_IO
         tt.add_bel_pin(io, "I", portmap['I'], PinType.INPUT)
         tt.add_bel_pin(io, "OEN", portmap['OE'], PinType.INPUT)
diff --git a/himbaechel/uarch/gowin/pack.cc b/himbaechel/uarch/gowin/pack.cc
index 34a7e88d..e4a729bd 100644
--- a/himbaechel/uarch/gowin/pack.cc
+++ b/himbaechel/uarch/gowin/pack.cc
@@ -154,6 +154,10 @@ struct GowinPacker
         if (bel == BelId()) {
             log_error("No bel named %s\n", IdStringList::parse(ctx, ci.attrs.at(id_BEL).as_string()).str(ctx).c_str());
         }
+        if (!ctx->checkBelAvail(bel)) {
+            log_error("Can't place %s at %s because it's already taken by %s\n", ctx->nameOf(&ci), ctx->nameOfBel(bel),
+                      ctx->nameOf(ctx->getBoundBelCell(bel)));
+        }
         ci.unsetAttr(id_BEL);
         ctx->bindBel(bel, &ci, PlaceStrength::STRENGTH_LOCKED);
         return bel;