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gowin: Himbaechel. Fix IO for GW1NZ-1

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In these chips, the midline IOs are still simple, but are no longer just
IOBUF - that is, unlike the GW1N-1 IBUF and OBUF are not obtained by
applying a signal to the OEN input.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
This commit is contained in:
YRabbit 2023-08-19 17:49:25 +10:00 committed by myrtle
parent 84a27c3ebf
commit 1b926b2703
2 changed files with 5 additions and 1 deletions
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2
himbaechel/uarch/gowin/gowin_arch_gen.py
View File

@ -402,7 +402,7 @@ def create_io_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int, tdesc:
tt.create_wire(portmap['OE'], "IO_OE")
# bels
io = tt.create_bel(name, "IOB", z = IOBA_Z + i)
if simple_io:
if simple_io and chip.name in {'GW1N-1'}:
io.flags |= BEL_FLAG_SIMPLE_IO
tt.add_bel_pin(io, "I", portmap['I'], PinType.INPUT)
tt.add_bel_pin(io, "OEN", portmap['OE'], PinType.INPUT)

4
himbaechel/uarch/gowin/pack.cc
View File

@ -154,6 +154,10 @@ struct GowinPacker
if (bel == BelId()) {
log_error("No bel named %s\n", IdStringList::parse(ctx, ci.attrs.at(id_BEL).as_string()).str(ctx).c_str());
}
if (!ctx->checkBelAvail(bel)) {
log_error("Can't place %s at %s because it's already taken by %s\n", ctx->nameOf(&ci), ctx->nameOfBel(bel),
ctx->nameOf(ctx->getBoundBelCell(bel)));
}
ci.unsetAttr(id_BEL);
ctx->bindBel(bel, &ci, PlaceStrength::STRENGTH_LOCKED);
return bel;