diff --git a/common/kernel/exclusive_state_groups.h b/common/kernel/exclusive_state_groups.h index b99876ba..508e94dd 100644 --- a/common/kernel/exclusive_state_groups.h +++ b/common/kernel/exclusive_state_groups.h @@ -125,10 +125,7 @@ template - bool - requires_range(const StateRange &state_range) - const + template bool requires_range(const StateRange &state_range) const { if (state < 0) { return false; diff --git a/himbaechel/arch.cc b/himbaechel/arch.cc index 6f5b303e..f7ca2357 100644 --- a/himbaechel/arch.cc +++ b/himbaechel/arch.cc @@ -23,13 +23,11 @@ #include "log.h" #include "nextpnr.h" -#include "util.h" #include "placer1.h" #include "placer_heap.h" #include "router1.h" #include "router2.h" - - +#include "util.h" NEXTPNR_NAMESPACE_BEGIN diff --git a/mistral/arch.h b/mistral/arch.h index eb0093fb..bc950566 100644 --- a/mistral/arch.h +++ b/mistral/arch.h @@ -435,8 +435,8 @@ struct Arch : BaseArch int &clockInfoCount) const override; // delay.cc TimingClockingInfo getPortClockingInfo(const CellInfo *cell, IdString port, int index) const override; // delay.cc bool getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, - DelayQuad &delay) const override; // delay.cc - DelayQuad getPipDelay(PipId pip) const override; // delay.cc + DelayQuad &delay) const override; // delay.cc + DelayQuad getPipDelay(PipId pip) const override; // delay.cc bool getArcDelayOverride(const NetInfo *net_info, const PortRef &sink, DelayQuad &delay) const override; // delay.cc // ------------------------------------------------- diff --git a/mistral/bitstream.cc b/mistral/bitstream.cc index f9cb40ff..c7fe7ccb 100644 --- a/mistral/bitstream.cc +++ b/mistral/bitstream.cc @@ -19,8 +19,8 @@ #include "log.h" #include "nextpnr.h" -#include "util.h" #include "timing.h" +#include "util.h" NEXTPNR_NAMESPACE_BEGIN namespace { diff --git a/mistral/delay.cc b/mistral/delay.cc index 7d999b01..896e518b 100644 --- a/mistral/delay.cc +++ b/mistral/delay.cc @@ -362,22 +362,29 @@ bool Arch::getArcDelayOverride(const NetInfo *net_info, const PortRef &sink, Del } if (input_wave[0].empty()) { - cyclonev->rnode_timing_build_input_wave(src.node, temp, CycloneV::DELAY_MAX, inverted ? mistral::CycloneV::RF_FALL : mistral::CycloneV::RF_RISE, est, input_wave[0]); - cyclonev->rnode_timing_build_input_wave(src.node, temp, CycloneV::DELAY_MAX, inverted ? mistral::CycloneV::RF_RISE : mistral::CycloneV::RF_FALL, est, input_wave[1]); - NPNR_ASSERT(!input_wave[mistral::CycloneV::RF_RISE].empty() && !input_wave[mistral::CycloneV::RF_FALL].empty()); + cyclonev->rnode_timing_build_input_wave(src.node, temp, CycloneV::DELAY_MAX, + inverted ? mistral::CycloneV::RF_FALL : mistral::CycloneV::RF_RISE, + est, input_wave[0]); + cyclonev->rnode_timing_build_input_wave(src.node, temp, CycloneV::DELAY_MAX, + inverted ? mistral::CycloneV::RF_RISE : mistral::CycloneV::RF_FALL, + est, input_wave[1]); + NPNR_ASSERT(!input_wave[mistral::CycloneV::RF_RISE].empty() && + !input_wave[mistral::CycloneV::RF_FALL].empty()); } for (int edge = 0; edge != 2; edge++) { - auto actual_edge = edge ? inverted ? mistral::CycloneV::RF_RISE : mistral::CycloneV::RF_FALL : inverted ? mistral::CycloneV::RF_FALL : mistral::CycloneV::RF_RISE; + auto actual_edge = edge ? inverted ? mistral::CycloneV::RF_RISE : mistral::CycloneV::RF_FALL + : inverted ? mistral::CycloneV::RF_FALL + : mistral::CycloneV::RF_RISE; mistral::AnalogSim sim; int input = -1; std::vector> outputs; cyclonev->rnode_timing_build_circuit(src.node, temp, CycloneV::DELAY_MAX, actual_edge, sim, input, outputs); sim.set_input_wave(input, input_wave[edge]); - auto o = std::find_if(outputs.begin(), outputs.end(), [&](std::pair output) { - return output.first == dst.node; - }); + auto o = std::find_if( + outputs.begin(), outputs.end(), + [&](std::pair output) { return output.first == dst.node; }); NPNR_ASSERT(o != outputs.end()); output_wave[edge].clear(); @@ -393,7 +400,8 @@ bool Arch::getArcDelayOverride(const NetInfo *net_info, const PortRef &sink, Del inverted = !inverted; } - delay = DelayQuad{delay_t(output_delay_sum[0].mi*1e12), delay_t(output_delay_sum[0].mx*1e12), delay_t(output_delay_sum[1].mi*1e12), delay_t(output_delay_sum[1].mx*1e12)}; + delay = DelayQuad{delay_t(output_delay_sum[0].mi * 1e12), delay_t(output_delay_sum[0].mx * 1e12), + delay_t(output_delay_sum[1].mi * 1e12), delay_t(output_delay_sum[1].mx * 1e12)}; return true; } @@ -406,7 +414,7 @@ delay_t Arch::predictDelay(BelId src_bel, IdString src_pin, BelId dst_bel, IdStr Loc dst_loc = getBelLocation(dst_bel); int x_diff = std::abs(dst_loc.x - src_loc.x); int y_diff = std::abs(dst_loc.y - src_loc.y); - return 43*x_diff + 114*y_diff + 470; + return 43 * x_diff + 114 * y_diff + 470; } delay_t Arch::estimateDelay(WireId src, WireId dst) const @@ -417,7 +425,7 @@ delay_t Arch::estimateDelay(WireId src, WireId dst) const int y1 = CycloneV::rn2y(dst.node); int x_diff = std::abs(x1 - x0); int y_diff = std::abs(y1 - y0); - return 43*x_diff + 114*y_diff + 470; + return 43 * x_diff + 114 * y_diff + 470; } NEXTPNR_NAMESPACE_END