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Code formatting

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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
This commit is contained in:
Maciej Kurc 2021-09-29 14:59:09 +02:00
parent 76f5874ffc
commit 1db3a87c62
4 changed files with 86 additions and 118 deletions
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3
common/command.cc
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@ -179,8 +179,7 @@ po::options_description CommandHandler::getGeneralOptions()
general.add_options()("report", po::value<std::string>(), general.add_options()("report", po::value<std::string>(),
"write timing and utilization report in JSON format to file"); "write timing and utilization report in JSON format to file");
general.add_options()("detailed-timing-report", general.add_options()("detailed-timing-report", "Append detailed net timing data to the JSON report");
"Append detailed net timing data to the JSON report");
general.add_options()("placed-svg", po::value<std::string>(), "write render of placement to SVG file"); general.add_options()("placed-svg", po::value<std::string>(), "write render of placement to SVG file");
general.add_options()("routed-svg", po::value<std::string>(), "write render of routing to SVG file"); general.add_options()("routed-svg", po::value<std::string>(), "write render of routing to SVG file");

6
common/nextpnr_types.h
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@ -242,10 +242,12 @@ struct ClockPair
struct CriticalPath struct CriticalPath
{ {
struct Segment { struct Segment
{
// Segment type // Segment type
enum class Type { enum class Type
{
CLK_TO_Q, // Clock-to-Q delay CLK_TO_Q, // Clock-to-Q delay
SOURCE, // Delayless source SOURCE, // Delayless source
LOGIC, // Combinational logic delay LOGIC, // Combinational logic delay

79
common/report.cc
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@ -41,40 +41,37 @@ dict<IdString, std::pair<int, int>> get_utilization(const Context *ctx)
} }
} // namespace } // namespace
static std::string clock_event_name (const Context* ctx, const ClockEvent& e) { static std::string clock_event_name(const Context *ctx, const ClockEvent &e)
{
std::string value; std::string value;
if (e.clock == ctx->id("$async$")) if (e.clock == ctx->id("$async$"))
value = std::string("<async>"); value = std::string("<async>");
else else
value = (e.edge == FALLING_EDGE ? std::string("negedge ") : value = (e.edge == FALLING_EDGE ? std::string("negedge ") : std::string("posedge ")) + e.clock.str(ctx);
std::string("posedge ")) + e.clock.str(ctx);
return value; return value;
}; };
static Json::array report_critical_paths (const Context* ctx) { static Json::array report_critical_paths(const Context *ctx)
{
auto report_critical_path = [ctx](const CriticalPath& report) { auto report_critical_path = [ctx](const CriticalPath &report) {
Json::array pathJson; Json::array pathJson;
for (const auto& segment : report.segments) { for (const auto &segment : report.segments) {
const auto& driver = ctx->cells.at(segment.from.first); const auto &driver = ctx->cells.at(segment.from.first);
const auto& sink = ctx->cells.at(segment.to.first); const auto &sink = ctx->cells.at(segment.to.first);
auto fromLoc = ctx->getBelLocation(driver->bel); auto fromLoc = ctx->getBelLocation(driver->bel);
auto toLoc = ctx->getBelLocation(sink->bel); auto toLoc = ctx->getBelLocation(sink->bel);
auto fromJson = Json::object({ auto fromJson = Json::object({{"cell", segment.from.first.c_str(ctx)},
{"cell", segment.from.first.c_str(ctx)},
{"port", segment.from.second.c_str(ctx)}, {"port", segment.from.second.c_str(ctx)},
{"loc", Json::array({fromLoc.x, fromLoc.y})} {"loc", Json::array({fromLoc.x, fromLoc.y})}});
});
auto toJson = Json::object({ auto toJson = Json::object({{"cell", segment.to.first.c_str(ctx)},
{"cell", segment.to.first.c_str(ctx)},
{"port", segment.to.second.c_str(ctx)}, {"port", segment.to.second.c_str(ctx)},
{"loc", Json::array({toLoc.x, toLoc.y})} {"loc", Json::array({toLoc.x, toLoc.y})}});
});
auto segmentJson = Json::object({ auto segmentJson = Json::object({
{"delay", ctx->getDelayNS(segment.delay)}, {"delay", ctx->getDelayNS(segment.delay)},
@ -84,17 +81,13 @@ static Json::array report_critical_paths (const Context* ctx) {
if (segment.type == CriticalPath::Segment::Type::CLK_TO_Q) { if (segment.type == CriticalPath::Segment::Type::CLK_TO_Q) {
segmentJson["type"] = "clk-to-q"; segmentJson["type"] = "clk-to-q";
} } else if (segment.type == CriticalPath::Segment::Type::SOURCE) {
else if (segment.type == CriticalPath::Segment::Type::SOURCE) {
segmentJson["type"] = "source"; segmentJson["type"] = "source";
} } else if (segment.type == CriticalPath::Segment::Type::LOGIC) {
else if (segment.type == CriticalPath::Segment::Type::LOGIC) {
segmentJson["type"] = "logic"; segmentJson["type"] = "logic";
} } else if (segment.type == CriticalPath::Segment::Type::SETUP) {
else if (segment.type == CriticalPath::Segment::Type::SETUP) {
segmentJson["type"] = "setup"; segmentJson["type"] = "setup";
} } else if (segment.type == CriticalPath::Segment::Type::ROUTING) {
else if (segment.type == CriticalPath::Segment::Type::ROUTING) {
segmentJson["type"] = "routing"; segmentJson["type"] = "routing";
segmentJson["net"] = segment.net.c_str(ctx); segmentJson["net"] = segment.net.c_str(ctx);
segmentJson["budget"] = ctx->getDelayNS(segment.budget); segmentJson["budget"] = ctx->getDelayNS(segment.budget);
@ -111,58 +104,51 @@ static Json::array report_critical_paths (const Context* ctx) {
// Critical paths // Critical paths
for (auto &report : ctx->timing_result.clock_paths) { for (auto &report : ctx->timing_result.clock_paths) {
critPathsJson.push_back(Json::object({ critPathsJson.push_back(Json::object({{"from", clock_event_name(ctx, report.second.clock_pair.start)},
{"from", clock_event_name(ctx, report.second.clock_pair.start)},
{"to", clock_event_name(ctx, report.second.clock_pair.end)}, {"to", clock_event_name(ctx, report.second.clock_pair.end)},
{"path", report_critical_path(report.second)} {"path", report_critical_path(report.second)}}));
}));
} }
// Cross-domain paths // Cross-domain paths
for (auto &report : ctx->timing_result.xclock_paths) { for (auto &report : ctx->timing_result.xclock_paths) {
critPathsJson.push_back(Json::object({ critPathsJson.push_back(Json::object({{"from", clock_event_name(ctx, report.clock_pair.start)},
{"from", clock_event_name(ctx, report.clock_pair.start)},
{"to", clock_event_name(ctx, report.clock_pair.end)}, {"to", clock_event_name(ctx, report.clock_pair.end)},
{"path", report_critical_path(report)} {"path", report_critical_path(report)}}));
}));
} }
return critPathsJson; return critPathsJson;
} }
static Json::array report_detailed_net_timings (const Context* ctx) { static Json::array report_detailed_net_timings(const Context *ctx)
{
auto detailedNetTimingsJson = Json::array(); auto detailedNetTimingsJson = Json::array();
// Detailed per-net timing analysis // Detailed per-net timing analysis
for (const auto& it : ctx->timing_result.detailed_net_timings) { for (const auto &it : ctx->timing_result.detailed_net_timings) {
const NetInfo* net = ctx->nets.at(it.first).get(); const NetInfo *net = ctx->nets.at(it.first).get();
ClockEvent start = it.second[0].clock_pair.start; ClockEvent start = it.second[0].clock_pair.start;
Json::array endpointsJson; Json::array endpointsJson;
for (const auto& sink_timing : it.second) { for (const auto &sink_timing : it.second) {
// FIXME: Is it possible that there are multiple different start // FIXME: Is it possible that there are multiple different start
// events for a single net? It has a single driver // events for a single net? It has a single driver
NPNR_ASSERT(sink_timing.clock_pair.start == start); NPNR_ASSERT(sink_timing.clock_pair.start == start);
auto endpointJson = Json::object({ auto endpointJson = Json::object({{"cell", sink_timing.cell_port.first.c_str(ctx)},
{"cell", sink_timing.cell_port.first.c_str(ctx)},
{"port", sink_timing.cell_port.second.c_str(ctx)}, {"port", sink_timing.cell_port.second.c_str(ctx)},
{"event", clock_event_name(ctx, sink_timing.clock_pair.end)}, {"event", clock_event_name(ctx, sink_timing.clock_pair.end)},
{"delay", ctx->getDelayNS(sink_timing.delay)}, {"delay", ctx->getDelayNS(sink_timing.delay)},
{"budget", ctx->getDelayNS(sink_timing.budget)} {"budget", ctx->getDelayNS(sink_timing.budget)}});
});
endpointsJson.push_back(endpointJson); endpointsJson.push_back(endpointJson);
} }
auto netTimingJson = Json::object({ auto netTimingJson = Json::object({{"net", net->name.c_str(ctx)},
{"net", net->name.c_str(ctx)},
{"driver", net->driver.cell->name.c_str(ctx)}, {"driver", net->driver.cell->name.c_str(ctx)},
{"port", net->driver.port.c_str(ctx)}, {"port", net->driver.port.c_str(ctx)},
{"event", clock_event_name(ctx, start)}, {"event", clock_event_name(ctx, start)},
{"endpoints", endpointsJson} {"endpoints", endpointsJson}});
});
detailedNetTimingsJson.push_back(netTimingJson); detailedNetTimingsJson.push_back(netTimingJson);
} }
@ -261,10 +247,7 @@ void Context::writeReport(std::ostream &out) const
} }
Json::object jsonRoot{ Json::object jsonRoot{
{"utilization", util_json}, {"utilization", util_json}, {"fmax", fmax_json}, {"critical_paths", report_critical_paths(this)}};
{"fmax", fmax_json},
{"critical_paths", report_critical_paths(this)}
};
if (detailed_timing_report) { if (detailed_timing_report) {
jsonRoot["detailed_net_timings"] = report_detailed_net_timings(this); jsonRoot["detailed_net_timings"] = report_detailed_net_timings(this);

70
common/timing.cc
View File

@ -644,8 +644,7 @@ struct Timing
}; };
Timing(Context *ctx, bool net_delays, bool update, CriticalPathDataMap *crit_path = nullptr, Timing(Context *ctx, bool net_delays, bool update, CriticalPathDataMap *crit_path = nullptr,
DelayFrequency *slack_histogram = nullptr, DelayFrequency *slack_histogram = nullptr, DetailedNetTimings *detailed_net_timings = nullptr)
DetailedNetTimings *detailed_net_timings = nullptr)
: ctx(ctx), net_delays(net_delays), update(update), min_slack(1.0e12 / ctx->setting<float>("target_freq")), : ctx(ctx), net_delays(net_delays), update(update), min_slack(1.0e12 / ctx->setting<float>("target_freq")),
crit_path(crit_path), slack_histogram(slack_histogram), detailed_net_timings(detailed_net_timings), crit_path(crit_path), slack_histogram(slack_histogram), detailed_net_timings(detailed_net_timings),
async_clock(ctx->id("$async$")) async_clock(ctx->id("$async$"))
@ -1108,7 +1107,8 @@ void assign_budget(Context *ctx, bool quiet)
log_info("Checksum: 0x%08x\n", ctx->checksum()); log_info("Checksum: 0x%08x\n", ctx->checksum());
} }
CriticalPath build_critical_path_report(Context* ctx, ClockPair &clocks, const PortRefVector &crit_path) { CriticalPath build_critical_path_report(Context *ctx, ClockPair &clocks, const PortRefVector &crit_path)
{
CriticalPath report; CriticalPath report;
report.clock_pair = clocks; report.clock_pair = clocks;
@ -1120,7 +1120,7 @@ CriticalPath build_critical_path_report(Context* ctx, ClockPair &clocks, const P
int port_clocks; int port_clocks;
auto portClass = ctx->getPortTimingClass(front_driver.cell, front_driver.port, port_clocks); auto portClass = ctx->getPortTimingClass(front_driver.cell, front_driver.port, port_clocks);
const CellInfo* last_cell = front->cell; const CellInfo *last_cell = front->cell;
IdString last_port = front_driver.port; IdString last_port = front_driver.port;
int clock_start = -1; int clock_start = -1;
@ -1128,8 +1128,7 @@ CriticalPath build_critical_path_report(Context* ctx, ClockPair &clocks, const P
for (int i = 0; i < port_clocks; i++) { for (int i = 0; i < port_clocks; i++) {
TimingClockingInfo clockInfo = ctx->getPortClockingInfo(front_driver.cell, front_driver.port, i); TimingClockingInfo clockInfo = ctx->getPortClockingInfo(front_driver.cell, front_driver.port, i);
const NetInfo *clknet = get_net_or_empty(front_driver.cell, clockInfo.clock_port); const NetInfo *clknet = get_net_or_empty(front_driver.cell, clockInfo.clock_port);
if (clknet != nullptr && clknet->name == clocks.start.clock && if (clknet != nullptr && clknet->name == clocks.start.clock && clockInfo.edge == clocks.start.edge) {
clockInfo.edge == clocks.start.edge) {
last_port = clockInfo.clock_port; last_port = clockInfo.clock_port;
clock_start = i; clock_start = i;
break; break;
@ -1202,7 +1201,8 @@ CriticalPath build_critical_path_report(Context* ctx, ClockPair &clocks, const P
return report; return report;
} }
void timing_analysis(Context *ctx, bool print_histogram, bool print_fmax, bool print_path, bool warn_on_failure, bool update_results) void timing_analysis(Context *ctx, bool print_histogram, bool print_fmax, bool print_path, bool warn_on_failure,
bool update_results)
{ {
auto format_event = [ctx](const ClockEvent &e, int field_width = 0) { auto format_event = [ctx](const ClockEvent &e, int field_width = 0) {
std::string value; std::string value;
@ -1274,9 +1274,8 @@ void timing_analysis(Context *ctx, bool print_histogram, bool print_fmax, bool p
} }
std::sort(xclock_reports.begin(), xclock_reports.end(), [ctx](const CriticalPath &ra, const CriticalPath &rb) { std::sort(xclock_reports.begin(), xclock_reports.end(), [ctx](const CriticalPath &ra, const CriticalPath &rb) {
const auto &a = ra.clock_pair;
const auto& a = ra.clock_pair; const auto &b = rb.clock_pair;
const auto& b = rb.clock_pair;
if (a.start.clock.str(ctx) < b.start.clock.str(ctx)) if (a.start.clock.str(ctx) < b.start.clock.str(ctx))
return true; return true;
@ -1334,55 +1333,40 @@ void timing_analysis(Context *ctx, bool print_histogram, bool print_fmax, bool p
}; };
// A helper function for reporting one critical path // A helper function for reporting one critical path
auto print_path_report = [ctx](const CriticalPath& path) { auto print_path_report = [ctx](const CriticalPath &path) {
delay_t total = 0, logic_total = 0, route_total = 0; delay_t total = 0, logic_total = 0, route_total = 0;
log_info("curr total\n"); log_info("curr total\n");
for (const auto& segment : path.segments) { for (const auto &segment : path.segments) {
total += segment.delay; total += segment.delay;
if (segment.type == CriticalPath::Segment::Type::CLK_TO_Q || if (segment.type == CriticalPath::Segment::Type::CLK_TO_Q ||
segment.type == CriticalPath::Segment::Type::SOURCE || segment.type == CriticalPath::Segment::Type::SOURCE ||
segment.type == CriticalPath::Segment::Type::LOGIC || segment.type == CriticalPath::Segment::Type::LOGIC ||
segment.type == CriticalPath::Segment::Type::SETUP) segment.type == CriticalPath::Segment::Type::SETUP) {
{
logic_total += segment.delay; logic_total += segment.delay;
const std::string type_name = const std::string type_name =
(segment.type == CriticalPath::Segment::Type::SETUP) ? (segment.type == CriticalPath::Segment::Type::SETUP) ? "Setup" : "Source";
"Setup" : "Source";
log_info("%4.1f %4.1f %s %s.%s\n", log_info("%4.1f %4.1f %s %s.%s\n", ctx->getDelayNS(segment.delay), ctx->getDelayNS(total),
ctx->getDelayNS(segment.delay), type_name.c_str(), segment.to.first.c_str(ctx), segment.to.second.c_str(ctx));
ctx->getDelayNS(total), } else if (segment.type == CriticalPath::Segment::Type::ROUTING) {
type_name.c_str(),
segment.to.first.c_str(ctx),
segment.to.second.c_str(ctx)
);
}
else if (segment.type == CriticalPath::Segment::Type::ROUTING) {
route_total += segment.delay; route_total += segment.delay;
const auto& driver = ctx->cells.at(segment.from.first); const auto &driver = ctx->cells.at(segment.from.first);
const auto& sink = ctx->cells.at(segment.to.first); const auto &sink = ctx->cells.at(segment.to.first);
auto driver_loc = ctx->getBelLocation(driver->bel); auto driver_loc = ctx->getBelLocation(driver->bel);
auto sink_loc = ctx->getBelLocation(sink->bel); auto sink_loc = ctx->getBelLocation(sink->bel);
log_info("%4.1f %4.1f Net %s budget %f ns (%d,%d) -> (%d,%d)\n", log_info("%4.1f %4.1f Net %s budget %f ns (%d,%d) -> (%d,%d)\n", ctx->getDelayNS(segment.delay),
ctx->getDelayNS(segment.delay), ctx->getDelayNS(total), segment.net.c_str(ctx), ctx->getDelayNS(segment.budget),
ctx->getDelayNS(total), driver_loc.x, driver_loc.y, sink_loc.x, sink_loc.y);
segment.net.c_str(ctx), log_info(" Sink %s.%s\n", segment.to.first.c_str(ctx), segment.to.second.c_str(ctx));
ctx->getDelayNS(segment.budget),
driver_loc.x, driver_loc.y, sink_loc.x, sink_loc.y
);
log_info(" Sink %s.%s\n",
segment.to.first.c_str(ctx),
segment.to.second.c_str(ctx)
);
const NetInfo* net = ctx->nets.at(segment.net).get(); const NetInfo *net = ctx->nets.at(segment.net).get();
if (ctx->verbose) { if (ctx->verbose) {
@ -1424,8 +1408,8 @@ void timing_analysis(Context *ctx, bool print_histogram, bool print_fmax, bool p
// Single domain paths // Single domain paths
for (auto &clock : clock_reports) { for (auto &clock : clock_reports) {
log_break(); log_break();
std::string start = std::string start = clock.second.clock_pair.start.edge == FALLING_EDGE ? std::string("negedge")
clock.second.clock_pair.start.edge == FALLING_EDGE ? std::string("negedge") : std::string("posedge"); : std::string("posedge");
std::string end = std::string end =
clock.second.clock_pair.end.edge == FALLING_EDGE ? std::string("negedge") : std::string("posedge"); clock.second.clock_pair.end.edge == FALLING_EDGE ? std::string("negedge") : std::string("posedge");
log_info("Critical path report for clock '%s' (%s -> %s):\n", clock.first.c_str(ctx), start.c_str(), log_info("Critical path report for clock '%s' (%s -> %s):\n", clock.first.c_str(ctx), start.c_str(),
@ -1485,7 +1469,7 @@ void timing_analysis(Context *ctx, bool print_histogram, bool print_fmax, bool p
const ClockEvent &a = report.clock_pair.start; const ClockEvent &a = report.clock_pair.start;
const ClockEvent &b = report.clock_pair.end; const ClockEvent &b = report.clock_pair.end;
delay_t path_delay = 0; delay_t path_delay = 0;
for (const auto& segment : report.segments) { for (const auto &segment : report.segments) {
path_delay += segment.delay; path_delay += segment.delay;
} }
auto ev_a = format_event(a, start_field_width), ev_b = format_event(b, end_field_width); auto ev_a = format_event(a, start_field_width), ev_b = format_event(b, end_field_width);
@ -1526,7 +1510,7 @@ void timing_analysis(Context *ctx, bool print_histogram, bool print_fmax, bool p
// Update timing results in the context // Update timing results in the context
if (update_results) { if (update_results) {
auto& results = ctx->timing_result; auto &results = ctx->timing_result;
results.clock_fmax = std::move(clock_fmax); results.clock_fmax = std::move(clock_fmax);
results.clock_paths = std::move(clock_reports); results.clock_paths = std::move(clock_reports);