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Merge pull request #76 from YosysHQ/plloutglobal_fix

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Add needed PLLOUTGLOBAL ports and mapped it
This commit is contained in:
Clifford Wolf 2018-09-25 18:15:00 +02:00 committed by GitHub
commit 1eb7411fb0
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GPG Key ID: 4AEE18F83AFDEB23
3 changed files with 38 additions and 4 deletions
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2
common/log.cc
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@ -195,7 +195,6 @@ void log_info(const char *format, ...)
void log_warning(const char *format, ...) void log_warning(const char *format, ...)
{ {
if (log_quiet_warnings) return;
va_list ap; va_list ap;
va_start(ap, format); va_start(ap, format);
logv_warning(format, ap); logv_warning(format, ap);
@ -204,7 +203,6 @@ void log_warning(const char *format, ...)
void log_warning_noprefix(const char *format, ...) void log_warning_noprefix(const char *format, ...)
{ {
if (log_quiet_warnings) return;
va_list ap; va_list ap;
va_start(ap, format); va_start(ap, format);
logv_warning_noprefix(format, ap); logv_warning_noprefix(format, ap);

2
ice40/cells.cc
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@ -243,6 +243,8 @@ std::unique_ptr<CellInfo> create_ice_cell(Context *ctx, IdString type, std::stri
add_port(ctx, new_cell.get(), "LOCK", PORT_OUT); add_port(ctx, new_cell.get(), "LOCK", PORT_OUT);
add_port(ctx, new_cell.get(), "PLLOUT_A", PORT_OUT); add_port(ctx, new_cell.get(), "PLLOUT_A", PORT_OUT);
add_port(ctx, new_cell.get(), "PLLOUT_B", PORT_OUT); add_port(ctx, new_cell.get(), "PLLOUT_B", PORT_OUT);
add_port(ctx, new_cell.get(), "PLLOUTGLOBALA", PORT_OUT);
add_port(ctx, new_cell.get(), "PLLOUTGLOBALB", PORT_OUT);
} else { } else {
log_error("unable to create iCE40 cell of type %s", type.c_str(ctx)); log_error("unable to create iCE40 cell of type %s", type.c_str(ctx));
} }

38
ice40/pack.cc
View File

@ -717,6 +717,30 @@ static void pack_special(Context *ctx)
NetInfo *pad_packagepin_net = nullptr; NetInfo *pad_packagepin_net = nullptr;
int pllout_a_used = 0;
int pllout_b_used = 0;
for (auto port : ci->ports) {
PortInfo &pi = port.second;
if (pi.name == ctx->id("PLLOUTCOREA"))
pllout_a_used++;
if (pi.name == ctx->id("PLLOUTCOREB"))
pllout_b_used++;
if (pi.name == ctx->id("PLLOUTCORE"))
pllout_a_used++;
if (pi.name == ctx->id("PLLOUTGLOBALA"))
pllout_a_used++;
if (pi.name == ctx->id("PLLOUTGLOBALB"))
pllout_b_used++;
if (pi.name == ctx->id("PLLOUTGLOBAL"))
pllout_a_used++;
}
if (pllout_a_used > 1)
log_error("PLL '%s' is using multiple ports mapping to PLLOUT_A output of the PLL\n", ci->name.c_str(ctx));
if (pllout_b_used > 1)
log_error("PLL '%s' is using multiple ports mapping to PLLOUT_B output of the PLL\n", ci->name.c_str(ctx));
for (auto port : ci->ports) { for (auto port : ci->ports) {
PortInfo &pi = port.second; PortInfo &pi = port.second;
std::string newname = pi.name.str(ctx); std::string newname = pi.name.str(ctx);
@ -730,10 +754,20 @@ static void pack_special(Context *ctx)
newname = "PLLOUT_B"; newname = "PLLOUT_B";
if (pi.name == ctx->id("PLLOUTCORE")) if (pi.name == ctx->id("PLLOUTCORE"))
newname = "PLLOUT_A"; newname = "PLLOUT_A";
if (pi.name == ctx->id("PLLOUTGLOBALA"))
newname = "PLLOUT_A";
if (pi.name == ctx->id("PLLOUTGLOBALB"))
newname = "PLLOUT_B";
if (pi.name == ctx->id("PLLOUTGLOBAL"))
newname = "PLLOUT_A";
if (pi.name == ctx->id("PLLOUTGLOBALA") || pi.name == ctx->id("PLLOUTGLOBALB") || pi.name == ctx->id("PLLOUTGLOBAL"))
log_warning("PLL '%s' is using port %s but implementation does not actually "
"use the global clock output of the PLL\n", ci->name.c_str(ctx), pi.name.str(ctx).c_str());
if (pi.name == ctx->id("PACKAGEPIN")) { if (pi.name == ctx->id("PACKAGEPIN")) {
if (!is_pad) { if (!is_pad) {
log_error("PLL '%s' has a PACKAGEPIN but is not a PAD PLL", ci->name.c_str(ctx)); log_error("PLL '%s' has a PACKAGEPIN but is not a PAD PLL\n", ci->name.c_str(ctx));
} else { } else {
// We drop this port and instead place the PLL adequately below. // We drop this port and instead place the PLL adequately below.
pad_packagepin_net = port.second.net; pad_packagepin_net = port.second.net;
@ -743,7 +777,7 @@ static void pack_special(Context *ctx)
} }
if (pi.name == ctx->id("REFERENCECLK")) { if (pi.name == ctx->id("REFERENCECLK")) {
if (!is_core) if (!is_core)
log_error("PLL '%s' has a REFERENCECLK but is not a CORE PLL", ci->name.c_str(ctx)); log_error("PLL '%s' has a REFERENCECLK but is not a CORE PLL\n", ci->name.c_str(ctx));
} }
if (packed->ports.count(ctx->id(newname)) == 0) { if (packed->ports.count(ctx->id(newname)) == 0) {