diff --git a/gowin/arch.cc b/gowin/arch.cc
index 82b44f91..6fe40f76 100644
--- a/gowin/arch.cc
+++ b/gowin/arch.cc
@@ -553,27 +553,7 @@ void Arch::setDelayScaling(double scale, double offset)
     args.delayOffset = offset;
 }
 
-void Arch::addCellTimingCombIn(IdString cell, IdString port) { cellTiming[cell].portClasses[port] = TMG_COMB_INPUT; }
-
-void Arch::addCellTimingCombOut(IdString cell, IdString port) { cellTiming[cell].portClasses[port] = TMG_COMB_OUTPUT; }
-
-void Arch::addCellTimingRegIn(IdString cell, IdString port) { cellTiming[cell].portClasses[port] = TMG_REGISTER_INPUT; }
-
-void Arch::addCellTimingRegOut(IdString cell, IdString port)
-{
-    cellTiming[cell].portClasses[port] = TMG_REGISTER_OUTPUT;
-}
-
-void Arch::addCellTimingIO(IdString cell, IdString port)
-{
-    if (port == id_I) {
-        cellTiming[cell].portClasses[port] = TMG_ENDPOINT;
-    } else {
-        if (port == id_O) {
-            cellTiming[cell].portClasses[port] = TMG_STARTPOINT;
-        }
-    }
-}
+void Arch::addCellTimingClass(IdString cell, IdString port, TimingPortClass cls) {cellTiming[cell].portClasses[port] = cls;}
 
 void Arch::addCellTimingClock(IdString cell, IdString port) { cellTiming[cell].portClasses[port] = TMG_CLOCK_INPUT; }
 
@@ -2042,8 +2022,8 @@ void Arch::assignArchInfo()
 
             // add timing paths
             addCellTimingClock(cname, id_CLK);
-            addCellTimingRegIn(cname, id_CE);
-            addCellTimingRegIn(cname, id_LSR);
+            addCellTimingClass(cname, id_CE, TMG_REGISTER_INPUT);
+            addCellTimingClass(cname, id_LSR, TMG_REGISTER_INPUT);
             IdString ports[4] = {id_A, id_B, id_C, id_D};
             for (int i = 0; i < 4; i++) {
                 DelayPair setup =
@@ -2074,18 +2054,18 @@ void Arch::assignArchInfo()
             delay = delay + delayLookup(speed->lut.timings.get(), speed->lut.num_timings, id_fx_ofx1);
             addCellTimingDelay(cname, id_I0, id_OF, delay);
             addCellTimingDelay(cname, id_I1, id_OF, delay);
-            addCellTimingCombIn(cname, id_SEL);
+            addCellTimingClass(cname, id_SEL, TMG_COMB_INPUT);
             break;
         }
         case ID_IOB:
             /* FALLTHRU */
         case ID_IOBS:
-            addCellTimingIO(cname, id_I);
-            addCellTimingIO(cname, id_O);
+            addCellTimingClass(cname, id_I, TMG_ENDPOINT);
+            addCellTimingClass(cname, id_O, TMG_STARTPOINT);
             break;
         case ID_BUFS:
-            addCellTimingCombIn(cname, id_I);
-            addCellTimingCombOut(cname, id_O);
+            addCellTimingClass(cname, id_I, TMG_ENDPOINT);
+            addCellTimingClass(cname, id_O, TMG_STARTPOINT);
             break;
         default:
             break;
diff --git a/gowin/arch.h b/gowin/arch.h
index d02a2488..034e4b86 100644
--- a/gowin/arch.h
+++ b/gowin/arch.h
@@ -339,11 +339,7 @@ struct Arch : BaseArch<ArchRanges>
     void setDelayScaling(double scale, double offset);
 
     void addCellTimingClock(IdString cell, IdString port);
-    void addCellTimingIO(IdString cell, IdString port);
-    void addCellTimingCombIn(IdString cell, IdString port);
-    void addCellTimingCombOut(IdString cell, IdString port);
-    void addCellTimingRegIn(IdString cell, IdString port);
-    void addCellTimingRegOut(IdString cell, IdString port);
+    void addCellTimingClass(IdString cell, IdString port, TimingPortClass cls);
     void addCellTimingDelay(IdString cell, IdString fromPort, IdString toPort, DelayQuad delay);
     void addCellTimingSetupHold(IdString cell, IdString port, IdString clock, DelayPair setup, DelayPair hold);
     void addCellTimingClockToOut(IdString cell, IdString port, IdString clock, DelayQuad clktoq);