gowin: Remove unnecessary functions
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
This commit is contained in:
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3364a3b674
commit
1ebfe67daf
@ -553,27 +553,7 @@ void Arch::setDelayScaling(double scale, double offset)
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args.delayOffset = offset;
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args.delayOffset = offset;
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}
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}
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void Arch::addCellTimingCombIn(IdString cell, IdString port) { cellTiming[cell].portClasses[port] = TMG_COMB_INPUT; }
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void Arch::addCellTimingClass(IdString cell, IdString port, TimingPortClass cls) {cellTiming[cell].portClasses[port] = cls;}
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void Arch::addCellTimingCombOut(IdString cell, IdString port) { cellTiming[cell].portClasses[port] = TMG_COMB_OUTPUT; }
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void Arch::addCellTimingRegIn(IdString cell, IdString port) { cellTiming[cell].portClasses[port] = TMG_REGISTER_INPUT; }
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void Arch::addCellTimingRegOut(IdString cell, IdString port)
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{
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cellTiming[cell].portClasses[port] = TMG_REGISTER_OUTPUT;
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}
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void Arch::addCellTimingIO(IdString cell, IdString port)
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{
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if (port == id_I) {
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cellTiming[cell].portClasses[port] = TMG_ENDPOINT;
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} else {
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if (port == id_O) {
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cellTiming[cell].portClasses[port] = TMG_STARTPOINT;
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}
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}
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}
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void Arch::addCellTimingClock(IdString cell, IdString port) { cellTiming[cell].portClasses[port] = TMG_CLOCK_INPUT; }
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void Arch::addCellTimingClock(IdString cell, IdString port) { cellTiming[cell].portClasses[port] = TMG_CLOCK_INPUT; }
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@ -2042,8 +2022,8 @@ void Arch::assignArchInfo()
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// add timing paths
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// add timing paths
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addCellTimingClock(cname, id_CLK);
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addCellTimingClock(cname, id_CLK);
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addCellTimingRegIn(cname, id_CE);
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addCellTimingClass(cname, id_CE, TMG_REGISTER_INPUT);
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addCellTimingRegIn(cname, id_LSR);
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addCellTimingClass(cname, id_LSR, TMG_REGISTER_INPUT);
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IdString ports[4] = {id_A, id_B, id_C, id_D};
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IdString ports[4] = {id_A, id_B, id_C, id_D};
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for (int i = 0; i < 4; i++) {
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for (int i = 0; i < 4; i++) {
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DelayPair setup =
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DelayPair setup =
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@ -2074,18 +2054,18 @@ void Arch::assignArchInfo()
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delay = delay + delayLookup(speed->lut.timings.get(), speed->lut.num_timings, id_fx_ofx1);
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delay = delay + delayLookup(speed->lut.timings.get(), speed->lut.num_timings, id_fx_ofx1);
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addCellTimingDelay(cname, id_I0, id_OF, delay);
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addCellTimingDelay(cname, id_I0, id_OF, delay);
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addCellTimingDelay(cname, id_I1, id_OF, delay);
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addCellTimingDelay(cname, id_I1, id_OF, delay);
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addCellTimingCombIn(cname, id_SEL);
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addCellTimingClass(cname, id_SEL, TMG_COMB_INPUT);
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break;
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break;
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}
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}
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case ID_IOB:
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case ID_IOB:
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/* FALLTHRU */
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/* FALLTHRU */
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case ID_IOBS:
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case ID_IOBS:
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addCellTimingIO(cname, id_I);
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addCellTimingClass(cname, id_I, TMG_ENDPOINT);
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addCellTimingIO(cname, id_O);
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addCellTimingClass(cname, id_O, TMG_STARTPOINT);
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break;
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break;
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case ID_BUFS:
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case ID_BUFS:
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addCellTimingCombIn(cname, id_I);
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addCellTimingClass(cname, id_I, TMG_ENDPOINT);
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addCellTimingCombOut(cname, id_O);
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addCellTimingClass(cname, id_O, TMG_STARTPOINT);
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break;
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break;
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default:
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default:
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break;
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break;
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@ -339,11 +339,7 @@ struct Arch : BaseArch<ArchRanges>
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void setDelayScaling(double scale, double offset);
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void setDelayScaling(double scale, double offset);
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void addCellTimingClock(IdString cell, IdString port);
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void addCellTimingClock(IdString cell, IdString port);
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void addCellTimingIO(IdString cell, IdString port);
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void addCellTimingClass(IdString cell, IdString port, TimingPortClass cls);
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void addCellTimingCombIn(IdString cell, IdString port);
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void addCellTimingCombOut(IdString cell, IdString port);
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void addCellTimingRegIn(IdString cell, IdString port);
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void addCellTimingRegOut(IdString cell, IdString port);
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void addCellTimingDelay(IdString cell, IdString fromPort, IdString toPort, DelayQuad delay);
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void addCellTimingDelay(IdString cell, IdString fromPort, IdString toPort, DelayQuad delay);
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void addCellTimingSetupHold(IdString cell, IdString port, IdString clock, DelayPair setup, DelayPair hold);
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void addCellTimingSetupHold(IdString cell, IdString port, IdString clock, DelayPair setup, DelayPair hold);
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void addCellTimingClockToOut(IdString cell, IdString port, IdString clock, DelayQuad clktoq);
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void addCellTimingClockToOut(IdString cell, IdString port, IdString clock, DelayQuad clktoq);
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