diff --git a/machxo2/arch.h b/machxo2/arch.h
index df10d9b0..d05346f3 100644
--- a/machxo2/arch.h
+++ b/machxo2/arch.h
@@ -57,12 +57,12 @@ NPNR_PACKED_STRUCT(struct BelPortPOD {
 
 NPNR_PACKED_STRUCT(struct PipInfoPOD {
     LocationPOD src, dst;
-    int32_t src_idx, dst_idx;
+    int16_t src_idx, dst_idx;
     int16_t timing_class;
     int8_t tile_type;
     int8_t pip_type;
     int16_t lutperm_flags;
-    int16_t padding2;
+    int16_t padding;
 });
 
 inline bool is_lutperm_pip(int16_t flags) { return flags & 0x4000; }
diff --git a/machxo2/facade_import.py b/machxo2/facade_import.py
index 3747daea..8282e107 100644
--- a/machxo2/facade_import.py
+++ b/machxo2/facade_import.py
@@ -410,8 +410,8 @@ def write_database(family, dev_name, chip, rg, endianness):
             for arc in t.arcs:
                 write_loc(arc.srcWire.rel, "src")
                 write_loc(arc.sinkWire.rel, "dst")
-                bba.u32(arc.srcWire.id, "src_idx {}".format(get_wire_name(arc.srcWire.rel, arc.srcWire.id)))
-                bba.u32(arc.sinkWire.id, "dst_idx {}".format(get_wire_name(arc.sinkWire.rel, arc.sinkWire.id)))
+                bba.u16(arc.srcWire.id, "src_idx {}".format(get_wire_name(arc.srcWire.rel, arc.srcWire.id)))
+                bba.u16(arc.sinkWire.id, "dst_idx {}".format(get_wire_name(arc.sinkWire.rel, arc.sinkWire.id)))
                 src_name = get_wire_name(arc.srcWire.rel, arc.srcWire.id)
                 snk_name = get_wire_name(arc.sinkWire.rel, arc.sinkWire.id)
                 bba.u16(get_pip_class(src_name, snk_name), "timing_class")
@@ -419,7 +419,7 @@ def write_database(family, dev_name, chip, rg, endianness):
                 cls = arc.cls
                 bba.u8(cls, "pip_type")
                 bba.u16(arc.lutperm_flags, "lutperm_flags")
-                bba.u16(0, "padding2")
+                bba.u16(0, "padding")
 
         if len(t.wires) > 0:
             for wire_idx in range(len(t.wires)):