Add ice40 ICESTORM_LC bels
Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf
parent
d85f5d2285
commit
20d7cd0194
@ -23,13 +23,13 @@
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IdString belTypeToId(BelType type)
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{
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if (type == TYPE_A) return "A";
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if (type == TYPE_ICESTORM_LC) return "ICESTORM_LC";
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return IdString();
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}
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BelType belTypeFromId(IdString id)
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{
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if (id == "A") return TYPE_A;
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if (id == "ICESTORM_LC") return TYPE_ICESTORM_LC;
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return TYPE_NIL;
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}
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@ -37,15 +37,33 @@ BelType belTypeFromId(IdString id)
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IdString PortPinToId(PortPin type)
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{
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if (type == PIN_FOO) return "FOO";
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if (type == PIN_BAR) return "BAR";
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if (type == PIN_IN_0) return "IN_0";
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if (type == PIN_IN_1) return "IN_1";
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if (type == PIN_IN_2) return "IN_2";
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if (type == PIN_IN_3) return "IN_3";
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if (type == PIN_O ) return "O";
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if (type == PIN_LO ) return "LO";
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if (type == PIN_CIN ) return "CIN";
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if (type == PIN_COUT) return "COUT";
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if (type == PIN_CEN ) return "CEN";
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if (type == PIN_CLK ) return "CLK";
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if (type == PIN_SR ) return "SR";
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return IdString();
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}
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PortPin PortPinFromId(IdString id)
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{
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if (id == "FOO") return PIN_FOO;
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if (id == "BAR") return PIN_BAR;
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if (id == "IN_0") return PIN_IN_0;
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if (id == "IN_1") return PIN_IN_1;
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if (id == "IN_2") return PIN_IN_2;
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if (id == "IN_3") return PIN_IN_3;
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if (id == "O" ) return PIN_O;
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if (id == "LO" ) return PIN_LO;
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if (id == "CIN" ) return PIN_CIN;
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if (id == "COUT") return PIN_COUT;
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if (id == "CEN" ) return PIN_CEN;
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if (id == "CLK" ) return PIN_CLK;
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if (id == "SR" ) return PIN_SR;
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return PIN_NIL;
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}
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25
ice40/chip.h
25
ice40/chip.h
@ -35,7 +35,7 @@ struct DelayInfo
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enum BelType
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{
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TYPE_NIL,
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TYPE_A
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TYPE_ICESTORM_LC
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};
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IdString belTypeToId(BelType type);
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@ -44,8 +44,17 @@ BelType belTypeFromId(IdString id);
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enum PortPin
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{
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PIN_NIL,
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PIN_FOO = 1,
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PIN_BAR = 2
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PIN_IN_0,
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PIN_IN_1,
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PIN_IN_2,
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PIN_IN_3,
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PIN_O,
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PIN_LO,
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PIN_CIN,
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PIN_COUT,
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PIN_CEN,
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PIN_CLK,
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PIN_SR
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};
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IdString PortPinToId(PortPin type);
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@ -83,6 +92,16 @@ struct WireInfoPOD
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BelPortPOD *bels_downhill;
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};
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extern int num_bels_384;
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extern int num_bels_1k;
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extern int num_bels_5k;
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extern int num_bels_8k;
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extern BelInfoPOD bel_data_384[];
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extern BelInfoPOD bel_data_1k[];
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extern BelInfoPOD bel_data_5k[];
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extern BelInfoPOD bel_data_8k[];
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extern int num_wires_384;
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extern int num_wires_1k;
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extern int num_wires_5k;
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114
ice40/chipdb.py
114
ice40/chipdb.py
@ -7,10 +7,24 @@ dev_width = None
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dev_height = None
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num_wires = None
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tiles = dict()
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wire_uphill = dict()
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wire_downhill = dict()
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wire_bidir = dict()
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bel_name = list()
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bel_type = list()
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wire_uphill_belport = dict()
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wire_downhill_belports = dict()
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wire_names = dict()
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wire_names_r = dict()
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def cmp_wire_names(newname, oldname):
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return newname < oldname
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with open(sys.argv[1], "r") as f:
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mode = None
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@ -39,11 +53,35 @@ with open(sys.argv[1], "r") as f:
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mode = ("routing", int(line[3]))
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continue
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if line[0] == ".io_tile":
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tiles[(int(line[1]), int(line[2]))] = "io"
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mode = None
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continue
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if line[0] == ".logic_tile":
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tiles[(int(line[1]), int(line[2]))] = "logic"
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mode = None
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continue
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if line[0] == ".ramb_tile":
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tiles[(int(line[1]), int(line[2]))] = "ramb"
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mode = None
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continue
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if line[0] == ".ramt_tile":
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tiles[(int(line[1]), int(line[2]))] = "ramt"
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mode = None
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continue
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if (line[0][0] == ".") or (mode is None):
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mode = None
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continue
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if mode[0] == "net":
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wname = (int(line[0]), int(line[1]), line[2])
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wire_names[wname] = mode[1]
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if (mode[1] not in wire_names_r) or cmp_wire_names(wname, wire_names_r[mode[1]]):
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wire_names_r[mode[1]] = wname
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continue
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if mode[0] == "buffer":
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@ -68,16 +106,72 @@ with open(sys.argv[1], "r") as f:
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wire_bidir[wire_b].add(wire_b)
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continue
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def add_bel_input(bel, wire, port):
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if wire not in wire_downhill_belports:
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wire_downhill_belports[wire] = set()
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wire_downhill_belports[wire].add((bel, port))
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def add_bel_output(bel, wire, port):
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assert wire not in wire_uphill_belport
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wire_uphill_belport[wire] = (bel, port)
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def add_bel_lc(x, y, z):
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bel = len(bel_name)
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bel_name.append("%d_%d_lc%d" % (x, y, z))
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bel_type.append("ICESTORM_LC")
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wire_cen = wire_names[(x, y, "lutff_global/cen")]
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wire_clk = wire_names[(x, y, "lutff_global/clk")]
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wire_s_r = wire_names[(x, y, "lutff_global/s_r")]
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if z == 0:
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wire_cin = wire_names[(x, y, "carry_in_mux")]
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else:
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wire_cin = wire_names[(x, y, "lutff_%d/cout" % (z-1))]
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wire_in_0 = wire_names[(x, y, "lutff_%d/in_0" % z)]
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wire_in_1 = wire_names[(x, y, "lutff_%d/in_1" % z)]
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wire_in_2 = wire_names[(x, y, "lutff_%d/in_2" % z)]
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wire_in_3 = wire_names[(x, y, "lutff_%d/in_3" % z)]
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wire_out = wire_names[(x, y, "lutff_%d/out" % z)]
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wire_cout = wire_names[(x, y, "lutff_%d/cout" % z)]
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wire_lout = wire_names[(x, y, "lutff_%d/lout" % z)] if z < 7 else None
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add_bel_input(bel, wire_cen, "CEN")
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add_bel_input(bel, wire_clk, "CLK")
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add_bel_input(bel, wire_s_r, "SR")
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add_bel_input(bel, wire_cin, "CIN")
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add_bel_input(bel, wire_in_0, "IN_0")
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add_bel_input(bel, wire_in_1, "IN_1")
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add_bel_input(bel, wire_in_2, "IN_2")
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add_bel_input(bel, wire_in_3, "IN_3")
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add_bel_output(bel, wire_out, "O")
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add_bel_output(bel, wire_cout, "COUT")
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if wire_lout is not None:
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add_bel_output(bel, wire_lout, "LO")
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for tile_xy, tile_type in sorted(tiles.items()):
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if tile_type == "logic":
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for i in range(8):
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add_bel_lc(tile_xy[0], tile_xy[1], i)
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print('#include "chip.h"')
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print("int num_bels_%s = %d;" % (dev_name, num_wires))
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print("BelInfoPOD bel_data_%s[%d] = {" % (dev_name, num_wires))
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for bel in range(len(bel_name)):
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print(" {\"%s\", TYPE_%s}%s" % (bel_name[bel], bel_type[bel], "," if bel+1 < len(bel_name) else ""))
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print("};")
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wireinfo = list()
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for wire in range(num_wires):
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num_uphill = 0
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num_downhill = 0
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num_bidir = 0
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has_bel_uphill = False
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num_bels_downhill = 0
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if wire in wire_uphill:
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@ -98,12 +192,26 @@ for wire in range(num_wires):
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print(",\n".join([" {%d, 1.0}" % other_wire for other_wire in wire_bidir[wire]]))
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print("};")
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if wire in wire_downhill_belports:
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num_bels_downhill = len(wire_downhill_belports[wire])
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print("static BelPortPOD wire%d_downbels[] = {" % wire)
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print(",\n".join([" {%d, PIN_%s}" % it for it in wire_downhill_belports[wire]]))
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print("};")
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info = " {"
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info += "\"wire%d\", " % wire
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info += "\"%d_%d_%s\", " % wire_names_r[wire]
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info += "%d, %d, %d, " % (num_uphill, num_downhill, num_bidir)
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info += ("wire%d_uphill, " % wire) if num_uphill > 0 else "nullptr, "
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info += ("wire%d_downhill, " % wire) if num_downhill > 0 else "nullptr, "
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info += ("wire%d_bidir, " % wire) if num_bidir > 0 else "nullptr, "
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info += "%d, " % (num_bels_downhill)
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if wire in wire_uphill_belport:
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info += "{%d, PIN_%s}, " % wire_uphill_belport[wire]
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else:
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info += "{-1, PIN_NIL}, "
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info += ("wire%d_downbels" % wire) if num_bels_downhill > 0 else "nullptr"
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info += "}"
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wireinfo.append(info)
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