Enable counter tests and add RAM tests.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>

fpga_interchange/examples/tests/CMakeLists.txt

@@ -1,6 +1,6 @@
 add_subdirectory(wire)
 add_subdirectory(const_wire)
-# FIXME: re-enable counter test as soon as post placement validity check completes successfully.
+add_subdirectory(counter)
-#add_subdirectory(counter)
+add_subdirectory(ram)
 add_subdirectory(ff)
 add_subdirectory(lut)

fpga_interchange/examples/tests/ram/CMakeLists.txt

@@ -0,0 +1,10 @@
+add_interchange_test(
+    name ram_basys3
+    family ${family}
+    device xc7a35t
+    package cpg236
+    tcl run.tcl
+    xdc basys3.xdc
+    sources ram.v
+)
+

fpga_interchange/examples/tests/ram/basys3.pcf

@@ -0,0 +1,41 @@
+# basys3 100 MHz CLK
+set_io clk W5
+
+set_io tx A18
+set_io rx B18
+#
+# in[0:15] correspond with SW0-SW15 on the basys3
+set_io sw[0] V17
+set_io sw[1] V16
+set_io sw[2] W16
+set_io sw[3] W17
+set_io sw[4] W15
+set_io sw[5] V15
+set_io sw[6] W14
+set_io sw[7] W13
+set_io sw[8] V2
+set_io sw[9] T3
+set_io sw[10] T2
+set_io sw[11] R3
+set_io sw[12] W2
+set_io sw[13] U1
+set_io sw[14] T1
+set_io sw[15] R2
+
+# out[0:15] correspond with LD0-LD15 on the basys3
+set_io led[0] U16
+set_io led[1] E19
+set_io led[2] U19
+set_io led[3] V19
+set_io led[4] W18
+set_io led[5] U15
+set_io led[6] U14
+set_io led[7] V14
+set_io led[8] V13
+set_io led[9] V3
+set_io led[10] W3
+set_io led[11] U3
+set_io led[12] P3
+set_io led[13] N3
+set_io led[14] P1
+set_io led[15] L1

fpga_interchange/examples/tests/ram/basys3.xdc

@@ -0,0 +1,80 @@
+# basys3 100 MHz CLK
+set_property PACKAGE_PIN W5 [get_ports clk]
+
+set_property PACKAGE_PIN A18 [get_ports tx]
+set_property PACKAGE_PIN B18 [get_ports rx]
+#
+# in[0:15] correspond with SW0-SW15 on the basys3
+set_property PACKAGE_PIN V17 [get_ports sw[0]]
+set_property PACKAGE_PIN V16 [get_ports sw[1]]
+set_property PACKAGE_PIN W16 [get_ports sw[2]]
+set_property PACKAGE_PIN W17 [get_ports sw[3]]
+set_property PACKAGE_PIN W15 [get_ports sw[4]]
+set_property PACKAGE_PIN V15 [get_ports sw[5]]
+set_property PACKAGE_PIN W14 [get_ports sw[6]]
+set_property PACKAGE_PIN W13 [get_ports sw[7]]
+set_property PACKAGE_PIN V2  [get_ports sw[8]]
+set_property PACKAGE_PIN T3  [get_ports sw[9]]
+set_property PACKAGE_PIN T2  [get_ports sw[10]]
+set_property PACKAGE_PIN R3  [get_ports sw[11]]
+set_property PACKAGE_PIN W2  [get_ports sw[12]]
+set_property PACKAGE_PIN U1  [get_ports sw[13]]
+set_property PACKAGE_PIN T1  [get_ports sw[14]]
+set_property PACKAGE_PIN R2  [get_ports sw[15]]
+
+# out[0:15] correspond with LD0-LD15 on the basys3
+set_property PACKAGE_PIN U16 [get_ports led[0]]
+set_property PACKAGE_PIN E19 [get_ports led[1]]
+set_property PACKAGE_PIN U19 [get_ports led[2]]
+set_property PACKAGE_PIN V19 [get_ports led[3]]
+set_property PACKAGE_PIN W18 [get_ports led[4]]
+set_property PACKAGE_PIN U15 [get_ports led[5]]
+set_property PACKAGE_PIN U14 [get_ports led[6]]
+set_property PACKAGE_PIN V14 [get_ports led[7]]
+set_property PACKAGE_PIN V13 [get_ports led[8]]
+set_property PACKAGE_PIN V3  [get_ports led[9]]
+set_property PACKAGE_PIN W3  [get_ports led[10]]
+set_property PACKAGE_PIN U3  [get_ports led[11]]
+set_property PACKAGE_PIN P3  [get_ports led[12]]
+set_property PACKAGE_PIN N3  [get_ports led[13]]
+set_property PACKAGE_PIN P1  [get_ports led[14]]
+set_property PACKAGE_PIN L1  [get_ports led[15]]
+
+set_property IOSTANDARD LVCMOS33 [get_ports clk]
+
+set_property IOSTANDARD LVCMOS33 [get_ports tx]
+set_property IOSTANDARD LVCMOS33 [get_ports rx]
+#
+set_property IOSTANDARD LVCMOS33 [get_ports sw[0]]
+set_property IOSTANDARD LVCMOS33 [get_ports sw[1]]
+set_property IOSTANDARD LVCMOS33 [get_ports sw[2]]
+set_property IOSTANDARD LVCMOS33 [get_ports sw[3]]
+set_property IOSTANDARD LVCMOS33 [get_ports sw[4]]
+set_property IOSTANDARD LVCMOS33 [get_ports sw[5]]
+set_property IOSTANDARD LVCMOS33 [get_ports sw[6]]
+set_property IOSTANDARD LVCMOS33 [get_ports sw[7]]
+set_property IOSTANDARD LVCMOS33 [get_ports sw[8]]
+set_property IOSTANDARD LVCMOS33 [get_ports sw[9]]
+set_property IOSTANDARD LVCMOS33 [get_ports sw[10]]
+set_property IOSTANDARD LVCMOS33 [get_ports sw[11]]
+set_property IOSTANDARD LVCMOS33 [get_ports sw[12]]
+set_property IOSTANDARD LVCMOS33 [get_ports sw[13]]
+set_property IOSTANDARD LVCMOS33 [get_ports sw[14]]
+set_property IOSTANDARD LVCMOS33 [get_ports sw[15]]
+
+set_property IOSTANDARD LVCMOS33 [get_ports led[0]]
+set_property IOSTANDARD LVCMOS33 [get_ports led[1]]
+set_property IOSTANDARD LVCMOS33 [get_ports led[2]]
+set_property IOSTANDARD LVCMOS33 [get_ports led[3]]
+set_property IOSTANDARD LVCMOS33 [get_ports led[4]]
+set_property IOSTANDARD LVCMOS33 [get_ports led[5]]
+set_property IOSTANDARD LVCMOS33 [get_ports led[6]]
+set_property IOSTANDARD LVCMOS33 [get_ports led[7]]
+set_property IOSTANDARD LVCMOS33 [get_ports led[8]]
+set_property IOSTANDARD LVCMOS33 [get_ports led[9]]
+set_property IOSTANDARD LVCMOS33 [get_ports led[10]]
+set_property IOSTANDARD LVCMOS33 [get_ports led[11]]
+set_property IOSTANDARD LVCMOS33 [get_ports led[12]]
+set_property IOSTANDARD LVCMOS33 [get_ports led[13]]
+set_property IOSTANDARD LVCMOS33 [get_ports led[14]]
+set_property IOSTANDARD LVCMOS33 [get_ports led[15]]

fpga_interchange/examples/tests/ram/ram.v

@@ -0,0 +1,134 @@
+module ram0(
+    // Write port
+    input wrclk,
+    input [15:0] di,
+    input wren,
+    input [9:0] wraddr,
+    // Read port
+    input rdclk,
+    input rden,
+    input [9:0] rdaddr,
+    output reg [15:0] do);
+
+    (* ram_style = "block" *) reg [15:0] ram[0:1023];
+
+    initial begin
+        ram[0] = 16'b00000000_00000001;
+        ram[1] = 16'b10101010_10101010;
+        ram[2] = 16'b01010101_01010101;
+        ram[3] = 16'b11111111_11111111;
+        ram[4] = 16'b11110000_11110000;
+        ram[5] = 16'b00001111_00001111;
+        ram[6] = 16'b11001100_11001100;
+        ram[7] = 16'b00110011_00110011;
+        ram[8] = 16'b00000000_00000010;
+        ram[9] = 16'b00000000_00000100;
+    end
+
+    always @ (posedge wrclk) begin
+        if(wren == 1) begin
+            ram[wraddr] <= di;
+        end
+    end
+
+    always @ (posedge rdclk) begin
+        if(rden == 1) begin
+            do <= ram[rdaddr];
+        end
+    end
+
+endmodule
+
+module top (
+    input  wire clk,
+
+    input  wire rx,
+    output wire tx,
+
+    input  wire [15:0] sw,
+    output wire [15:0] led
+);
+    wire rden;
+    reg wren;
+    wire [9:0] rdaddr;
+    wire [9:0] wraddr;
+    wire [15:0] di;
+    wire [15:0] do;
+    ram0 ram(
+        .wrclk(clk),
+        .di(di),
+        .wren(wren),
+        .wraddr(wraddr),
+        .rdclk(clk),
+        .rden(rden),
+        .rdaddr(rdaddr),
+        .do(do)
+    );
+
+    reg [9:0] address_reg;
+    reg [15:0] data_reg;
+    reg [15:0] out_reg;
+
+    assign rdaddr = address_reg;
+    assign wraddr = address_reg;
+
+    // display_mode == 00 -> ram[address_reg]
+    // display_mode == 01 -> address_reg
+    // display_mode == 10 -> data_reg
+    wire [1:0] display_mode;
+
+    // input_mode == 00 -> in[9:0] -> address_reg
+    // input_mode == 01 -> in[7:0] -> data_reg[7:0]
+    // input_mode == 10 -> in[7:0] -> data_reg[15:8]
+    // input_mode == 11 -> data_reg -> ram[address_reg]
+    wire [1:0] input_mode;
+
+    // WE == 0 -> address_reg and data_reg unchanged.
+    // WE == 1 -> address_reg or data_reg is updated because on input_mode.
+    wire we;
+
+    assign display_mode[0] = sw[14];
+    assign display_mode[1] = sw[15];
+
+    assign input_mode[0] = sw[12];
+    assign input_mode[1] = sw[13];
+
+    assign we = sw[11];
+    assign led = out_reg;
+    assign di = data_reg;
+    assign rden = 1;
+
+    initial begin
+        address_reg = 10'b0;
+        data_reg = 16'b0;
+        out_reg = 16'b0;
+    end
+
+    always @ (posedge clk) begin
+        if(display_mode == 0) begin
+            out_reg <= do;
+        end else if(display_mode == 1) begin
+            out_reg <= address_reg;
+        end else if(display_mode == 2) begin
+            out_reg <= data_reg;
+        end
+
+        if(we == 1) begin
+            if(input_mode == 0) begin
+                address_reg <= sw[9:0];
+                wren <= 0;
+            end else if(input_mode == 1) begin
+                data_reg[7:0] <= sw[7:0];
+                wren <= 0;
+            end else if(input_mode == 2) begin
+                data_reg[15:8] <= sw[7:0];
+                wren <= 0;
+            end else if(input_mode == 3) begin
+                wren <= 1;
+            end
+        end
+    end
+
+    // Uart loopback
+    assign tx = rx;
+endmodule

fpga_interchange/examples/tests/ram/run.tcl

@@ -0,0 +1,17 @@
+yosys -import
+
+foreach src $::env(SOURCES) {
+    read_verilog $src
+}
+
+synth_xilinx -flatten -nolutram -nowidelut -nosrl -nocarry -nodsp
+techmap -map $::env(TECHMAP)
+
+# opt_expr -undriven makes sure all nets are driven, if only by the $undef
+# net.
+opt_expr -undriven
+opt_clean
+
+setundef -zero -params
+
+write_json $::env(OUT_JSON)