port ecp5 split slice to machxo2
This commit is contained in:
Lofty
myrtle
parent
b033b915a6
commit
235a575267
@ -95,6 +95,20 @@ Arch::Arch(ArchArgs args) : args(args)
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if (!package_info)
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log_error("Unsupported package '%s' for '%s'.\n", package_name, getChipName().c_str());
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tile_status.resize(chip_info->num_tiles);
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for (int i = 0; i < chip_info->num_tiles; i++) {
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auto &ts = tile_status.at(i);
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auto &tile_data = chip_info->tile_info[i];
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ts.boundcells.resize(chip_info->tiles[i].bel_data.size(), nullptr);
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for (auto &name : tile_data.tile_names) {
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if (strcmp(chip_info->tiletype_names[name.type_idx].get(), "PLC2") == 0) {
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// Is a logic tile
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ts.lts = new LogicTileStatus();
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break;
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}
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}
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}
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BaseArch::init_cell_types();
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BaseArch::init_bel_buckets();
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@ -470,12 +484,6 @@ DecalXY Arch::getPipDecal(PipId pip) const
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// ---------------------------------------------------------------
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bool Arch::isBelLocationValid(BelId bel, bool explain_invalid) const
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{
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// FIXME: Same deal as isValidBelForCell.
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return true;
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}
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const std::string Arch::defaultPlacer = "heap";
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const std::vector<std::string> Arch::availablePlacers = {"sa", "heap"};
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@ -381,6 +381,38 @@ struct Arch : BaseArch<ArchRanges>
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// inverse of the above for name->object mapping
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dict<IdString, int> id_to_x, id_to_y;
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enum LogicBELType
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{
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BEL_COMB = 0,
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BEL_FF = 1,
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BEL_RAMW = 2
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};
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static const int lc_idx_shift = 2;
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struct LogicTileStatus
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{
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// Per-SLICE valid and dirty bits
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struct SliceStatus
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{
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bool valid = true, dirty = true;
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} slices[4];
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// Per-tile legality check for control set legality
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bool tile_valid = true;
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bool tile_dirty = true;
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// Fast index from z-pos to cell
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std::array<CellInfo *, 8 * (1 << lc_idx_shift)> cells;
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};
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struct TileStatus
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{
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std::vector<CellInfo *> boundcells;
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LogicTileStatus *lts = nullptr;
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// TODO: use similar mechanism for DSP legality checking
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~TileStatus() { delete lts; }
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};
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mutable std::vector<TileStatus> tile_status;
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// Helpers
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template <typename Id> const TileTypePOD *tile_info(Id &id) const
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{
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@ -392,6 +424,11 @@ struct Arch : BaseArch<ArchRanges>
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return (bel.location.y * chip_info->width + bel.location.x) * max_loc_bels + bel.index;
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}
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template <typename Id> inline int tile_index(Id id) const
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{
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return id.location.y * chip_info->width + id.location.x;
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}
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// ---------------------------------------------------------------
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// Common Arch API. Every arch must provide the following methods.
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@ -624,6 +661,12 @@ struct Arch : BaseArch<ArchRanges>
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// Placer
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bool isBelLocationValid(BelId bel, bool explain_invalid = false) const override;
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// Helper function for above
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bool slices_compatible(LogicTileStatus *lts) const;
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void assign_arch_info_for_cell(CellInfo *ci);
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void assignArchInfo() override;
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static const std::string defaultPlacer;
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static const std::vector<std::string> availablePlacers;
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static const std::string defaultRouter;
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@ -143,6 +143,57 @@ struct NetInfo;
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struct ArchCellInfo : BaseClusterInfo
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{
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enum CombFlags : uint8_t
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{
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COMB_NONE = 0x00,
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COMB_CARRY = 0x01,
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COMB_LUTRAM = 0x02,
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COMB_MUX5 = 0x04,
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COMB_MUX6 = 0x08,
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COMB_RAM_WCKINV = 0x10,
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COMB_RAM_WREINV = 0x20,
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COMB_RAMW_BLOCK = 0x40,
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};
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enum FFFlags : uint8_t
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{
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FF_NONE = 0x00,
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FF_CLKINV = 0x01,
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FF_CEINV = 0x02,
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FF_CECONST = 0x04,
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FF_LSRINV = 0x08,
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FF_GSREN = 0x10,
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FF_ASYNC = 0x20,
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FF_M_USED = 0x40,
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};
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struct
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{
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uint8_t flags;
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IdString ram_wck, ram_wre;
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CellInfo *mux_fxad;
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} combInfo;
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struct
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{
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uint8_t flags;
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IdString clk_sig, lsr_sig, ce_sig, di_sig;
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} ffInfo;
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struct
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{
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bool is_pdp;
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// Are the outputs from a DP16KD registered (OUTREG)
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// or non-registered (NOREG)
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bool is_output_a_registered;
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bool is_output_b_registered;
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// Which timing information to use for a DP16KD. Depends on registering
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// configuration.
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IdString regmode_timing_id;
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} ramInfo;
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struct
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{
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bool is_clocked;
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IdString timing_id;
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} multInfo;
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};
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NEXTPNR_NAMESPACE_END
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349
machxo2/cells.cc
349
machxo2/cells.cc
@ -32,24 +32,73 @@ std::unique_ptr<CellInfo> create_machxo2_cell(Context *ctx, IdString type, std::
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name.empty() ? ctx->id("$nextpnr_" + type.str(ctx) + "_" + std::to_string(auto_idx++)) : ctx->id(name);
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auto new_cell = std::make_unique<CellInfo>(ctx, name_id, type);
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if (type == id_TRELLIS_SLICE) {
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if (type == id_TRELLIS_COMB) {
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new_cell->params[id_MODE] = std::string("LOGIC");
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new_cell->params[id_GSR] = std::string("ENABLED");
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new_cell->params[id_SRMODE] = std::string("LSR_OVER_CE");
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new_cell->params[id_CEMUX] = std::string("1");
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new_cell->params[id_CLKMUX] = std::string("0");
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new_cell->params[id_LSRMUX] = std::string("LSR");
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new_cell->params[id_LSRONMUX] = std::string("LSRMUX");
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new_cell->params[id_LUT0_INITVAL] = Property(0xFFFF, 16);
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new_cell->params[id_LUT1_INITVAL] = Property(0xFFFF, 16);
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new_cell->params[id_REGMODE] = std::string("FF");
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new_cell->params[id_REG0_SD] = std::string("1");
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new_cell->params[id_REG1_SD] = std::string("1");
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new_cell->params[id_REG0_REGSET] = std::string("SET");
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new_cell->params[id_REG1_REGSET] = std::string("SET");
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new_cell->params[id_CCU2_INJECT1_0] = std::string("YES");
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new_cell->params[id_CCU2_INJECT1_1] = std::string("YES");
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new_cell->params[id_WREMUX] = std::string("INV");
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new_cell->params[id_INITVAL] = Property(0, 16);
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new_cell->params[id_CCU2_INJECT1] = std::string("NO");
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new_cell->params[id_WREMUX] = std::string("WRE");
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new_cell->addInput(id_A);
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new_cell->addInput(id_B);
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new_cell->addInput(id_C);
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new_cell->addInput(id_D);
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new_cell->addInput(id_M);
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new_cell->addInput(id_F1);
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new_cell->addInput(id_FCI);
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new_cell->addInput(id_FXA);
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new_cell->addInput(id_FXB);
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new_cell->addInput(id_DI0);
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new_cell->addInput(id_DI1);
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new_cell->addInput(id_WD);
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new_cell->addInput(id_WAD0);
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new_cell->addInput(id_WAD1);
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new_cell->addInput(id_WAD2);
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new_cell->addInput(id_WAD3);
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new_cell->addInput(id_WRE);
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new_cell->addInput(id_WCK);
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new_cell->addOutput(id_F);
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new_cell->addOutput(id_FCO);
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new_cell->addOutput(id_OFX);
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} else if (type == id_TRELLIS_RAMW) {
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for (auto i : {id_A0, id_B0, id_C0, id_D0, id_A1, id_B1, id_C1, id_D1})
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new_cell->addInput(i);
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for (auto o : {id_WDO0, id_WDO1, id_WDO2, id_WDO3, id_WADO0, id_WADO1, id_WADO2, id_WADO3})
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new_cell->addOutput(o);
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} else if (type == id_TRELLIS_IO) {
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new_cell->params[id_DIR] = std::string("INPUT");
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new_cell->attrs[id_IO_TYPE] = std::string("LVCMOS33");
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new_cell->params[id_DATAMUX_ODDR] = std::string("PADDO");
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new_cell->params[id_DATAMUX_MDDR] = std::string("PADDO");
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new_cell->addInout(id_B);
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new_cell->addInput(id_I);
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new_cell->addInput(id_T);
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new_cell->addOutput(id_O);
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new_cell->addInput(id_IOLDO);
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new_cell->addInput(id_IOLTO);
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} else if (type == id_LUT4) {
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new_cell->params[id_INIT] = Property(0, 16);
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new_cell->addInput(id_A);
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new_cell->addInput(id_B);
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new_cell->addInput(id_C);
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new_cell->addInput(id_D);
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new_cell->addOutput(id_Z);
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} else if (type == id_CCU2C) {
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new_cell->params[id_INIT0] = Property(0, 16);
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new_cell->params[id_INIT1] = Property(0, 16);
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new_cell->params[id_INJECT1_0] = std::string("YES");
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new_cell->params[id_INJECT1_1] = std::string("YES");
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new_cell->addInput(id_CIN);
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new_cell->addInput(id_A0);
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new_cell->addInput(id_B0);
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@ -61,62 +110,9 @@ std::unique_ptr<CellInfo> create_machxo2_cell(Context *ctx, IdString type, std::
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new_cell->addInput(id_C1);
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new_cell->addInput(id_D1);
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new_cell->addInput(id_M0);
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new_cell->addInput(id_M1);
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new_cell->addInput(id_FCI);
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new_cell->addInput(id_FXA);
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new_cell->addInput(id_FXB);
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new_cell->addInput(id_CLK);
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new_cell->addInput(id_LSR);
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new_cell->addInput(id_CE);
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new_cell->addInput(id_DI0);
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new_cell->addInput(id_DI1);
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new_cell->addInput(id_WD0);
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new_cell->addInput(id_WD1);
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new_cell->addInput(id_WAD0);
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new_cell->addInput(id_WAD1);
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new_cell->addInput(id_WAD2);
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new_cell->addInput(id_WAD3);
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new_cell->addInput(id_WRE);
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new_cell->addInput(id_WCK);
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new_cell->addOutput(id_F0);
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new_cell->addOutput(id_Q0);
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new_cell->addOutput(id_F1);
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new_cell->addOutput(id_Q1);
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new_cell->addOutput(id_FCO);
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new_cell->addOutput(id_OFX0);
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new_cell->addOutput(id_OFX1);
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new_cell->addOutput(id_WDO0);
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new_cell->addOutput(id_WDO1);
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new_cell->addOutput(id_WDO2);
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new_cell->addOutput(id_WDO3);
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new_cell->addOutput(id_WADO0);
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new_cell->addOutput(id_WADO1);
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new_cell->addOutput(id_WADO2);
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new_cell->addOutput(id_WADO3);
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} else if (type == id_TRELLIS_IO) {
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new_cell->params[id_DIR] = std::string("INPUT");
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new_cell->attrs[id_IO_TYPE] = std::string("LVCMOS33");
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new_cell->addInout(id_B);
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new_cell->addInput(id_I);
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new_cell->addInput(id_EN);
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new_cell->addOutput(id_O);
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} else if (type == id_LUT4) {
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new_cell->params[id_INIT] = Property(0, 16);
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new_cell->addInput(id_A);
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new_cell->addInput(id_B);
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new_cell->addInput(id_C);
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new_cell->addInput(id_D);
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new_cell->addOutput(id_Z);
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new_cell->addOutput(id_S0);
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new_cell->addOutput(id_S1);
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new_cell->addOutput(id_COUT);
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} else {
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log_error("unable to create MachXO2 cell of type %s", type.c_str(ctx));
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}
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@ -124,6 +120,135 @@ std::unique_ptr<CellInfo> create_machxo2_cell(Context *ctx, IdString type, std::
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return new_cell;
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}
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static unsigned get_dram_init(const Context *ctx, const CellInfo *ram, int bit)
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{
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auto init_prop = get_or_default(ram->params, id_INITVAL, Property(0, 64));
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NPNR_ASSERT(!init_prop.is_string);
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const std::string &idata = init_prop.str;
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NPNR_ASSERT(idata.length() == 64);
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unsigned value = 0;
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for (int i = 0; i < 16; i++) {
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char c = idata.at(4 * i + bit);
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if (c == '1')
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value |= (1 << i);
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else
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NPNR_ASSERT(c == '0' || c == 'x');
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}
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return value;
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}
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void lut_to_comb(Context *ctx, CellInfo *lut)
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{
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lut->type = id_TRELLIS_COMB;
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lut->params[id_INITVAL] = get_or_default(lut->params, id_INIT, Property(0, 16));
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lut->params.erase(id_INIT);
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lut->renamePort(id_Z, id_F);
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}
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void dram_to_ramw_split(Context *ctx, CellInfo *ram, CellInfo *ramw)
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{
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if (ramw->hierpath == IdString())
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ramw->hierpath = ramw->hierpath;
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ram->movePortTo(ctx->id("WAD[0]"), ramw, id_D0);
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ram->movePortTo(ctx->id("WAD[1]"), ramw, id_B0);
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ram->movePortTo(ctx->id("WAD[2]"), ramw, id_C0);
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ram->movePortTo(ctx->id("WAD[3]"), ramw, id_A0);
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ram->movePortTo(ctx->id("DI[0]"), ramw, id_C1);
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ram->movePortTo(ctx->id("DI[1]"), ramw, id_A1);
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ram->movePortTo(ctx->id("DI[2]"), ramw, id_D1);
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ram->movePortTo(ctx->id("DI[3]"), ramw, id_B1);
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}
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void ccu2_to_comb(Context *ctx, CellInfo *ccu, CellInfo *comb, NetInfo *internal_carry, int i)
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{
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std::string ii = std::to_string(i);
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if (comb->hierpath == IdString())
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comb->hierpath = ccu->hierpath;
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comb->params[id_MODE] = std::string("CCU2");
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comb->params[id_INITVAL] = get_or_default(ccu->params, ctx->id("INIT" + ii), Property(0, 16));
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comb->params[id_CCU2_INJECT1] = str_or_default(ccu->params, ctx->id("INJECT1_" + ii), "YES");
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ccu->movePortTo(ctx->id("A" + ii), comb, id_A);
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ccu->movePortTo(ctx->id("B" + ii), comb, id_B);
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ccu->movePortTo(ctx->id("C" + ii), comb, id_C);
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ccu->movePortTo(ctx->id("D" + ii), comb, id_D);
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ccu->movePortTo(ctx->id("S" + ii), comb, id_F);
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if (i == 0) {
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ccu->movePortTo(id_CIN, comb, id_FCI);
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comb->connectPort(id_FCO, internal_carry);
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} else if (i == 1) {
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comb->connectPort(id_FCI, internal_carry);
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ccu->movePortTo(id_COUT, comb, id_FCO);
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} else {
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NPNR_ASSERT_FALSE("bad carry index!");
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}
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for (auto &attr : ccu->attrs)
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comb->attrs[attr.first] = attr.second;
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}
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void dram_to_comb(Context *ctx, CellInfo *ram, CellInfo *comb, CellInfo *ramw, int index)
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{
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if (comb->hierpath == IdString())
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comb->hierpath = ram->hierpath;
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comb->params[id_MODE] = std::string("DPRAM");
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comb->params[id_WREMUX] = str_or_default(ram->params, id_WREMUX, "WRE");
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comb->params[id_WCKMUX] = str_or_default(ram->params, id_WCKMUX, "WCK");
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unsigned permuted_init = 0;
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unsigned init = get_dram_init(ctx, ram, index);
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for (int i = 0; i < 16; i++) {
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int permuted_addr = 0;
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if (i & 1)
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permuted_addr |= 8;
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if (i & 2)
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permuted_addr |= 2;
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if (i & 4)
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permuted_addr |= 4;
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if (i & 8)
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permuted_addr |= 1;
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if (init & (1 << permuted_addr))
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permuted_init |= (1 << i);
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}
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comb->params[ctx->id("INITVAL")] = Property(permuted_init, 16);
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||||
|
||||
if (ram->ports.count(ctx->id("RAD[0]")))
|
||||
comb->connectPort(id_D, ram->ports.at(ctx->id("RAD[0]")).net);
|
||||
|
||||
if (ram->ports.count(ctx->id("RAD[1]")))
|
||||
comb->connectPort(id_B, ram->ports.at(ctx->id("RAD[1]")).net);
|
||||
|
||||
if (ram->ports.count(ctx->id("RAD[2]")))
|
||||
comb->connectPort(id_C, ram->ports.at(ctx->id("RAD[2]")).net);
|
||||
|
||||
if (ram->ports.count(ctx->id("RAD[3]")))
|
||||
comb->connectPort(id_A, ram->ports.at(ctx->id("RAD[3]")).net);
|
||||
|
||||
if (ram->ports.count(id_WRE))
|
||||
comb->connectPort(id_WRE, ram->ports.at(id_WRE).net);
|
||||
if (ram->ports.count(id_WCK))
|
||||
comb->connectPort(id_WCK, ram->ports.at(id_WCK).net);
|
||||
|
||||
ramw->connectPorts(id_WADO0, comb, id_WAD0);
|
||||
ramw->connectPorts(id_WADO1, comb, id_WAD1);
|
||||
ramw->connectPorts(id_WADO2, comb, id_WAD2);
|
||||
ramw->connectPorts(id_WADO3, comb, id_WAD3);
|
||||
|
||||
NPNR_ASSERT(index < 4);
|
||||
std::string ii = std::to_string(index);
|
||||
ramw->connectPorts(ctx->id("WDO" + ii), comb, id_WD);
|
||||
ram->movePortTo(ctx->id("DO[" + ii + "]"), comb, id_F);
|
||||
|
||||
for (auto &attr : ram->attrs)
|
||||
comb->attrs[attr.first] = attr.second;
|
||||
}
|
||||
|
||||
void lut_to_lc(const Context *ctx, CellInfo *lut, CellInfo *lc, bool no_dff)
|
||||
{
|
||||
lc->params[id_LUT0_INITVAL] = lut->params[id_INIT];
|
||||
@ -165,6 +290,82 @@ void dff_to_lc(Context *ctx, CellInfo *dff, CellInfo *lc, LutType lut_type)
|
||||
}
|
||||
}
|
||||
|
||||
void nxio_to_iob(Context *ctx, CellInfo *nxio, CellInfo *iob, pool<IdString> &todelete_cells) {}
|
||||
void nxio_to_tr(Context *ctx, CellInfo *nxio, CellInfo *trio, std::vector<std::unique_ptr<CellInfo>> &created_cells,
|
||||
pool<IdString> &todelete_cells)
|
||||
{
|
||||
if (nxio->type == ctx->id("$nextpnr_ibuf")) {
|
||||
trio->params[id_DIR] = std::string("INPUT");
|
||||
nxio->movePortTo(id_O, trio, id_O);
|
||||
} else if (nxio->type == ctx->id("$nextpnr_obuf")) {
|
||||
trio->params[id_DIR] = std::string("OUTPUT");
|
||||
nxio->movePortTo(id_I, trio, id_I);
|
||||
} else if (nxio->type == ctx->id("$nextpnr_iobuf")) {
|
||||
// N.B. tristate will be dealt with below
|
||||
NetInfo *i = nxio->getPort(id_I);
|
||||
if (i == nullptr || i->driver.cell == nullptr)
|
||||
trio->params[id_DIR] = std::string("INPUT");
|
||||
else {
|
||||
log_info("%s: %s.%s\n", ctx->nameOf(i), ctx->nameOf(i->driver.cell), ctx->nameOf(i->driver.port));
|
||||
trio->params[id_DIR] = std::string("BIDIR");
|
||||
}
|
||||
nxio->movePortTo(id_I, trio, id_I);
|
||||
nxio->movePortTo(id_O, trio, id_O);
|
||||
} else {
|
||||
NPNR_ASSERT(false);
|
||||
}
|
||||
NetInfo *donet = trio->ports.at(id_I).net, *dinet = trio->ports.at(id_O).net;
|
||||
|
||||
// Rename I/O nets to avoid conflicts
|
||||
if (donet != nullptr && donet->name == nxio->name)
|
||||
if (donet)
|
||||
ctx->renameNet(donet->name, ctx->id(donet->name.str(ctx) + "$TRELLIS_IO_OUT"));
|
||||
if (dinet != nullptr && dinet->name == nxio->name)
|
||||
if (dinet)
|
||||
ctx->renameNet(dinet->name, ctx->id(dinet->name.str(ctx) + "$TRELLIS_IO_IN"));
|
||||
|
||||
if (ctx->nets.count(nxio->name)) {
|
||||
int i = 0;
|
||||
IdString new_name;
|
||||
do {
|
||||
new_name = ctx->id(nxio->name.str(ctx) + "$rename$" + std::to_string(i++));
|
||||
} while (ctx->nets.count(new_name));
|
||||
if (ctx->nets.at(nxio->name).get())
|
||||
ctx->renameNet(ctx->nets.at(nxio->name).get()->name, new_name);
|
||||
}
|
||||
|
||||
// Create a new top port net for accurate IO timing analysis and simulation netlists
|
||||
if (ctx->ports.count(nxio->name)) {
|
||||
IdString tn_netname = nxio->name;
|
||||
NPNR_ASSERT(!ctx->nets.count(tn_netname));
|
||||
ctx->net_aliases.erase(tn_netname);
|
||||
NetInfo *toplevel_net = ctx->createNet(tn_netname);
|
||||
toplevel_net->name = tn_netname;
|
||||
trio->connectPort(id_B, toplevel_net);
|
||||
ctx->ports[nxio->name].net = toplevel_net;
|
||||
}
|
||||
|
||||
CellInfo *tbuf = net_driven_by(
|
||||
ctx, donet, [](const Context *ctx, const CellInfo *cell) { return cell->type == ctx->id("$_TBUF_"); },
|
||||
id_Y);
|
||||
if (tbuf) {
|
||||
tbuf->movePortTo(id_A, trio, id_I);
|
||||
// Need to invert E to form T
|
||||
std::unique_ptr<CellInfo> inv_lut = create_machxo2_cell(ctx, id_LUT4, trio->name.str(ctx) + "$invert_T");
|
||||
tbuf->movePortTo(id_E, inv_lut.get(), id_A);
|
||||
inv_lut->params[id_INIT] = Property(21845, 16);
|
||||
inv_lut->connectPorts(id_Z, trio, id_T);
|
||||
created_cells.push_back(std::move(inv_lut));
|
||||
|
||||
if (donet->users.entries() > 1) {
|
||||
for (auto user : donet->users)
|
||||
log_info(" remaining tristate user: %s.%s\n", user.cell->name.c_str(ctx), user.port.c_str(ctx));
|
||||
log_error("unsupported tristate IO pattern for IO buffer '%s', "
|
||||
"instantiate SB_IO manually to ensure correct behaviour\n",
|
||||
nxio->name.c_str(ctx));
|
||||
}
|
||||
ctx->nets.erase(donet->name);
|
||||
todelete_cells.insert(tbuf->name);
|
||||
}
|
||||
}
|
||||
|
||||
NEXTPNR_NAMESPACE_END
|
||||
|
||||
@ -41,12 +41,13 @@ std::unique_ptr<CellInfo> create_machxo2_cell(Context *ctx, IdString type, std::
|
||||
|
||||
// Return true if a cell is a LUT
|
||||
inline bool is_lut(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_LUT4; }
|
||||
inline bool is_carry(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_CCU2C; }
|
||||
inline bool is_dpram(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_TRELLIS_DPR16X4; }
|
||||
inline bool is_trellis_io(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_TRELLIS_IO; }
|
||||
|
||||
// Return true if a cell is a flipflop
|
||||
inline bool is_ff(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_TRELLIS_FF; }
|
||||
|
||||
inline bool is_lc(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_TRELLIS_SLICE; }
|
||||
|
||||
// Convert a LUT primitive to (part of) an GENERIC_SLICE, swapping ports
|
||||
// as needed. Set no_dff if a DFF is not being used, so that the output
|
||||
// can be reconnected
|
||||
@ -58,8 +59,15 @@ void lut_to_lc(const Context *ctx, CellInfo *lut, CellInfo *lc, bool no_dff = tr
|
||||
// ignored
|
||||
void dff_to_lc(Context *ctx, CellInfo *dff, CellInfo *lc, LutType lut_type = LutType::Normal);
|
||||
|
||||
// Convert a nextpnr IO buffer to a GENERIC_IOB
|
||||
void nxio_to_iob(Context *ctx, CellInfo *nxio, CellInfo *sbio, pool<IdString> &todelete_cells);
|
||||
// Convert a nextpnr IO buffer to a TRELLIS_IO
|
||||
void nxio_to_tr(Context *ctx, CellInfo *nxio, CellInfo *trio, std::vector<std::unique_ptr<CellInfo>> &created_cells,
|
||||
pool<IdString> &todelete_cells);
|
||||
|
||||
void lut_to_comb(Context *ctx, CellInfo *lut);
|
||||
void dram_to_ramw_split(Context *ctx, CellInfo *ram, CellInfo *ramw);
|
||||
void ccu2_to_comb(Context *ctx, CellInfo *ccu, CellInfo *comb, NetInfo *internal_carry, int i);
|
||||
void dram_to_comb(Context *ctx, CellInfo *ram, CellInfo *comb, CellInfo *ramw, int index);
|
||||
|
||||
|
||||
NEXTPNR_NAMESPACE_END
|
||||
|
||||
|
||||
@ -15,6 +15,8 @@ X(FXB)
|
||||
X(CLK)
|
||||
X(LSR)
|
||||
X(CE)
|
||||
X(CEA)
|
||||
X(CEW)
|
||||
X(DI0)
|
||||
X(DI1)
|
||||
X(WD0)
|
||||
@ -131,3 +133,32 @@ X(place)
|
||||
X(placer)
|
||||
X(route)
|
||||
X(router)
|
||||
|
||||
|
||||
X(TRELLIS_COMB)
|
||||
X(TRELLIS_RAMW)
|
||||
X(WD)
|
||||
X(OFX)
|
||||
X(F)
|
||||
X(M)
|
||||
|
||||
X(CCU2C)
|
||||
X(CCU2_INJECT1)
|
||||
X(INJECT1_0)
|
||||
X(INJECT1_1)
|
||||
X(TRELLIS_DPR16X4)
|
||||
X(INITVAL)
|
||||
X(INIT0)
|
||||
X(INIT1)
|
||||
|
||||
X(DATAMUX_ODDR)
|
||||
X(DATAMUX_MDDR)
|
||||
X(CIN)
|
||||
X(S0)
|
||||
X(S1)
|
||||
X(COUT)
|
||||
|
||||
X(E)
|
||||
X(Y)
|
||||
|
||||
X(WCKMUX)
|
||||
@ -481,7 +481,7 @@ def main():
|
||||
constids["PIO"] = constids["TRELLIS_IO"]
|
||||
|
||||
chip = pytrellis.Chip(dev_names[args.device])
|
||||
rg = pytrellis.make_optimized_chipdb(chip, split_slice_mode=False)
|
||||
rg = pytrellis.make_optimized_chipdb(chip, split_slice_mode=True)
|
||||
max_row = chip.get_max_row()
|
||||
max_col = chip.get_max_col()
|
||||
process_pio_db(rg, args.device)
|
||||
|
||||
1390
machxo2/pack.cc
1390
machxo2/pack.cc
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue
Block a user