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cyclonev: Fix some archcheck fails

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Signed-off-by: gatecat <gatecat@ds0.me>
This commit is contained in:
gatecat 2021-05-03 15:19:52 +01:00
parent 431c4cec9f
commit 24af19b58d
3 changed files with 6 additions and 4 deletions
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2
cyclonev/arch.cc
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@ -249,6 +249,7 @@ WireId Arch::add_wire(int x, int y, IdString name, uint64_t flags)
z++;
wires[id].name_override = name;
wires[id].flags = flags;
npnr_wirebyname[full_name] = id;
return id;
}
}
@ -263,6 +264,7 @@ PipId Arch::add_pip(WireId src, WireId dst)
void Arch::add_bel_pin(BelId bel, IdString pin, PortType dir, WireId wire)
{
auto &b = bel_data(bel);
NPNR_ASSERT(!b.pins.count(pin));
b.pins[pin].dir = dir;
b.pins[pin].wire = wire;

2
cyclonev/arch.h
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@ -278,7 +278,7 @@ struct Arch : BaseArch<ArchRanges>
WireId getWireByName(IdStringList name) const override;
IdStringList getWireName(WireId wire) const override;
DelayQuad getWireDelay(WireId wire) const override { return DelayQuad(0); }
const std::vector<BelPin> &getWireBelPins(WireId wire) const override { return empty_belpin_list; }
const std::vector<BelPin> &getWireBelPins(WireId wire) const override { return wires.at(wire).bel_pins; }
AllWireRange getWires() const override { return AllWireRange(wires); }
// -------------------------------------------------

6
cyclonev/lab.cc
View File

@ -72,8 +72,8 @@ static void create_alm(Arch *arch, int x, int y, int z, uint32_t lab_idx)
// Carry/share chain
arch->add_bel_pin(bel, id_CIN, PORT_IN, carry_in);
arch->add_bel_pin(bel, id_SHAREIN, PORT_IN, share_in);
arch->add_bel_pin(bel, id_CIN, PORT_OUT, carry_in);
arch->add_bel_pin(bel, id_SHAREIN, PORT_OUT, share_out);
arch->add_bel_pin(bel, id_COUT, PORT_OUT, carry_out);
arch->add_bel_pin(bel, id_SHAREOUT, PORT_OUT, share_out);
// Combinational output
WireId comb_out = arch->add_wire(x, y, arch->id(stringf("COMBOUT[%d]", z * 2 + i)));
arch->add_bel_pin(bel, id_COMBOUT, PORT_OUT, comb_out);
@ -93,7 +93,7 @@ static void create_alm(Arch *arch, int x, int y, int z, uint32_t lab_idx)
sel_aclr[i] = arch->add_wire(x, y, arch->id(stringf("ACLR%c[%d]", i ? 'B' : 'T', z)));
sel_ef[i] = arch->add_wire(x, y, arch->id(stringf("%cEF[%d]", i ? 'B' : 'T', z)));
// Muxes - three CLK/ENA per LAB, two ACLR
for (int j = 0; j < 3; i++) {
for (int j = 0; j < 3; j++) {
arch->add_pip(lab.clk_wires[j], sel_clk[i]);
arch->add_pip(lab.ena_wires[j], sel_ena[i]);
if (j < 2)